CN103078596B - Fully-differential low-power-consumption low-noise amplifier - Google Patents
Fully-differential low-power-consumption low-noise amplifier Download PDFInfo
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Abstract
The invention discloses a fully-differential low-power-consumption low-noise amplifier. The amplifier comprises a common-source amplifier and a common-grid amplifier, wherein the common-source amplifier comprises a first N-type metallic oxide transistor and a second N-type metallic oxide transistor, a first P-type metallic oxide transistor, a second P type metallic oxide transistor, a first resistor, a second resistor, fifth to eighth resistors, and first to fifth capacitors; and the common-grid amplifier comprises a third P-type metallic oxide transistor, a fourth P type metallic oxide transistor, a third resistor and a fourth resistor. According to the low-noise amplifier with the structure, the quiescent bias currents of the N-type metallic oxide transistors and the P-type metallic oxide transistors are multiplexed; and meanwhile, the structure has the function of counteracting noise, so that the low-noise amplifier with the structure has the functions of low power consumption and low noise coefficient.
Description
Technical field
The present invention relates to a kind of amplifier, specifically, relate to a kind of Fully-differential low-power-consumptiolow-noise low-noise amplifier.Background technology
Low noise amplifier is the first order active circuit being positioned at radiofrequency receiving chip, considers from whole receiver, and noise factor determines primarily of the noise factor of the module of radio-frequency front-end.Therefore, in order to restraint speckle is on the impact of subsequent conditioning circuit, low noise amplifier should have relatively low noise factor.Low noise amplifier also provides certain gain, the weak radio-frequency signal that amplifying antenna receives, and meets the requirement of subsequent conditioning circuit to gain.Along with multi-transceiver technology and complex modulation technology are applied in wireless telecommunications more and more, the requirement of receiver various performance parameters is also improved gradually.Because MOS transistor is subject to the restriction of cut-off frequency, be difficult to take the design tactics in some low-frequency channels in radio circuit.The technology such as such as feedback, mutual conductance bootstrapping.The impact of ghost effect should be taken into full account when carrying out radio circuit design.
According to the structure of low noise amplifier, common-source stage low noise amplifier can be divided into and be total to grid level low noise amplifier.For common-source stage low noise amplifier, in order to the input in radiofrequency signal realizes impedance matching, the general structure adopting source degeneration inductance, by the source electrode of common-source stage amplifier by an inductance ground connection.Such structure can provide certain gain and lower noise factor, but due to passive inductance on the low noise amplifier employing sheet of this structure, integrated level is affected.The Q value of inductance also can produce larger impact to the performance of circuit, is unfavorable on sheet integrated.Another kind of common-source stage low noise amplifier adopts the form of resistance feedback to realize impedance matching, by a degenerative resistance by the signal feedback of output to input.According to Miller effect, feedback resistance equivalence does impedance matching to the internal resistance of input and signal source.This low noise amplifier has the effect of noise suppressed, has lower noise factor and certain gain.The shortcoming of this structure is that the stability of feedback resistance to loop proposes challenge.
For the low noise amplifier of common grid level, radiofrequency signal inputs from the source electrode of MOS transistor.Regulate the transconductance value of grid level amplifier altogether, can impedance matching be realized.Because the mutual conductance of common grid level amplifier is relatively fixing, not easily realize high gain, therefore adopt the common-source stage amplifier radio frequency signal of another branch road to amplify.The low noise amplifier of this common-source stage altogether grid level has the function of noise cancellation, can in output offsets grid level amplifier altogether the channel noise that produces of bank tube altogether, therefore there is lower noise factor and certain gain.But the low-noise factor that this structure realizes is with the power consumption of circuit in return, the power consumption of this common-source stage altogether grid level low noise amplifier is larger.Therefore, should at noise factor during Design Low Noise Amplifier, compromise in the aspect such as gain and power consumption.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide a kind of Fully-differential low-power-consumptiolow-noise low-noise amplifier, carry out multiplexing to the quiescent bias current of N-type MOS transistor and P type MOS transistor, there is the function of low-power consumption and noise cancellation.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of Fully-differential low-power-consumptiolow-noise low-noise amplifier, and this amplifier comprises common-source stage amplifier and is total to grid level amplifier; Wherein, common-source stage amplifier comprises the first and second N-type MOS transistors, the first and second P type MOS transistors, the first resistance, the second resistance, the 5th to the 8th resistance and the first to the 5th electric capacity; Grid level amplifier comprises the third and fourth P type MOS transistor and the third and fourth resistance altogether;
The bottom crown of the positive termination first of differential input signal and the 3rd electric capacity and the source electrode of the 4th P type MOS transistor; Differential input signal negative terminal connect second and the 4th electric capacity bottom crown and the source electrode of the 3rd P type MOS transistor; The top crown of the first and second electric capacity connects the grid of the first and second N-type MOS transistors respectively; The top crown of the first and second electric capacity connects again the anode of the 7th and the 8th resistance respectively, and the negative terminal of the 7th and the 8th resistance provides biased by the first bias voltage; Source electrode all ground connection of the first and second N-type MOS transistors; The drain electrode of the first N-type MOS transistor connects the drain electrode and first and the 3rd anode of resistance of a P type MOS transistor; The drain electrode of the second N-type MOS transistor connects the drain electrode and second and the 4th anode of resistance of the 2nd P type MOS transistor; First resistance negative terminal is connected with the negative terminal of the second resistance, and connects the top crown of the 5th electric capacity; The bottom crown ground connection of the 5th electric capacity; The negative terminal of the 3rd resistance connects the drain electrode of the 3rd P type MOS transistor, and as difference output negative terminal; The negative terminal of the 4th resistance connects the drain electrode of the 4th P type MOS transistor, and as difference output anode; The grid of the third and fourth P type MOS transistor connects, and connects the negative terminal of the 5th and the 6th resistance respectively, provides biased by the second bias voltage; The anode of the 5th resistance is connected with the top crown of the 3rd electric capacity, and connects the grid of a P type MOS transistor; The anode of the 6th resistance is connected with the top crown of the 4th electric capacity, and connects the grid of the 2nd P type MOS transistor; The source electrode of the first and second P type MOS transistors connects supply voltage.
Beneficial effect: low noise amplifier of the present invention achieves the function of low-noise factor while realizing low-power consumption.N-type MOS transistor and P type MOS transistor are placed in the middle of the direct current biasing of same road by low noise amplifier of the present invention, realize current multiplexing, improve current utilization rate, save power consumption.On the basis of this current multiplexing structure, third and fourth P type MOS transistor is as the amplifier tube of common grid level, their channel noise produces the noise voltage of common mode respectively at difference output end, therefore the noise factor of the third and fourth P type MOS transistor to system is not contributed, and achieves the function of noise cancellation and low-noise factor.
Accompanying drawing explanation
Fig. 1 is circuit diagram of the present invention;
Fig. 2 is the simulation result figure of low noise amplifier noise factor of the present invention;
Fig. 3 is the simulation result figure of low noise amplifier gain of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
As shown in Figure 1, a kind of Fully-differential low-power-consumptiolow-noise low-noise amplifier of the present invention, comprises common-source stage amplifier and is total to grid level amplifier; Wherein, common-source stage amplifier comprises the first and second N-type MOS transistor N1 and N2, the first and second P type MOS transistor P1 and P2, the first resistance R1, the second resistance R2, the 5th to the 8th resistance R5-R8 and first to the 5th electric capacity C1-C5; Grid level amplifier comprises the third and fourth P type MOS transistor P3 and P4 and the third and fourth resistance R3 and R4 altogether;
Differential input signal anode Vin+ connect first and the 3rd electric capacity C1 and C3 bottom crown and the source electrode of the 4th P type MOS transistor P4; Differential input signal negative terminal Vin-connect second and the 4th electric capacity C2 and C4 bottom crown and the source electrode of the 3rd P type MOS transistor P3; The top crown of the first and second electric capacity C1 and C2 connects the grid of the first and second N-type MOS transistor N1 and N2 respectively; The top crown of the first and second electric capacity C1 and C2 connects again the anode of the 7th and the 8th resistance R7 and R8 respectively, and the negative terminal of the 7th and the 8th resistance R7 and R8 provides biased by the first bias voltage Vb1; Source electrode all ground connection of the first and second N-type MOS transistor N1 and N2; The drain electrode of the first N-type MOS transistor N1 connects the drain electrode and first and the 3rd anode of resistance R1 and R3 of a P type MOS transistor P1; The drain electrode of the second N-type MOS transistor N2 connects the drain electrode and second and the 4th anode of resistance R2 and R4 of the 2nd P type MOS transistor P2; First resistance R1 negative terminal is connected with the negative terminal of the second resistance R2, and connects the top crown of the 5th electric capacity C5; The bottom crown ground connection of the 5th electric capacity C5; The negative terminal of the 3rd resistance R3 connects the drain electrode of the 3rd P type MOS transistor P3, and as difference output negative terminal Vout-; The negative terminal of the 4th resistance R4 connects the drain electrode of the 4th P type MOS transistor P4, and as difference output anode Vout+; The grid of the third and fourth P type MOS transistor P3 with P4 is connected, and connects the negative terminal of the 5th and the 6th resistance R5 and R6 respectively, provides biased by the second bias voltage Vb2; The anode of the 5th resistance R5 is connected with the top crown of the 3rd electric capacity C3, and connects the grid of a P type MOS transistor P1; The anode of the 6th resistance R6 is connected with the top crown of the 4th electric capacity C4, and connects the grid of the 2nd P type MOS transistor P2; The source electrode of the first and second P type MOS transistor P1 with P2 is connected supply voltage.
Above-mentioned Fully-differential low-power-consumptiolow-noise low-noise amplifier, counteracts the noise that the third and fourth P type MOS transistor P3 and P4 in common grid level amplifier produces at output.The principle of lower surface analysis low noise amplifier noise cancellation of the present invention.The channel noise electric current produced when 3rd P type MOS transistor P3 works can think a noise current source, and flow into from its drain electrode, source electrode flows out.The noise current produced flows through first and the 3rd resistance R1 and R3, therefore at the noise voltage that Vout-holds generation one negative.Noise current flows out from its source electrode (i.e. Vin-end), flows through through the antenna impedance of matching network equivalence to input, therefore at the noise voltage that Vin-holds generation one positive.Namely Vin-end connects the source electrode of the 3rd P type MOS transistor P3, connects again the grid of the second N-type MOS transistor N2.Therefore, 3rd P type MOS transistor P3 holds the positive noise voltage of generation one oppositely to amplify through the second N-type MOS transistor N2 again at Vin-, a negative noise voltage is produced again in the drain electrode of the second N-type MOS transistor N2, this negative noise voltage finally exports at Vout+ end, this is that the ac voltage signal of the 4th resistance R4 positive and negative terminal is substantially identical because the channel resistance of the 4th P type MOS transistor P4 is very large.In sum, the 3rd P type MOS transistor P3 is in the same way at the noise voltage that difference output end produces, and similarly, the 4th P type MOS transistor P4 is also in the same way at the noise voltage that difference output end produces.During design, keep the gain balance of grid level and common-source stage amplifier altogether, the noise voltage that such third and fourth P type MOS transistor P3 and P4 produces at output is respectively common mode characteristic, does not contribute the noise factor of system.Such structure achieves the function of noise cancellation.Can find out according to Fig. 1, the first resistance and the second resistance R1 and R2 are as the load resistance of common-source stage amplifier.First resistance R1 and the 3rd resistance R3 sum and the second resistance R2 and the 4th resistance R4 sum are as the load resistance of common grid level.Therefore, the load impedance of grid level is greater than the load impedance of common-source stage altogether, during design, keeps the mutual conductance of common-source stage to be greater than the mutual conductance of common grid level, makes common-source stage and the gain balance being total to grid level.
The quiescent bias current of low noise amplifier of the present invention to N-type MOS transistor and P type MOS transistor carries out multiplexing, achieves the function of low-power consumption.During design by flow through first and the 3rd the bias current of P type MOS transistor P1 and P3 flow through the first N-type MOS transistor N1, by flow through second and the 4th the bias current of P type MOS transistor P2 and P4 flow through the second N-type MOS transistor N2, achieve the function of current multiplexing, save power consumption.
Illustrate that the present invention has the feature of low-noise factor and low-power consumption below by emulation.
Adopt
virtuoso simulation software emulates low noise amplifier noise factor of the present invention and gain.As shown in Figure 2, abscissa represents the frequency of input radio frequency signal to noise factor simulation result, unit Hz, and ordinate represents noise factor, unit dB.When low noise amplifier of the present invention is operated near 2G, noise factor is less than 1.8dB.As shown in Figure 3, abscissa represents the frequency of input radio frequency signal to gain simulation result, unit Hz, and ordinate represents gain, unit dB.The gain of low noise amplifier of the present invention can reach 25dB.The power consumption of low noise amplifier of the present invention only has 1.6mW.
Claims (1)
1. a Fully-differential low-power-consumptiolow-noise low-noise amplifier, is characterized in that: this amplifier comprises common-source stage amplifier and is total to grid level amplifier; Wherein, common-source stage amplifier comprises the first and second N-type MOS transistors (N1 and N2), the first and second P type MOS transistors (P1 and P2), the first resistance (R1), the second resistance (R2), the 5th to the 8th resistance (R5-R8) and the first to the 5th electric capacity (C1-C5); Grid level amplifier comprises the third and fourth P type MOS transistor (P3 and P4) and the third and fourth resistance (R3 and R4) altogether; Differential input signal anode (Vin+) connect first and the 3rd electric capacity (C1 and C3) bottom crown and the source electrode of the 4th P type MOS transistor (P4); Differential input signal negative terminal (Vin-) connect second and the 4th electric capacity (C2 and C4) bottom crown and the source electrode of the 3rd P type MOS transistor (P3); The top crown of the first and second electric capacity (C1 and C2) connects the grid of the first and second N-type MOS transistors (N1 and N2) respectively; The top crown of the first and second electric capacity (C1 and C2) connects again the anode of the 7th and the 8th resistance (R7 and R8) respectively, and the negative terminal of the 7th and the 8th resistance (R7 and R8) provides biased by the first bias voltage (Vb1); Source electrode all ground connection of the first and second N-type MOS transistors (N1 and N2); The drain electrode of the first N-type MOS transistor (N1) connects the drain electrode and first and the 3rd anode of resistance (R1 and R3) of a P type MOS transistor (P1); The drain electrode of the second N-type MOS transistor (N2) connects the drain electrode and second and the 4th anode of resistance (R2 and R4) of the 2nd P type MOS transistor (P2); First resistance (R1) negative terminal is connected with the negative terminal of the second resistance (R2), and connects the top crown of the 5th electric capacity (C5); The bottom crown ground connection of the 5th electric capacity (C5); The negative terminal of the 3rd resistance (R3) connects the drain electrode of the 3rd P type MOS transistor (P3), and as difference output negative terminal (Vout-); The negative terminal of the 4th resistance (R4) connects the drain electrode of the 4th P type MOS transistor (P4), and as difference output anode (Vout+); The grid of the third and fourth P type MOS transistor (P3 with P4) is all connected with the second bias voltage (Vb2), there is provided biased by described second bias voltage (Vb2), and connect the negative terminal of the 5th and the 6th resistance (R5 and R6) respectively; The anode of the 5th resistance (R5) is connected with the top crown of the 3rd electric capacity (C3), and connects the grid of a P type MOS transistor (P1); The anode of the 6th resistance (R6) is connected with the top crown of the 4th electric capacity (C4), and connects the grid of the 2nd P type MOS transistor (P2); The source electrode of the first and second P type MOS transistors (P1 with P2) is connected supply voltage.
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| CN104348430B (en) * | 2013-07-30 | 2018-02-09 | 上海东软载波微电子有限公司 | Low-noise amplifier and chip |
| CN110971198B (en) * | 2018-09-29 | 2024-04-26 | 天津大学青岛海洋技术研究院 | Radio frequency low noise amplifier design with high gain |
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| US20110109392A1 (en) * | 2009-11-09 | 2011-05-12 | Electronics And Telecommunications Research Institute | Low noise amplifier |
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| US8339205B1 (en) * | 2009-07-14 | 2012-12-25 | Marvell International Ltd. | Low power wide-band amplifier with reused current |
| CN101656516A (en) * | 2009-07-23 | 2010-02-24 | 复旦大学 | Full-difference CMOS ultra wide band low-noise amplifier |
| CN101820251A (en) * | 2010-05-17 | 2010-09-01 | 北京大学 | Ultra-low power consumption low-noise amplifier structure and preparation method thereof |
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