CN102916666B - A kind of broadband programmable gain amplifier - Google Patents
A kind of broadband programmable gain amplifier Download PDFInfo
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- CN102916666B CN102916666B CN201110219918.1A CN201110219918A CN102916666B CN 102916666 B CN102916666 B CN 102916666B CN 201110219918 A CN201110219918 A CN 201110219918A CN 102916666 B CN102916666 B CN 102916666B
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Abstract
The invention discloses a kind of broadband programmable gain amplifier.This amplifier comprises: adopt the input buffer stage of fully differential source follower structure, adopt the 1dB resistance attenuator of the R-2R ladder shaped resistance structure of symmetrical configuration fully differential form and adopt the variable gain amplifier of source degeneracy and current-mode combined technology; The input of described input buffer stage is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described 1dB resistance attenuator; The output of described 1dB resistance attenuator is connected with the input of described variable gain amplifier; The output of described variable gain amplifier is the output of differential signal, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs.The broadband programmable gain amplifier that this programme provides has the higher linearity, can effectively reduce distorted signals.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly relate to a kind of broadband programmable gain amplifier.
Background technology
Along with developing rapidly of Communications Market, radio communication has entered the epoch of high speed data transfer, and wider frequency band effectively will improve message transmission rate, especially short-range wireless high-speed transmission.The Ultra-wideband Communication Technology being operated in 3.1-10.6GHz frequency range that FCC announced in 2002 is as a kind of unconventional, novel Radio Transmission Technology, adopt extremely wide bandwidth (being greater than 500MHz) to transmit information, there is the features such as transmission rate is high, spatial frequency spectrum efficiency is high, system is simple and easy, low in energy consumption.At present, Ultra-wideband Communication Technology is just being widely used in the short-distance wireless high-speed transfer fields such as enterprise intelligent office, digital home entertainment, medical treatment, In-vehicle networking.
Although super-broadband tech is compared to traditional narrowband systems, there is a lot of advantage, compared to traditional narrow wireless communication technology, occurred in super-broadband tech from the past different from theory to the challenge designed.These technological challenges comprise: the radio-frequency front-end in broadband, baseband circuit design at a high speed, the design of ultra broadband MIMO technology, ultra-wideband antenna, disturb and the reduction of noise and removal etc.In addition, ultra broadband and coexisting of various narrowband systems need the receiving system of ever-increasing dynamic range, and this is also technological difficulties.In conjunction with the 6-9GHz frequency range that China plans ultrabroad-band spectrum, from the angle that system realizes, adopt 0.18 μm of CMOS technology of current main-stream, the radio-frequency front-end design in broadband is especially rich in challenge.
Programmable gain amplifier is as the very important module of in radio-frequency front-end, and its performance of performance on whole radio-frequency front-end has vital impact.Especially, for the receiving terminal of ultra-wideband communication system, by utilizing the broadband programmable gain amplifier of high linearity to carry out adjustment gain, the distortion of signal can be effectively reduced.Therefore, the linearity how improving broadband programmable gain amplifier is a study hotspot.
Summary of the invention
Embodiments provide a kind of broadband programmable gain amplifier, it has the higher linearity, and can effectively reduce the distortion of signal, technical scheme is as follows:
A kind of broadband programmable gain amplifier, comprising:
Adopt the input buffer stage of fully differential source follower structure, adopt the 1dB resistance attenuator of the R-2R ladder shaped resistance structure of symmetrical configuration fully differential form and adopt the variable gain amplifier of source degeneracy and current-mode combined technology;
The input of described input buffer stage is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator is connected with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs.
In the technical scheme that the embodiment of the present invention provides, broadband programmable gain amplifier is made up of the input buffer stage of the employing fully differential source follower structure be connected successively, the 1dB resistance attenuator of R-2R ladder shaped resistance structure of employing symmetrical configuration fully differential form and the variable gain amplifier of employing source degeneracy and current-mode combined technology.Wherein, variable gain amplifier is on the basis of common source degeneracy structure, have employed the technology that linearity enhancement mode source degeneracy structure combines with current amplifier, make the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure be similar to linear term, effectively can improve the linearity of whole programmable gain amplifier; Simultaneously cascade resistance decrement network before variable gain amplifier, makes the linearity after cascade obtain further raising.Therefore, the broadband programmable gain amplifier that this programme provides has the higher linearity, can effectively reduce the distortion of signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The electrical block diagram of a kind of broadband programmable gain amplifier that Fig. 1 provides for the embodiment of the present invention;
The electrical block diagram of the input buffer stage in a kind of broadband programmable gain amplifier that Fig. 2 provides for the embodiment of the present invention;
The electrical block diagram of the 1dB resistance attenuator in a kind of broadband programmable gain amplifier that Fig. 3 provides for the embodiment of the present invention;
The electrical block diagram of the variable gain amplifier in a kind of broadband programmable gain amplifier that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Embodiments provide a kind of broadband programmable gain amplifier, it has the higher linearity, is arranged on the receiving terminal of ultra-wideband communication system, can effectively reduce the distortion of signal.This broadband programmable gain amplifier, comprising:
Adopt the input buffer stage of fully differential source follower structure, adopt the 1dB resistance attenuator of the R-2R ladder shaped resistance structure of symmetrical configuration fully differential form and adopt the variable gain amplifier of source degeneracy and current-mode combined technology;
The input of described input buffer stage is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator is connected with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs.
In the technical scheme that the embodiment of the present invention provides, broadband programmable gain amplifier is made up of the input buffer stage of the employing fully differential source follower structure be connected successively, the 1dB resistance attenuator of R-2R ladder shaped resistance structure of employing symmetrical configuration fully differential form and the variable gain amplifier of employing source degeneracy and current-mode combined technology.Wherein, variable gain amplifier is on the basis of common source degeneracy structure, have employed the technology that linearity enhancement mode source degeneracy structure combines with current amplifier, make the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure be similar to linear term, effectively can improve the linearity of whole programmable gain amplifier; Simultaneously cascade resistance decrement network before variable gain amplifier, makes the linearity after cascade obtain further raising.Therefore, the broadband programmable gain amplifier that this programme provides has the higher linearity, can effectively reduce the distortion of signal.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As described in Figure 1, a kind of broadband programmable gain amplifier that the embodiment of the present invention provides comprises:
Adopt the input buffer stage 101 of fully differential source follower structure, adopt the 1dB resistance attenuator 102 of the R-2R ladder shaped resistance structure of symmetrical configuration fully differential form and adopt the variable gain amplifier 103 of source degeneracy and current-mode combined technology;
The input of input buffer stage 101 and the first differential input signal V
inp, the second differential input signal V
innbe connected, output is connected with the input of 1dB resistance attenuator 102;
The output of 1dB resistance attenuator 102 is connected with variable gain amplifier 103 input;
The output of variable gain amplifier 103 is the output of differential signal, and described differential signal outputs comprises: the first differential signal outputs V
outpwith the second differential signal outputs V
outn.
Fig. 2 is the electrical block diagram of input buffer stage.As shown in Figure 2, input buffer stage 101 to comprise: by the first nmos pass transistor M
n1with the second nmos pass transistor M
n2the first differential input stage 201 formed, by the 3rd nmos pass transistor M
n3, the 4th nmos pass transistor M
n4, the 5th nmos pass transistor M
n5with the 6th nmos pass transistor M
n6the cascade active load 202 formed.
Wherein, the first nmos pass transistor M
n1with the second nmos pass transistor M
n2, its grid respectively with the first differential input signal V
inp, the second differential input signal V
innbe connected; Its source electrode respectively with the 3rd nmos pass transistor M
n3drain electrode, the 4th nmos pass transistor M
n4drain electrode be connected, namely its source electrode respectively with input buffer stage the second differential signal outputs V
outn, the first differential signal outputs V
outpbe connected; Its drain electrode connects with supply voltage;
3rd nmos pass transistor M
n3with the 4th nmos pass transistor M
n4, its grid be connected, and with the first bias voltage V
bn1be connected;
5th nmos pass transistor M
n5with the 6th nmos pass transistor M
n6, its grid be connected, and with the second bias voltage V
bn2be connected, its drain electrode respectively with the 3rd nmos pass transistor M
n3source electrode, the 4th nmos pass transistor M
n4source electrode be connected, its source grounding.
Fig. 3 is the electrical block diagram of 1dB resistance attenuator 102.As shown in Figure 3,1dB resistance attenuator 102 comprises: the first switch closes to twelvemo: S
01~ S
51and S
02~ S
52, identical the first resistance of resistance is to the tenth resistance: R
11~ R
51and R
12~ R
52, different the 11 resistance of resistance is to the 15 resistance: R
1~ R
5;
Wherein, the first resistance is to the 5th resistance: R
11~ R
51be connected in series successively, and the first differential input signal V
inpwith the first resistance R
11one end be connected; First switch S
01one end and the first resistance R
11connect the first differential input signal V
inpone end be connected, the other end and the first differential signal outputs V
outpbe connected; Second switch S
11one end and the second resistance R
21connect the first resistance R
11one end be connected, the other end and the first differential signal outputs V
outpbe connected; 3rd switch S
21one end and the 3rd resistance R
31connect the second resistance R
21one end be connected, the other end and the first differential signal outputs V
outpbe connected; 4th switch S
31one end and the 4th resistance R
41connect the 3rd resistance R
31one end be connected, the other end and the first differential signal outputs V
outpbe connected; 5th switch S
41one end and the 5th resistance R
51connect the 4th resistance R
41one end be connected, the other end and the first differential signal outputs V
outpbe connected; 6th switch S
51one end and the 5th resistance R
51the other end be connected, the other end and the first differential signal outputs V
outpbe connected;
Same, the 6th resistance is to the tenth resistance: R
12~ R
52be connected in series successively, and the second differential input signal V
innwith the 6th resistance R
12one end be connected; 7th switch S
02one end and the 6th resistance R
12connect the second differential input signal V
innone end be connected, the other end and the second differential signal outputs V
outnbe connected; 8th switch S
12one end and the 7th resistance R
22connect the 6th resistance R
12one end be connected, the other end and the second differential signal outputs V
outnbe connected; 9th switch S
22one end and the 8th resistance R
32connect the 7th resistance R
22one end be connected, the other end and the second differential signal outputs V
outnbe connected; Tenth switch S
32one end and the 9th resistance R
42connect the 8th resistance R
32one end be connected, the other end and the second differential signal outputs V
outnbe connected; 11 switch S
42one end and the tenth resistance R
52connect the 9th resistance R
42one end be connected, the other end and the second differential signal outputs V
outnbe connected; Twelvemo closes S
52one end and the tenth resistance R
52the other end be connected, the other end and the second differential signal outputs V
outnbe connected;
11 resistance R
1one end and the second resistance R
21connect the first resistance R
11one end be connected, the other end and the 7th resistance R
22connect the 6th resistance R
12one end be connected; 12 resistance R
2one end and the 3rd resistance R
31connect the second resistance R
21one end be connected, the other end and the 8th resistance R
32connect the 7th resistance R
22one end be connected; 13 resistance R
3one end and the 4th resistance R
41connect the 3rd resistance R
31one end be connected, the other end and the 9th resistance R
42connect the 8th resistance R
32one end be connected; 14 resistance R
4one end and the 5th resistance R
51connect the 4th resistance R
41one end be connected, the other end and the tenth resistance R
52connect the 9th resistance R
42one end be connected; 15 resistance R
5one end and the 5th resistance R
51connect the 6th switch S
51one end be connected, the other end and the tenth resistance R
52connect twelvemo and close S
52one end be connected.
Fig. 4 is the electrical block diagram of variable gain amplifier 103.As shown in Figure 4, variable gain amplifier 103 comprises: the second differential input stage 401, source degeneracy switched resistor network 402, two buffered feedback levels: first current amplifier stage 405 and second current amplifier stage 406 with resistance feedback of the first buffered feedback level 403 and the second buffered feedback level 404, symmetrical configuration.
Wherein, the second differential input stage 401 comprises: the 7th nmos pass transistor M
11with the 8th nmos pass transistor M
12, by the 9th nmos pass transistor M
31a, the tenth nmos pass transistor M
32a, the 11 nmos pass transistor M
31b, the tenth bi-NMOS transistor M
32bthe NMOS cascade current source current source formed, by the first PMOS transistor M
21a, the second PMOS transistor M
22a, the 3rd PMOS transistor M
21b, the 4th PMOS transistor M
22bthe PMOS cascade active load formed;
7th nmos pass transistor M
11with the 8th nmos pass transistor M
12, its grid meets the first differential input signal V respectively
inp, the second differential input signal V
inn, its source electrode meets the 11 nmos pass transistor M respectively
31bdrain electrode, the tenth bi-NMOS transistor M
32bdrain electrode, its drain electrode meets the 3rd PMOS transistor M respectively
21bdrain electrode, the 4th PMOS transistor M
22bdrain electrode;
9th nmos pass transistor M
31awith the tenth nmos pass transistor M
32a, its grid connects the first nmos source in the first buffered feedback level 403 respectively and follows pipe M
41pipe M is followed with the first nmos source in the second buffered feedback level 404
41, its drain electrode meets the 11 nmos pass transistor M respectively
31bwith the 12 NMOS crystal M
32bsource electrode, its source ground;
11 nmos pass transistor M
31bwith the 12 NMOS crystal M
32b, its grid connects, and with the first bias voltage V
bn1connect;
First PMOS transistor M
21awith the second PMOS transistor M
22a, its grid be connected, and with the 4th bias voltage V
bp2be connected, its drain electrode respectively with the 3rd PMOS transistor M
21bsource electrode, the 4th PMOS transistor source electrode M
22bbe connected, its source electrode connects supply voltage;
3rd PMOS transistor M
21bwith the 4th PMOS transistor M
22b, its grid be connected, and with the 3rd bias voltage V
bp1be connected.
Wherein, source degeneracy switched resistor network 402 comprises: the connection in series-parallel of many group resistance switchs is formed, and this resistance switch string comprises: the 16 resistance R
sn1, the 13 switch S
n, the 17 resistance R
sn2, wherein n=1,2,3,4.......
Wherein, the first buffered feedback level 403 comprises: the first nmos source follows pipe M
41, the second nmos source follows pipe M
51, by the 13 nmos pass transistor M
41awith the 14 nmos pass transistor M
51a, the 15 nmos pass transistor M
41bwith the 16 nmos pass transistor M
51bthe NMOS cascade active load formed;
First nmos source follows pipe M
41pipe M is followed with the second nmos source
51, its grid is connected, and is connected to the 7th nmos pass transistor M in the second differential input stage 401
11drain electrode, its source electrode respectively with the 15 nmos pass transistor M
41bdrain electrode and the 16 nmos pass transistor M
51bdrain electrode be connected, its drain electrode connect supply voltage;
13 nmos pass transistor M
41awith the 14 nmos pass transistor M
51a, its grid be connected, and with the second bias voltage V
bn2be connected, its drain electrode respectively with the 15 nmos pass transistor M
41bsource electrode, the 16 nmos pass transistor M
51bsource electrode be connected, its source ground;
15 nmos pass transistor M
41bwith the 16 nmos pass transistor M
51b, its grid be connected, and with the first bias voltage V
bn1be connected, and the 15 nmos pass transistor M
41bdrain electrode and the second differential input stage in the 9th nmos pass transistor M
31agrid be connected.
Wherein, as shown in Figure 4, the second buffered feedback level 404 forms identical with connected mode with the first buffered feedback level 403 circuit, does not repeat them here.
Wherein, the first current amplifier stage 405 comprises: by the 17 nmos pass transistor M
71awith the 18 nmos pass transistor M
71bthe NMOS cascade mirror current source formed, by the 5th PMOS transistor M
61awith the 6th PMOS transistor M
61bthe PMOS cascade active load formed and feedback resistance R
f1;
17 nmos pass transistor M
71a, the second nmos source in its grid and buffered feedback level follows pipe M
51source electrode be connected, its drain electrode with the 18 nmos pass transistor M
71bsource electrode be connected, its source ground;
18 nmos pass transistor M
71b, its grid meets the first bias voltage V
bn1, drain electrode meets the first differential signal outputs V
outp;
5th PMOS transistor M
61a, its grid meets the 4th bias voltage V
bP2, drain electrode meets the 6th PMOS transistor M
61bsource electrode, source electrode connects supply voltage;
6th PMOS transistor M
61b, its grid meets the 3rd bias voltage V
bP1, drain electrode meets the first differential signal outputs V
outp;
Feedback resistance R
f1be connected on the 17 nmos pass transistor M
71agrid and the first differential signal outputs V
outpbetween.
Wherein, as shown in Figure 4, the second current amplifier stage 406 forms identical with the first current amplifier stage 405 circuit, but connected mode difference is: the feedback resistance R in the second current amplifier stage 406
f1be connected on the 17 nmos pass transistor M
71agrid and the second differential signal outputs V
outnbetween.Therefore, for the second current amplifier stage 406 circuit composition and connected mode do not repeat them here.
The operation principle of the broadband programmable gain amplifier that the embodiment of the present invention provides is: in order to improve the linearity and bandwidth, variable gain amplifier improves on the basis of conventional source degeneracy structure, have employed the technology that linearity enhancement mode source degeneracy structure combines with current amplifier.As shown in Figure 4, the buffered feedback level of the second differential input stage, source degeneracy switched resistor network, two symmetrical configuration constitutes linearity enhancement mode source degeneracy structure.Differential input voltage signal is by linearity enhancement mode source degeneracy circuit structure, and be approximately linearly converted to current signal, be namely equivalent to the trsanscondutance amplifier of an approximately linear, equivalent transconductance can approximate representation be:
Wherein R
sfor source degeneracy resistance.Current signal again through current amplifier stage amplify after, by feedback resistance R
f1constitute a closed loop trans-impedance amplifier, the equivalent resistance of this amplifier can approximate representation be:
R
m≈-R
F1
Couple together by the buffered feedback level of a source follower structure between second differential input stage and current amplifier stage, an effect of buffered feedback level makes the equivalent transconductance of the second differential input stage closer to linear term 1/R
s, namely obtain the better linearity, another effect carries out frequency compensation between two-stage, makes overall amplifier more stable.Therefore, the gain A of overall variable gain amplifier
vcan be expressed as:
Visible, the amplifier gain of this structure is only relevant with resistance ratio, and does not depend on the absolute value with resistance, therefore can obtain more accurate yield value, change any one resistance value, can reach the object changing gain.
In addition, owing to have employed current-mode, and introduce buffered feedback level, the dominant pole of overall variable gain amplifier is only determined by the electric capacity of feedback resistance and output node, suitable choose feedback resistance value amplifier and can realize wider bandwidth.In order to ensure to remain unchanged at adjustment gain Time Bandwidth, R should be made
f1remain unchanged, therefore, by resistance R
sbe designed to switch resistance array, by control switch, can control R
sresistance, thus the gain of control amplifier.
Because variable gain amplifier of the present invention have employed linearity enhancement mode source degeneracy structure, and before variable gain amplifier, add resistance attenuator, make the linearity of overall programmable gain amplifier obtain effective raising, the simulation result of its OIP3 reaches as high as 24dBm.In addition, the output stage of variable gain amplifier have employed current-mode form, makes bandwidth can be much more wide than traditional voltage-mode amplifier band, can reach hundreds of MHz.Therefore, this structure programmable gain amplifier can be used as high linearity, broadband programmable gain amplifier.
While guarantee high linearity index, in order to meet the demand of more accurate gain adjuster step in practical application, the mode of 1dB resistance decrement network and the cascade of variable gain amplifier phase is have employed in the present invention, as shown in Figure 1, accurate 1dB gain-adjusted is realized with 1dB resistance decrement network, and realize with variable gain amplifier the coarse tuning that 6dB regulates step-length, so both meet degree of regulation requirement, also ensure that high linearity simultaneously.
The circuit theory of 1dB resistance decrement network is the attenuator realizing any step-length derived by R-2R trapezoid resistance network, as shown in Figure 3, works as R
11~ R
51and R
12~ R
52all get identical resistance R
0time, R
5for 18R
0, R
1~ R
4be the resistance of 4 similar resistance, resistance is 180R
0, the R-2R trapezoid resistance network revised like this can realize the decay of 1dB step-length.
Finally, the gain-adjusted of overall programmable gain amplifier is by digital switch control realization, and attainable gain-adjusted scope is-4dB ~ 28dB, and gain adjuster step is 1dB, and it is 24dBm that-three dB bandwidth is greater than 300MHz, OIP3.
Therefore, the broadband programmable gain amplifier that the embodiment of the present invention provides meets specific bandwidth demand and has the higher linearity, is used in super broad band radio communication system application, can effectively reduces the distortion of signal.
The above is only the specific embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (1)
1. a broadband programmable gain amplifier, is characterized in that, comprising:
Adopt the input buffer stage of fully differential source follower structure, adopt the 1dB resistance attenuator of the R-2R ladder shaped resistance structure of symmetrical configuration fully differential form and adopt the variable gain amplifier of source degeneracy and current-mode combined technology;
The input of described input buffer stage is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator is connected with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs;
Wherein, described input buffer stage comprises: the first differential input stage be made up of the first nmos pass transistor and the second nmos pass transistor, the cascade active load be made up of the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor;
Described first nmos pass transistor and the second nmos pass transistor, its grid is connected with the first differential input signal, the second differential input signal respectively, its source electrode is connected with the drain electrode of the 3rd nmos pass transistor, the drain electrode of the 4th nmos pass transistor respectively, and its drain electrode connects with supply voltage;
Described 3rd nmos pass transistor and the 4th nmos pass transistor, its grid is connected, and is connected with the first bias voltage;
Described 5th nmos pass transistor and the 6th nmos pass transistor, its grid is connected, and is connected with the second bias voltage, and its drain electrode is connected with the source electrode of the 3rd nmos pass transistor, the source electrode of the 4th nmos pass transistor respectively, its source ground;
Wherein, described 1dB resistance attenuator comprises: 12 switches: the first switch is to ten resistance that twelvemo is closed, resistance is identical: the first resistance is to the tenth resistance, different five resistance of resistance: the 11 resistance is to the 15 resistance;
Described first resistance is connected in series successively to the 5th resistance, and the first differential input signal is connected with one end of the first resistance; First switch one end is connected the first differential input signal one end with the first resistance is connected, and the other end is connected with the first differential signal outputs; Second switch one end is connected the first resistance one end with the second resistance is connected, and the other end is connected with the first differential signal outputs; 3rd switch one end is connected the second resistance one end with the 3rd resistance is connected, and the other end is connected with the first differential signal outputs; 4th switch one end is connected the 3rd resistance one end with the 4th resistance is connected, and the other end is connected with the first differential signal outputs; 5th switch one end is connected the 4th resistance one end with the 5th resistance is connected, and the other end is connected with the first differential signal outputs; 6th switch one end is connected with the other end of the 5th resistance, and the other end is connected with the first differential signal outputs;
Described 6th resistance is connected in series successively to the tenth resistance, and the second differential input signal is connected with one end of the 6th resistance; 7th switch one end is connected the second differential input signal one end with the 6th resistance is connected, and the other end is connected with the second differential signal outputs; 8th switch one end is connected the 6th resistance one end with the 7th resistance is connected, and the other end is connected with the second differential signal outputs; 9th switch one end is connected the 7th resistance one end with the 8th resistance is connected, and the other end is connected with the second differential signal outputs; Tenth switch one end is connected the 8th resistance one end with the 9th resistance is connected, and the other end is connected with the second differential signal outputs; 11 switch one end is connected the 9th resistance one end with the tenth resistance is connected, and the other end is connected with the second differential signal outputs; Twelvemo is closed one end and is connected with the other end of the tenth resistance, and the other end is connected with the second differential signal outputs;
Described 11 resistance one end is connected with one end that the second resistance is connected the first resistance, and the other end is connected the 6th resistance one end with the 7th resistance is connected; One end that 12 resistance one end is connected the second resistance with the 3rd resistance is connected, and the other end is connected the 7th resistance one end with the 8th resistance is connected; One end that 13 resistance one end is connected the 3rd resistance with the 4th resistance is connected, and the other end is connected the 8th resistance one end with the 9th resistance is connected; One end that 14 resistance one end is connected the 4th resistance with the 5th resistance is connected, and the other end is connected the 9th resistance one end with the tenth resistance is connected; One end that 15 resistance one end is connected the 6th switch with the 5th resistance is connected, and the other end is connected one end that twelvemo closes and is connected with the tenth resistance;
Wherein, described variable gain amplifier comprises: the second differential input stage, source degeneracy switched resistor network, two buffered feedback levels: the first buffered feedback level and the second buffered feedback level, two current amplifier stage with resistance feedback: the first current amplifier stage and the second current amplifier stage;
Wherein, described second differential input stage comprises: the 7th nmos pass transistor and the 8th nmos pass transistor, the NMOS cascade current source current source be made up of the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the PMOS cascade active load be made up of the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor;
Described 7th nmos pass transistor and the 8th nmos pass transistor, its grid connects the first differential input signal, the second differential input signal respectively, its source electrode connects the drain electrode of the 11 nmos pass transistor, the drain electrode of the tenth bi-NMOS transistor respectively, and its drain electrode connects the drain electrode of the 3rd PMOS transistor, the drain electrode of the 4th PMOS transistor respectively;
Described 9th nmos pass transistor and the tenth nmos pass transistor, its grid connects the source electrode of source follower in buffered feedback level respectively, and its drain electrode connects the source electrode of the 11 nmos pass transistor, the source electrode of the 12 NMOS crystal, its source ground respectively;
Described 11 nmos pass transistor and the 12 NMOS crystal, its grid connects, and connects with the first bias voltage;
Described first PMOS transistor and the second PMOS transistor, its grid is connected, and is connected with the 4th bias voltage, and its drain electrode is connected with the source electrode of the 3rd PMOS transistor, the source electrode of the 4th PMOS transistor respectively, and its source electrode connects supply voltage;
Described 3rd PMOS transistor and the 4th PMOS transistor, its grid is connected, and is connected with the 3rd bias voltage;
Wherein, described source degeneracy switched resistor network forms by organizing resistance switch connection in series-parallel more, and described resistance switch string comprises: the 16 resistance, the 13 switch, the 17 resistance;
Wherein, described first buffered feedback level comprises: the first nmos source follows pipe, second nmos source follows pipe, the NMOS cascade active load be made up of the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Described first nmos source follows pipe and the second nmos source follows pipe, its grid is connected, and be connected to the drain electrode of the 7th nmos pass transistor in the second differential input stage, its source electrode is connected with the drain electrode of the 15 nmos pass transistor, the drain electrode of the 16 nmos pass transistor respectively, and its drain electrode connects supply voltage;
Described 13 nmos pass transistor and the 14 nmos pass transistor, its grid is connected, and is connected with the second bias voltage, and its drain electrode is connected with the source electrode of the 15 nmos pass transistor, the source electrode of the 16 nmos pass transistor respectively, its source ground;
Described 15 nmos pass transistor and the 16 nmos pass transistor, its grid is connected, and is connected with the first bias voltage, and the drain electrode of the 15 nmos pass transistor is connected with the grid of the 9th nmos pass transistor in the second differential input stage;
Wherein, described second buffered feedback level forms identical with described first buffered feedback level circuit, the second nmos source that the first nmos source in described second buffered feedback level is followed in pipe and described second buffered feedback level follows pipe, its grid is connected, and is connected to the drain electrode of the 8th nmos pass transistor in described second differential input stage; The drain electrode of the 15 nmos pass transistor in described second buffered feedback level is connected with the grid of the tenth nmos pass transistor in described second differential input stage;
Wherein, described first current amplifier stage comprises: the NMOS cascade mirror current source be made up of the 17 nmos pass transistor and the 18 nmos pass transistor, the PMOS cascade active load be made up of the 5th PMOS transistor and the 6th PMOS transistor and feedback resistance;
Described 17 nmos pass transistor, the source electrode that its grid follows pipe with the second nmos source in buffered feedback level is connected, and its drain electrode is connected with the source electrode of the 18 nmos pass transistor, its source ground;
Described 18 nmos pass transistor, its grid connects the first bias voltage, and drain electrode connects the first differential signal outputs;
Described 5th PMOS transistor, its grid connects the 4th bias voltage, and drain electrode connects the source electrode of the 6th PMOS transistor, and source electrode connects supply voltage;
Described 6th PMOS transistor, its grid connects the 3rd bias voltage, and drain electrode connects the first differential signal outputs;
Between the grid that described feedback resistance is connected on the 17 nmos pass transistor and the first differential signal outputs;
Wherein, described second current amplifier stage forms identical with the first current amplifier stage circuit, between the grid that its feedback resistance is connected on the 17 nmos pass transistor in described second current amplifier stage and the second differential signal outputs.
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| CN201110219918.1A CN102916666B (en) | 2011-08-02 | 2011-08-02 | A kind of broadband programmable gain amplifier |
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| CN107749746A (en) * | 2017-11-10 | 2018-03-02 | 北京无线电测量研究所 | A kind of Data control gain amplifier |
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| US10211865B1 (en) * | 2018-06-22 | 2019-02-19 | Futurewei Technologies, Inc. | Fully differential adjustable gain devices and methods for use therewith |
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| CN111865244B (en) * | 2020-09-18 | 2020-12-18 | 成都嘉纳海威科技有限责任公司 | Digital control variable gain amplifier |
| CN112506259B (en) * | 2020-11-12 | 2022-07-01 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
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| CN113746472A (en) * | 2021-08-19 | 2021-12-03 | 上海卫星工程研究所 | Matrix type initiating explosive device driving circuit for deep space probe and control method thereof |
| CN114337710B (en) * | 2022-03-08 | 2022-06-03 | 深圳市鼎阳科技股份有限公司 | Gain switching circuit for receiving radio frequency signal and radio frequency receiver |
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