CN102916666A - Broadband programmable gain amplifier - Google Patents
Broadband programmable gain amplifier Download PDFInfo
- Publication number
- CN102916666A CN102916666A CN2011102199181A CN201110219918A CN102916666A CN 102916666 A CN102916666 A CN 102916666A CN 2011102199181 A CN2011102199181 A CN 2011102199181A CN 201110219918 A CN201110219918 A CN 201110219918A CN 102916666 A CN102916666 A CN 102916666A
- Authority
- CN
- China
- Prior art keywords
- resistance
- pass transistor
- nmos pass
- links
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a broadband programmable gain amplifier which comprises an input buffer, a 1dB resistance attenuator and a variable gain amplifier. The input buffer is of a fully differential source follower structure, the 1dB resistance attenuator is of a R-2R ladder resistance structure in a structurally symmetric fully differential form, and a source degeneration and current mold combination technology is adopted for the variable gain amplifier; an input end of the input buffer is connected with first differential input signals and second differential input signals, and an output end of the input buffer is connected with an input end of the 1dB resistance attenuator; an output end of the 1dB resistance attenuator is connected with an input end of the variable gain amplifier; and an output end of the variable gain amplifier is a differential signal output end, and the differential signal output end comprises a first differential signal output end and a second differential signal output end. According to the scheme, the broadband programmable gain amplifier is high in linearity, and signal distortion can be effectively reduced.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly relate to a kind of broadband programmable gain amplifier.
Background technology
Along with developing rapidly of Communications Market, radio communication has entered the epoch of high speed data transfer, and wider frequency band is with the Effective Raise message transmission rate, and especially short-range wireless high-speed transmits.The Ultra-wideband Communication Technology that is operated in the 3.1-10.6GHz frequency range that FCC announced in 2002 is as a kind of unconventional, novel Radio Transmission Technology, adopt extremely wide bandwidth (greater than 500MHz) transmission information, have the characteristics such as transmission rate is high, spatial frequency spectrum efficient is high, system is simple and easy, low in energy consumption.At present, Ultra-wideband Communication Technology just is being widely used in the short-distance wireless high-speed transfer fields such as enterprise intelligent office, digital home entertainment, medical treatment, In-vehicle networking.
Although super-broadband tech than traditional narrowband systems, has a lot of advantages, than the traditional narrow wireless communication technology, occurred in the super-broadband tech and the in the past different challenges from theory to design.These technological challenges comprise: the reduction of the radio-frequency front-end in broadband, at a high speed baseband circuit design, ultra broadband MIMO technology, ultra-wideband antenna design, interference and noise and removal etc.In addition, the coexistence of ultra broadband and various narrowband systems needs the receiving system of ever-increasing dynamic range, and this also is technological difficulties.In conjunction with the 6-9GHz frequency range of China to the planning of ultra broadband frequency spectrum, from the angle that system realizes, adopt 0.18 μ m CMOS technique of current main-stream, the radio-frequency front-end design in broadband especially is rich in challenge.
Programmable gain amplifier is as a very important module in the radio-frequency front-end, and its performance has vital impact to the performance of whole radio-frequency front-end.Especially for the receiving terminal of ultra-wideband communication system, regulate gain by the broadband programmable gain amplifier that utilizes high linearity, can effectively reduce the distortion of signal.Therefore, the linearity that how to improve broadband programmable gain amplifier is a study hotspot.
Summary of the invention
The embodiment of the invention provides a kind of broadband programmable gain amplifier, and it has the higher linearity, can effectively reduce the distortion of signal, and technical scheme is as follows:
A kind of broadband programmable gain amplifier comprises:
The 1dB resistance attenuator of the R-2R ladder shaped resistance structure of the input buffer stage of employing fully differential source follower structure, employing symmetrical configuration fully differential form and the variable gain amplifier that adopts source degeneracy and current-mode combined technology;
The input of described input buffer stage links to each other with the first differential input signal, the second differential input signal, and output links to each other with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator links to each other with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal output comprises: the first differential signal output and the second differential signal output.
In the technical scheme that the embodiment of the invention provides, broadband programmable gain amplifier by the input buffer stage of the employing fully differential source follower structure that links to each other successively, adopt symmetrical configuration fully differential form R-2R ladder shaped resistance structure the 1dB resistance attenuator and adopt the variable gain amplifier of source degeneracy and current-mode combined technology to consist of.Wherein, variable gain amplifier is on the basis of common source degeneracy structure, the technology that has adopted linearity enhancement mode source degeneracy structure to combine with current amplifier, so that the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure is similar to linear term, but the linearity of the whole programmable gain amplifier of Effective Raise; Simultaneously before variable gain amplifier cascade the resistance decrement network so that the linearity after the cascade has obtained further raising.Therefore, the broadband programmable gain amplifier that this programme provides has the higher linearity, can effectively reduce the distortion of signal.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do simple the introduction to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The electrical block diagram of a kind of broadband programmable gain amplifier that Fig. 1 provides for the embodiment of the invention;
The electrical block diagram of the input buffer stage in a kind of broadband programmable gain amplifier that Fig. 2 provides for the embodiment of the invention;
The electrical block diagram of the 1dB resistance attenuator in a kind of broadband programmable gain amplifier that Fig. 3 provides for the embodiment of the invention;
The electrical block diagram of the variable gain amplifier in a kind of broadband programmable gain amplifier that Fig. 4 provides for the embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of broadband programmable gain amplifier, and it has the higher linearity, is arranged on the receiving terminal of ultra-wideband communication system, can effectively reduce the distortion of signal.This broadband programmable gain amplifier comprises:
The 1dB resistance attenuator of the R-2R ladder shaped resistance structure of the input buffer stage of employing fully differential source follower structure, employing symmetrical configuration fully differential form and the variable gain amplifier that adopts source degeneracy and current-mode combined technology;
The input of described input buffer stage links to each other with the first differential input signal, the second differential input signal, and output links to each other with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator links to each other with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal output comprises: the first differential signal output and the second differential signal output.
In the technical scheme that the embodiment of the invention provides, broadband programmable gain amplifier by the input buffer stage of the employing fully differential source follower structure that links to each other successively, adopt symmetrical configuration fully differential form R-2R ladder shaped resistance structure the 1dB resistance attenuator and adopt the variable gain amplifier of source degeneracy and current-mode combined technology to consist of.Wherein, variable gain amplifier is on the basis of common source degeneracy structure, the technology that has adopted linearity enhancement mode source degeneracy structure to combine with current amplifier, so that the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure is similar to linear term, but the linearity of the whole programmable gain amplifier of Effective Raise; Simultaneously before variable gain amplifier cascade the resistance decrement network so that the linearity after the cascade has obtained further raising.Therefore, the broadband programmable gain amplifier that this programme provides has the higher linearity, can effectively reduce the distortion of signal.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
As described in Figure 1, a kind of broadband programmable gain amplifier of providing of the embodiment of the invention comprises:
The 1dB resistance attenuator 102 of the R-2R ladder shaped resistance structure of the input buffer stage 101 of employing fully differential source follower structure, employing symmetrical configuration fully differential form and the variable gain amplifier 103 that adopts source degeneracy and current-mode combined technology;
Input and the first differential input signal V of input buffer stage 101
Inp, the second differential input signal V
InnLink to each other, output links to each other with the input of 1dB resistance attenuator 102;
The output of 1dB resistance attenuator 102 links to each other with variable gain amplifier 103 inputs;
The output of variable gain amplifier 103 is the output of differential signal, and described differential signal output comprises: the first differential signal output V
OutpWith the second differential signal output V
Outn
Fig. 2 is the electrical block diagram of input buffer stage.As shown in Figure 2, input buffer stage 101 comprises: by the first nmos pass transistor M
N1With the second nmos pass transistor M
N2The first differential input stage 201 that consists of is by the 3rd nmos pass transistor M
N3, the 4th nmos pass transistor M
N4, the 5th nmos pass transistor M
N5With the 6th nmos pass transistor M
N6The cascade active load 202 that consists of.
Wherein, the first nmos pass transistor M
N1With the second nmos pass transistor M
N2, its grid respectively with the first differential input signal V
Inp, the second differential input signal V
InnLink to each other; Its source electrode respectively with the 3rd nmos pass transistor M
N3Drain electrode, the 4th nmos pass transistor M
N4Drain electrode link to each other, namely its source electrode respectively with the second differential signal output V of input buffer stage
Outn, the first differential signal output V
OutpLink to each other; Its drain electrode is joined with supply voltage;
The 3rd nmos pass transistor M
N3With the 4th nmos pass transistor M
N4, its grid links to each other, and with the first bias voltage V
Bn1Link to each other;
The 5th nmos pass transistor M
N5With the 6th nmos pass transistor M
N6, its grid links to each other, and with the second bias voltage V
Bn2Link to each other, its drain electrode respectively with the 3rd nmos pass transistor M
N3Source electrode, the 4th nmos pass transistor M
N4Source electrode link to each other its source grounding.
Fig. 3 is the electrical block diagram of 1dB resistance attenuator 102.As shown in Figure 3,1dB resistance attenuator 102 comprises: the first switch to the twelvemo is closed: S
01～S
51And S
02～S
52, the first resistance to the ten resistance that resistance is identical: R
11～R
51And R
12～R
52, the 11 resistance to the 15 resistance that resistance is different: R
1～R
5
Wherein, the first resistance to the five resistance: R
11～R
51Be connected in series successively, and the first differential input signal V
InpWith the first resistance R
11An end link to each other; The first switch S
01One end and the first resistance R
11Connect the first differential input signal V
InpAn end link to each other the other end and the first differential signal output V
OutpLink to each other; Second switch S
11One end and the second resistance R
21Connect the first resistance R
11An end link to each other the other end and the first differential signal output V
OutpLink to each other; The 3rd switch S
21One end and the 3rd resistance R
31Connect the second resistance R
21An end link to each other the other end and the first differential signal output V
OutpLink to each other; The 4th switch S
31One end and the 4th resistance R
41Connect the 3rd resistance R
31An end link to each other the other end and the first differential signal output V
OutpLink to each other; The 5th switch S
41One end and the 5th resistance R
51Connect the 4th resistance R
41An end link to each other the other end and the first differential signal output V
OutpLink to each other; The 6th switch S
51One end and the 5th resistance R
51The other end link to each other the other end and the first differential signal output V
OutpLink to each other;
Same, the 6th resistance to the ten resistance: R
12～R
52Be connected in series successively, and the second differential input signal V
InnWith the 6th resistance R
12An end link to each other; Minion is closed S
02One end and the 6th resistance R
12Connect the second differential input signal V
InnAn end link to each other the other end and the second differential signal output V
OutnLink to each other; The 8th switch S
12One end and the 7th resistance R
22Connect the 6th resistance R
12An end link to each other the other end and the second differential signal output V
OutnLink to each other; The 9th switch S
22One end and the 8th resistance R
32Connect the 7th resistance R
22An end link to each other the other end and the second differential signal output V
OutnLink to each other; The tenth switch S
32One end and the 9th resistance R
42Connect the 8th resistance R
32An end link to each other the other end and the second differential signal output V
OutnLink to each other; The 11 switch S
42One end and the tenth resistance R
52Connect the 9th resistance R
42An end link to each other the other end and the second differential signal output V
OutnLink to each other; Twelvemo is closed S
52One end and the tenth resistance R
52The other end link to each other the other end and the second differential signal output V
OutnLink to each other;
The 11 resistance R
1One end and the second resistance R
21Connect the first resistance R
11An end link to each other the other end and the 7th resistance R
22Connect the 6th resistance R
12An end link to each other; The 12 resistance R
2One end and the 3rd resistance R
31Connect the second resistance R
21An end link to each other the other end and the 8th resistance R
32Connect the 7th resistance R
22An end link to each other; The 13 resistance R
3One end and the 4th resistance R
41Connect the 3rd resistance R
31An end link to each other the other end and the 9th resistance R
42Connect the 8th resistance R
32An end link to each other; The 14 resistance R
4One end and the 5th resistance R
51Connect the 4th resistance R
41An end link to each other the other end and the tenth resistance R
52Connect the 9th resistance R
42An end link to each other; The 15 resistance R
5One end and the 5th resistance R
51Connect the 6th switch S
51An end link to each other the other end and the tenth resistance R
52Connect twelvemo and close S
52An end link to each other.
Fig. 4 is the electrical block diagram of variable gain amplifier 103.As shown in Figure 4, variable gain amplifier 103 comprises: the second differential input stage 401, source degeneracy switched resistor network 402, two buffering feedback stages: the first electric current amplifying stage 405 with resistance feedback and the second electric current amplifying stage 406 of the first buffering feedback stage 403 and the second buffering feedback stage 404, symmetrical configuration.
Wherein, the second differential input stage 401 comprises: the 7th nmos pass transistor M
11With the 8th nmos pass transistor M
12, by the 9th nmos pass transistor M
31a, the tenth nmos pass transistor M
32a, the 11 nmos pass transistor M
31b, the tenth bi-NMOS transistor M
32bThe NMOS cascade current source current source that consists of is by a PMOS transistor M
21a, the 2nd PMOS transistor M
22a, the 3rd PMOS transistor M
21b, the 4th PMOS transistor M
22bThe PMOS cascade active load that consists of;
The 7th nmos pass transistor M
11With the 8th nmos pass transistor M
12, its grid meets respectively the first differential input signal V
Inp, the second differential input signal V
Inn, its source electrode meets respectively the 11 nmos pass transistor M
31bDrain electrode, the tenth bi-NMOS transistor M
32bDrain electrode, its drain electrode meets respectively the 3rd PMOS transistor M
21bDrain electrode, the 4th PMOS transistor M
22bDrain electrode;
The 9th nmos pass transistor M
31aWith the tenth nmos pass transistor M
32a, its grid connect respectively first the buffering feedback stage 403 in the first nmos source follow the pipe M
41Follow pipe M with the first nmos source in the second buffering feedback stage 404
41, its drain electrode meets respectively the 11 nmos pass transistor M
31bWith the 12 NMOS crystal M
32bSource electrode, its source ground;
The 11 nmos pass transistor M
31bWith the 12 NMOS crystal M
32b, its grid joins, and with the first bias voltage V
Bn1Join;
The one PMOS transistor M
21aWith the 2nd PMOS transistor M
22a, its grid links to each other, and with the 4th bias voltage V
Bp2Link to each other, its drain electrode respectively with the 3rd PMOS transistor M
21bSource electrode, the 4th PMOS transistor source M
22bLink to each other, its source electrode connects supply voltage;
The 3rd PMOS transistor M
21bWith the 4th PMOS transistor M
22b, its grid links to each other, and with the 3rd bias voltage V
Bp1Link to each other.
Wherein, source degeneracy switched resistor network 402 comprises: organize the resistance switch connection in series-parallel more and consist of, this resistance switch string comprises: the 16 resistance R
Sn1, the 13 switch S
n, the 17 resistance R
Sn2, wherein n=1,2,3,4.......
Wherein, the first buffering feedback stage 403 comprises: the first nmos source is followed pipe M
41, the second nmos source is followed pipe M
51, by the 13 nmos pass transistor M
41aWith the 14 nmos pass transistor M
51a, the 15 nmos pass transistor M
41bWith the 16 nmos pass transistor M
51bThe NMOS cascade active load that consists of;
The first nmos source is followed pipe M
41Follow pipe M with the second nmos source
51, its grid links to each other, and is connected to the 7th nmos pass transistor M in the second differential input stage 401
11Drain electrode, its source electrode respectively with the 15 nmos pass transistor M
41bDrain electrode and the 16 nmos pass transistor M
51bDrain electrode link to each other, its drain electrode connects supply voltage;
The 13 nmos pass transistor M
41aWith the 14 nmos pass transistor M
51a, its grid links to each other, and with the second bias voltage V
Bn2Link to each other, its drain electrode respectively with the 15 nmos pass transistor M
41bSource electrode, the 16 nmos pass transistor M
51bSource electrode link to each other its source ground;
The 15 nmos pass transistor M
41bWith the 16 nmos pass transistor M
51b, its grid links to each other, and with the first bias voltage V
Bn1Link to each other, and the 15 nmos pass transistor M
41bDrain electrode and the 9th nmos pass transistor M in the second differential input stage
31aGrid link to each other.
Wherein, as shown in Figure 4, the second buffering feedback stage 404 is identical with connected mode with the first buffering feedback stage 403 the electric circuit constitutes, does not repeat them here.
Wherein, the first electric current amplifying stage 405 comprises: by the 17 nmos pass transistor M
71aWith the 18 nmos pass transistor M
71bThe NMOS cascade mirror current source that consists of is by the 5th PMOS transistor M
61aWith the 6th PMOS transistor M
61bThe PMOS cascade active load and the feedback resistance R that consist of
F1
The 17 nmos pass transistor M
71a, its grid is followed pipe M with the second nmos source in the buffering feedback stage
51Source electrode link to each other its drain electrode and the 18 nmos pass transistor M
71bSource electrode link to each other its source ground;
The 18 nmos pass transistor M
71b, its grid meets the first bias voltage V
Bn1, drain electrode meets the first differential signal output V
Outp
The 5th PMOS transistor M
61a, its grid meets the 4th bias voltage V
BP2, drain electrode meets the 6th PMOS transistor M
61bSource electrode, source electrode connects supply voltage;
The 6th PMOS transistor M
61b, its grid meets the 3rd bias voltage V
BP1, drain electrode meets the first differential signal output V
Outp
Feedback resistance R
F1Be connected on the 17 nmos pass transistor M
71aGrid and the first differential signal output V
OutpBetween.
Wherein, as shown in Figure 4, the second electric current amplifying stage 406 is identical with the first electric current amplifying stage 405 the electric circuit constitutes, but the connected mode difference is: the feedback resistance R in the second electric current amplifying stage 406
F1Be connected on the 17 nmos pass transistor M
71aGrid and the second differential signal output V
OutnBetween.Therefore, the electric circuit constitute and the connected mode for the second electric current amplifying stage 406 do not repeat them here.
The operation principle of the broadband programmable gain amplifier that the embodiment of the invention provides is: in order to improve the linearity and bandwidth, variable gain amplifier improves on the basis of conventional source degeneracy structure, the technology that has adopted linearity enhancement mode source degeneracy structure to combine with current amplifier.As shown in Figure 4, the buffering feedback stage of the second differential input stage, source degeneracy switched resistor network, two symmetrical configuration has formed linearity enhancement mode source degeneracy structure.The difference input voltage signal is converted to current signal by the linearity enhancement mode source degeneracy circuit structure approximately linear, namely is equivalent to the trsanscondutance amplifier of an approximately linear, and equivalent transconductance can approximate representation be:
R wherein
SBe source degeneracy resistance.Current signal is again after the overcurrent amplifying stage amplifies, by feedback resistance R
F1Consisted of a closed loop trans-impedance amplifier, but the equivalent resistance approximate representation of this amplifier is:
R
m≈-R
F1
Buffering feedback stage with a source follower structure between the second differential input stage and the electric current amplifying stage couples together, and an effect of buffering feedback stage is to make the equivalent transconductance of the second differential input stage closer to linear term 1/R
S, namely obtaining the better linearity, another effect is to carry out frequency compensation between two-stage, makes overall amplifier more stable.Therefore, the gain A of whole variable gain amplifier
vCan be expressed as:
As seen, the amplifier gain of this structure is only relevant with resistance ratio, and does not depend on and the absolute value of resistance, therefore can obtain more accurate yield value, changes any resistance value, can reach the purpose that changes gain.
In addition, owing to having adopted current-mode, and introduced the buffering feedback stage, so that the dominant pole of whole variable gain amplifier only determines by the electric capacity at feedback resistance and output node place, suitable chosen the feedback resistance value amplifier and can realize wider bandwidth.In order to guarantee to remain unchanged at adjusting gain Time Bandwidth, should make R
F1Remain unchanged, therefore, with resistance R
SBe designed to the switch resistance array, by control switch, can control R
SResistance, thereby the gain of control amplifier.
Because variable gain amplifier of the present invention has adopted linearity enhancement mode source degeneracy structure, and before variable gain amplifier, added resistance attenuator, so that the linearity of whole programmable gain amplifier has obtained effective raising, the simulation result of its OIP3 reaches as high as 24dBm.In addition, the output stage of variable gain amplifier has adopted the current-mode form, so that bandwidth can be wide more a lot of than traditional voltage-mode amplifier band, can reach hundreds of MHz.Therefore, this structure programmable gain amplifier can be used as high linearity, broadband programmable gain amplifier.
When guaranteeing the high linearity index, in order to satisfy the demand of more accurate gain-adjusted step-length in the practical application, adopted the mutually mode of cascade of 1dB resistance decrement network and variable gain amplifier among the present invention, as shown in Figure 1, realize accurate 1dB gain-adjusted with 1dB resistance decrement network, and realize that with variable gain amplifier 6dB regulates the coarse tuning of step-length, and so both satisfied the degree of regulation requirement, also guaranteed high linearity simultaneously.
The circuit theory of 1dB resistance decrement network is the attenuator of realizing any step-length that is derived by the R-2R trapezoid resistance network, as shown in Figure 3, works as R
11～R
51And R
12～R
52All get identical resistance R
0The time, R
5Be 18R
0, R
1～R
4Be the resistance of 4 similar resistance, resistance is 180R
0, the R-2R trapezoid resistance network of revising like this can be realized the decay of 1dB step-length.
Finally, the gain-adjusted of whole programmable gain amplifier realizes by digital switch control, and attainable gain-adjusted scope is-4dB～28dB, and the gain-adjusted step-length is 1dB, and-three dB bandwidth is 24dBm greater than 300MHz, OIP3.
Therefore, the broadband programmable gain amplifier that the embodiment of the invention provides satisfies specific bandwidth demand and has the higher linearity, is used in the super broad band radio communication system application, can effectively reduce the distortion of signal.
The above only is the specific embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. a broadband programmable gain amplifier is characterized in that, comprising:
The 1dB resistance attenuator of the R-2R ladder shaped resistance structure of the input buffer stage of employing fully differential source follower structure, employing symmetrical configuration fully differential form and the variable gain amplifier that adopts source degeneracy and current-mode combined technology;
The input of described input buffer stage links to each other with the first differential input signal, the second differential input signal, and output links to each other with the input of described 1dB resistance attenuator;
The output of described 1dB resistance attenuator links to each other with the input of described variable gain amplifier;
The output of described variable gain amplifier is the output of differential signal, and described differential signal output comprises: the first differential signal output and the second differential signal output.
2. amplifier according to claim 1, it is characterized in that, described input buffer stage comprises: the first differential input stage that is made of the first nmos pass transistor and the second nmos pass transistor, the cascade active load that is made of the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor;
Described the first nmos pass transistor and the second nmos pass transistor, its grid links to each other with the first differential input signal, the second differential input signal respectively, its source electrode links to each other with the drain electrode of the 3rd nmos pass transistor, the drain electrode of the 4th nmos pass transistor respectively, and its drain electrode is joined with supply voltage;
Described the 3rd nmos pass transistor and the 4th nmos pass transistor, its grid links to each other, and links to each other with the first bias voltage;
Described the 5th nmos pass transistor and the 6th nmos pass transistor, its grid links to each other, and links to each other with the second bias voltage, and its drain electrode links to each other its source ground with the source electrode of the 3rd nmos pass transistor, the source electrode of the 4th nmos pass transistor respectively.
3. amplifier according to claim 2, it is characterized in that, described 1dB resistance attenuator comprises: 12 switches: ten resistance that the first switch to the twelvemo is closed, resistance is identical: the first resistance to the ten resistance, different five resistance of resistance: the 11 resistance to the 15 resistance;
Described the first resistance to the five resistance are connected in series successively, and the first differential input signal links to each other with an end of the first resistance; The first switch one end is connected the first differential input signal with the first resistance a end links to each other, and the other end links to each other with the first differential signal output; Second switch one end is connected the first resistance with the second resistance a end links to each other, and the other end links to each other with the first differential signal output; The 3rd switch one end is connected the second resistance with the 3rd resistance a end links to each other, and the other end links to each other with the first differential signal output; The 4th switch one end is connected the 3rd resistance with the 4th resistance a end links to each other, and the other end links to each other with the first differential signal output; The 5th switch one end is connected the 4th resistance with the 5th resistance a end links to each other, and the other end links to each other with the first differential signal output; The 6th switch one end links to each other with the other end of the 5th resistance, and the other end links to each other with the first differential signal output;
Described the 6th resistance to the ten resistance are connected in series successively, and the second differential input signal links to each other with an end of the 6th resistance; Minion is closed an end is connected the second differential input signal with the 6th resistance a end and is linked to each other, and the other end links to each other with the second differential signal output; The 8th switch one end is connected the 6th resistance with the 7th resistance a end links to each other, and the other end links to each other with the second differential signal output; The 9th switch one end is connected the 7th resistance with the 8th resistance a end links to each other, and the other end links to each other with the second differential signal output; The tenth switch one end is connected the 8th resistance with the 9th resistance a end links to each other, and the other end links to each other with the second differential signal output; The 11 switch one end is connected the 9th resistance with the tenth resistance a end links to each other, and the other end links to each other with the second differential signal output; Twelvemo is closed an end and is linked to each other with the other end of the tenth resistance, and the other end links to each other with the second differential signal output;
Described the 11 resistance one end is connected the first resistance with the second resistance a end links to each other, and the other end is connected the 6th resistance with the 7th resistance a end links to each other; The 12 resistance one end is connected the second resistance with the 3rd resistance a end links to each other, and the other end is connected the 7th resistance with the 8th resistance a end links to each other; The 13 resistance one end is connected the 3rd resistance with the 4th resistance a end links to each other, and the other end is connected the 8th resistance with the 9th resistance a end links to each other; The 14 resistance one end is connected the 4th resistance with the 5th resistance a end links to each other, and the other end is connected the 9th resistance with the tenth resistance a end links to each other; The 15 resistance one end is connected the 6th switch with the 5th resistance a end links to each other, and the other end is connected the twelvemo pass with the tenth resistance a end links to each other.
4. amplifier according to claim 3, it is characterized in that, described variable gain amplifier comprises: the second differential input stage, source degeneracy switched resistor network, two buffering feedback stages: the first buffering feedback stage and the second buffering feedback stage, two electric current amplifying stages with resistance feedback: the first electric current amplifying stage and the second electric current amplifying stage;
Wherein, described the second differential input stage comprises: the 7th nmos pass transistor and the 8th nmos pass transistor, the NMOS cascade current source current source that is consisted of by the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the PMOS cascade active load that is consisted of by a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor;
Described the 7th nmos pass transistor and the 8th nmos pass transistor, its grid connects respectively the first differential input signal, the second differential input signal, its source electrode connects respectively the drain electrode of the 11 nmos pass transistor, the drain electrode of the tenth bi-NMOS transistor, and its drain electrode connects respectively the transistorized drain electrode of the 3rd PMOS, the transistorized drain electrode of the 4th PMOS;
Described the 9th nmos pass transistor and the tenth nmos pass transistor, its grid connect respectively the source electrode of source follower in the buffering feedback stage, and its drain electrode connects respectively the source electrode of the 11 nmos pass transistor, the source electrode of the 12 NMOS crystal, its source ground;
Described the 11 nmos pass transistor and the 12 NMOS crystal, its grid joins, and joins with the first bias voltage;
A described PMOS transistor and the 2nd PMOS transistor, its grid links to each other, and links to each other with the 4th bias voltage, and its drain electrode links to each other with the transistorized source electrode of the 3rd PMOS, the transistorized source electrode of the 4th PMOS respectively, and its source electrode connects supply voltage;
Described the 3rd PMOS transistor and the 4th PMOS transistor, its grid links to each other, and links to each other with the 3rd bias voltage;
Wherein, described source degeneracy switched resistor network is made of the connection in series-parallel of many groups resistance switch, and described resistance switch string comprises: the 16 resistance, the 13 switch, the 17 resistance;
Wherein, described the first buffering feedback stage and the second buffering feedback stage include: the first nmos source is followed pipe, the second nmos source is followed pipe, the NMOS cascade active load that is made of the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor;
Described the first nmos source is followed pipe and the second nmos source is followed pipe, its grid links to each other, and be connected to the drain electrode of the 7th nmos pass transistor in the second differential input stage, its source electrode links to each other with the drain electrode of the 15 nmos pass transistor, the drain electrode of the 16 nmos pass transistor respectively, and its drain electrode connects supply voltage;
Described the 13 nmos pass transistor and the 14 nmos pass transistor, its grid links to each other, and links to each other with the second bias voltage, and its drain electrode links to each other respectively its source ground with the source electrode of the 15 nmos pass transistor, the source electrode of the 16 nmos pass transistor;
Described the 15 nmos pass transistor and the 16 nmos pass transistor, its grid link to each other, and link to each other with the first bias voltage, and the grid of the 9th nmos pass transistor in the drain electrode of the 15 nmos pass transistor and the second differential input stage links to each other;
Wherein, described the first electric current amplifying stage comprises: the NMOS cascade mirror current source that is made of the 17 nmos pass transistor and the 18 nmos pass transistor, the PMOS cascade active load and the feedback resistance that are made of the 5th PMOS transistor and the 6th PMOS transistor;
Described the 17 nmos pass transistor, its grid links to each other with the source electrode that the second nmos source in the buffering feedback stage is followed pipe, and its drain electrode links to each other its source ground with the 18 transistorized source electrode;
Described the 18 nmos pass transistor, its grid connects the first bias voltage, and drain electrode connects the first differential signal output;
Described the 5th PMOS transistor, its grid connects the 4th bias voltage, and drain electrode connects the transistorized source electrode of the 6th PMOS, and source electrode connects supply voltage;
Described the 6th PMOS transistor, its grid connects the 3rd bias voltage, and drain electrode connects the first differential signal output;
Described feedback resistance is connected between the grid and the first differential signal output of the 17 nmos pass transistor;
Wherein, described the second electric current amplifying stage is identical with the first electric current amplification grade circuit composition, and its feedback resistance is connected between the grid and the second differential signal output of the 17 nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110219918.1A CN102916666B (en) | 2011-08-02 | 2011-08-02 | A kind of broadband programmable gain amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110219918.1A CN102916666B (en) | 2011-08-02 | 2011-08-02 | A kind of broadband programmable gain amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102916666A true CN102916666A (en) | 2013-02-06 |
| CN102916666B CN102916666B (en) | 2015-09-09 |
Family
ID=47614920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110219918.1A Active CN102916666B (en) | 2011-08-02 | 2011-08-02 | A kind of broadband programmable gain amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102916666B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104836535A (en) * | 2015-05-20 | 2015-08-12 | 西安电子科技大学 | Wide variable gain amplifier |
| CN105406823A (en) * | 2015-12-21 | 2016-03-16 | 东南大学 | Differential trans-impedance amplifier circuit in double-negative-feedback and feed-forward common-gate structure |
| CN105429599A (en) * | 2015-12-21 | 2016-03-23 | 东南大学 | Feed-forward common-gate trans-impedance amplifier circuit with active inductor structure |
| CN107749746A (en) * | 2017-11-10 | 2018-03-02 | 北京无线电测量研究所 | A kind of Data control gain amplifier |
| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109660221A (en) * | 2018-12-18 | 2019-04-19 | 四川长虹电器股份有限公司 | A kind of gain-changeable amplifier circuit |
| WO2019196119A1 (en) * | 2018-04-13 | 2019-10-17 | 华为技术有限公司 | Signal attenuation network and wireless signal receiver |
| CN111865244A (en) * | 2020-09-18 | 2020-10-30 | 成都嘉纳海威科技有限责任公司 | Digital control variable gain amplifier |
| CN112506259A (en) * | 2020-11-12 | 2021-03-16 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
| CN112673573A (en) * | 2018-06-22 | 2021-04-16 | 华为技术有限公司 | Fully differential adjustable gain apparatus and method for use therewith |
| CN113114162A (en) * | 2021-03-24 | 2021-07-13 | 中国电子科技集团公司第三十八研究所 | Attenuator circuit for CMOS broadband amplitude-phase multifunctional chip |
| CN108667453B (en) * | 2018-04-09 | 2021-08-31 | 上海集成电路研发中心有限公司 | Low-power-consumption driver circuit with adjustable slew rate |
| CN113746472A (en) * | 2021-08-19 | 2021-12-03 | 上海卫星工程研究所 | Matrix type initiating explosive device driving circuit for deep space probe and control method thereof |
| CN114337710A (en) * | 2022-03-08 | 2022-04-12 | 深圳市鼎阳科技股份有限公司 | Gain switching circuit for receiving radio frequency signal and radio frequency receiver |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874840A (en) * | 1996-04-26 | 1999-02-23 | International Business Machines Corporation | Differential source follower with body effect compensation |
| US7714658B1 (en) * | 2008-11-24 | 2010-05-11 | Linear Technology Corporation | Method and system for variable-gain amplifier |
| US20100315164A1 (en) * | 2009-06-10 | 2010-12-16 | Broadcom Corporation | Constant-Bandwidth Variable Gain Amplifier |
| CN102104367A (en) * | 2011-03-04 | 2011-06-22 | 中兴通讯股份有限公司 | Variable gain amplifier (VGA) |
-
2011
- 2011-08-02 CN CN201110219918.1A patent/CN102916666B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874840A (en) * | 1996-04-26 | 1999-02-23 | International Business Machines Corporation | Differential source follower with body effect compensation |
| US7714658B1 (en) * | 2008-11-24 | 2010-05-11 | Linear Technology Corporation | Method and system for variable-gain amplifier |
| US20100315164A1 (en) * | 2009-06-10 | 2010-12-16 | Broadcom Corporation | Constant-Bandwidth Variable Gain Amplifier |
| CN102104367A (en) * | 2011-03-04 | 2011-06-22 | 中兴通讯股份有限公司 | Variable gain amplifier (VGA) |
Non-Patent Citations (1)
| Title |
|---|
| 黄晓辉 等: "一种用于大规模无线传感网RF前端电缆的dB线性可编程增益放大器", 《微电子学与计算机》 * |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104836535B (en) * | 2015-05-20 | 2017-12-08 | 西安电子科技大学 | A kind of wide cut variable gain amplifier |
| CN104836535A (en) * | 2015-05-20 | 2015-08-12 | 西安电子科技大学 | Wide variable gain amplifier |
| CN105406823A (en) * | 2015-12-21 | 2016-03-16 | 东南大学 | Differential trans-impedance amplifier circuit in double-negative-feedback and feed-forward common-gate structure |
| CN105429599A (en) * | 2015-12-21 | 2016-03-23 | 东南大学 | Feed-forward common-gate trans-impedance amplifier circuit with active inductor structure |
| CN105429599B (en) * | 2015-12-21 | 2018-09-28 | 东南大学 | Feedforward with active inductance structure is total to grid trans-impedance amplifier circuit |
| CN105406823B (en) * | 2015-12-21 | 2018-11-23 | 东南大学 | The difference trans-impedance amplifier circuit of double negative-feedback feedforward common gate structures |
| CN107749746A (en) * | 2017-11-10 | 2018-03-02 | 北京无线电测量研究所 | A kind of Data control gain amplifier |
| CN108667453B (en) * | 2018-04-09 | 2021-08-31 | 上海集成电路研发中心有限公司 | Low-power-consumption driver circuit with adjustable slew rate |
| WO2019196119A1 (en) * | 2018-04-13 | 2019-10-17 | 华为技术有限公司 | Signal attenuation network and wireless signal receiver |
| CN112673573A (en) * | 2018-06-22 | 2021-04-16 | 华为技术有限公司 | Fully differential adjustable gain apparatus and method for use therewith |
| CN112673573B (en) * | 2018-06-22 | 2022-08-26 | 华为技术有限公司 | Fully differential adjustable gain apparatus and method for use therewith |
| CN109167583A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
| CN109660221A (en) * | 2018-12-18 | 2019-04-19 | 四川长虹电器股份有限公司 | A kind of gain-changeable amplifier circuit |
| CN111865244A (en) * | 2020-09-18 | 2020-10-30 | 成都嘉纳海威科技有限责任公司 | Digital control variable gain amplifier |
| CN112506259A (en) * | 2020-11-12 | 2021-03-16 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
| CN113114162A (en) * | 2021-03-24 | 2021-07-13 | 中国电子科技集团公司第三十八研究所 | Attenuator circuit for CMOS broadband amplitude-phase multifunctional chip |
| CN113746472A (en) * | 2021-08-19 | 2021-12-03 | 上海卫星工程研究所 | Matrix type initiating explosive device driving circuit for deep space probe and control method thereof |
| CN114337710A (en) * | 2022-03-08 | 2022-04-12 | 深圳市鼎阳科技股份有限公司 | Gain switching circuit for receiving radio frequency signal and radio frequency receiver |
| CN114337710B (en) * | 2022-03-08 | 2022-06-03 | 深圳市鼎阳科技股份有限公司 | Gain switching circuit for receiving radio frequency signal and radio frequency receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102916666B (en) | 2015-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102916666B (en) | A kind of broadband programmable gain amplifier | |
| CN102916667B (en) | A kind of broadband programmable gain amplifier of 2dB step-length | |
| CN103051298B (en) | Programmable Gain Amplifier Circuit and programmable gain amplifier | |
| CN102790595B (en) | Single ended differential gain amplifier with configurable radio frequency broadband gain | |
| CN103248324A (en) | High-linearity low-noise amplifier | |
| CN106921346B (en) | High linearity broadband up-mixer | |
| CN104270100B (en) | A kind of low-power consumption low-noise amplifier for strengthening technology using positive feedback technique and active transconductance | |
| CN104935266B (en) | A kind of fully integrated pseudo-differential low-noise amplifiers of CMOS for working in 71~76GHz | |
| CN103051299B (en) | Programmable gain amplifier applicable to transmitting end of communication system | |
| CN103762947A (en) | Cross-coupling input low-noise trans-conductance amplifier | |
| CN111245373B (en) | Ultra-wideband low-noise amplifier adopting partial active negative feedback technology and positive feedback technology | |
| CN216162678U (en) | Radio frequency power amplifier | |
| CN102801389A (en) | Ultra-low power consumption low-noise amplifier | |
| CN102868377A (en) | Total 3G (Third Generation Telecommunication) CMOS (Complementary Metal-Oxide-Semiconductor Transistor) differential low-noise amplifier based on controllable active inductor | |
| CN107196611A (en) | Broadband single-ended transfer difference low-noise amplifier | |
| CN109167578B (en) | Ultra-wideband low-noise amplifier with active inductor | |
| CN104779917A (en) | Receiver front-end circuit based on integrated inductor noise cancelling technology | |
| CN102638227A (en) | Ultra-wideband frequency mixer circuit with on-chip active balanced-unbalanced converter | |
| SG185739A1 (en) | Amplifier and transceiver including the amplifier | |
| Kim et al. | 58–72 GHz CMOS wideband variable gain low-noise amplifier | |
| CN103379063A (en) | Linear equalizer | |
| CN105720938A (en) | dB linear ultra-wideband variable gain amplifier | |
| CN202772848U (en) | Fully third generation telecommunication (3G) complementary metal oxide semiconductor (CMOS) difference low noise amplifier based on controllable active inductor | |
| CN102332866B (en) | High-linearity upper mixer | |
| CN104660185A (en) | Low-power-consumption ultra-wide-band low-noise amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201215 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220525 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
|
| TR01 | Transfer of patent right |