CN103078593A - Lower-power-supply-voltage high-conversion-gain passive mixer - Google Patents
Lower-power-supply-voltage high-conversion-gain passive mixer Download PDFInfo
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Abstract
The invention discloses a lower-power-supply-voltage high-conversion-gain passive mixer, which comprises an input transconductance amplification stage, a switch mixing stage and an output transimpedance amplification stage. The input transconductance amplification stage adopts a push-pull transconductance structure. In order to satisfy the requirement of 0.6V power supply voltage, a common-mode negative feedback circuit based on two stages of common-source amplifiers is provided to enable transconductance-stage common mode bias voltage to be equal to fixed grid-source voltage. The switch mixing stage is used for modulating radio-frequency current output by the transconductance amplification stage and outputting medium-frequency current signals through low-pass filtering. The output transimpedance amplification stage is used for absorbing the medium-frequency current output by the switch mixing stage and outputting a mirror, and finally medium-frequency output voltage is obtained on a load resistor. Moreover, a transimpedance amplifier under low power supply voltage is provided. The transimpedance amplifier is based on a negative feedback structure, the output of low input impedance within a medium frequency band is realized, and the current utilization efficiency and the port isolation are improved. The lower-power-supply-voltage high-conversion-gain passive mixer with the structure has the advantages of low power consumption, high conversion gain and good port isolation.
Description
Technical field
The present invention relates to a kind of frequency mixer, be specifically related to high-conversion-gain passive frequency mixer under a kind of low supply voltage.
Background technology
In the radiofrequency signal receiver, the effect of frequency mixer is that the input radio frequency signal is downconverted to intermediate frequency or base band so that subsequent module is processed.Consider from whole receiver, frequency mixer should have higher conversion gain with the impact on whole receiver noise factor of the noise that suppresses rear class intermediate frequency amplifier circuit and filter circuit.In addition, frequency mixer itself should have preferably interport isolation to reduce the local-oscillator leakage at the intermediate frequency end.Along with the continuous progress of CMOS technique, supply voltage constantly reduces, and constantly proposes the problem of complexity for the design of frequency mixer.In recent years, silicon solar cell more and more is applied in the Circuits System, and silicon solar cell only provides 0.6 volt of supply voltage, so the frequency mixer of design low supply voltage high-gain is significant, will expand the application of silicon solar cell power supply circuits system.
Frequency mixer can be divided into active mixer and passive frequency mixer; active mixer has the enlarging function to signal in the lump when mixing function is provided; can effectively suppress comparatively serious intermediate-frequency circuit noise; but active mixer itself has larger noise; especially in the zero intermediate frequency reciver structure; its flicker noise can be brought certain influence; passive frequency mixer does not then have quiescent current; its flicker noise has also reduced greatly, and the linearity of passive frequency mixer can be higher than active mixer usually.
In the classical mixing structure, when in the transconductance stage radio-frequency voltage being converted to radio-frequency current, because the signal that receiver is accepted is generally very little, the transconductance value of traditional transconductance stage circuit is general in addition is the transconductance value of input transistors only, its transconductance value is limited under Low-bias Current, and conversion gain is on the low side.
Summary of the invention
Goal of the invention: for the problem and shortage of above-mentioned prior art existence, the purpose of this invention is to provide high-conversion-gain passive frequency mixer under a kind of low supply voltage, so that the transconductance value of transconductance stage circuit is strengthened greatly, reduce as far as possible the input resistance of output stage trans-impedance amplifier.
Technical scheme: for achieving the above object, the technical solution used in the present invention is high-conversion-gain passive frequency mixer under a kind of low supply voltage, comprises that input mutual conductance amplifying stage, passive mixing switch are to striding the resistance amplifying stage with output;
Wherein, input mutual conductance amplifying stage comprises NMOS pipe, the 2nd NMOS pipe, PMOS pipe, the 2nd PMOS pipe as radio frequency mutual conductance pipe, first, second, the 5th, the 6th resistance, first to fourth electric capacity, be used for reading the 3rd resistance and the 4th resistance of output common mode level, the 3rd NMOS pipe and the 3rd PMOS pipe that form common mode feedback circuit first order current source loads common source amplifying circuit, the 4th PMOS pipe and the 8th resistance that form common mode feedback circuit second level ohmic load common source amplifying circuit, and the 7th resistance and the 5th electric capacity that form the RC compensating network;
Passive mixing switch is to comprising the 4th to the 7th NMOS pipe, the 6th to the 8th electric capacity;
Output is striden the resistance amplifying stage and is comprised the 8th, the 9th, the 13, the 14 NMOS pipe, as the 5th of current source, the 7th PMOS pipe, with the 12 of common grid mode work, the 17 NMOS pipe, the 11, the 14 resistance, the 6th of the first order current source loads common source amplifying circuit of composition feedback arrangement, the 8th PMOS manages and is used as the tenth of current source, the 15 NMOS pipe, the 11 of the second level ohmic load common source amplifying circuit of composition feedback arrangement, the 16 NMOS pipe and the tenth, the 13 resistance, and form the 9th of RC compensating network, the 12 resistance and the 9th, the tenth electric capacity;
Wherein:
It is anodal that the top crown of the first electric capacity connects the input radio frequency signal, and its bottom crown connects the grid of a NMOS pipe; The top crown of the second electric capacity connects input radio frequency signal negative pole, and its bottom crown connects the grid of the 2nd NMOS pipe; The grid of the one NMOS pipe connects the negative terminal of the first resistance, and its drain electrode connects the anode of the 3rd resistance, its source ground; The grid of the 2nd NMOS pipe connects the negative terminal of the second resistance, and its drain electrode connects the anode of the 4th resistance, its source ground; The anode of the first resistance and the second resistance all connects the first bias voltage; The top crown of the 3rd electric capacity connects the grid of a NMOS pipe, and its bottom crown connects the grid of a PMOS pipe; The top crown of the 4th electric capacity connects the grid of the 2nd NMOS pipe, and its bottom crown connects the grid of the 2nd PMOS pipe; The grid of the one PMOS pipe connects the negative terminal of the 5th resistance, and its drain electrode connects the anode of the 3rd resistance, and its source electrode connects supply voltage; The grid of the 2nd PMOS pipe connects the negative terminal of the 6th resistance, and its drain electrode connects the anode of the 4th resistance, and its source electrode connects supply voltage; The grid of the 3rd NMOS pipe connects the negative terminal of the 3rd resistance and the 4th resistance, its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS pipe; The grid of the 3rd PMOS pipe connects the second bias voltage, its source ground, and its drain electrode connects the grid of the 4th PMOS pipe; The grid of the 4th PMOS pipe connects the anode of the 7th resistance, and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance and the 6th resistance; The drain electrode of positive termination the 4th PMOS pipe of the 8th resistance, its negativing ending grounding; The top crown of the 5th electric capacity connects the negative terminal of the 7th resistance, its bottom crown ground connection; The top crown of the 6th electric capacity connects the drain electrode of a NMOS pipe, and its bottom crown connects the source electrode of the 4th, the 5th NMOS pipe; The top crown of the 7th electric capacity connects the drain electrode of the 2nd NMOS pipe, and its bottom crown connects the source electrode of the 6th, the 7th NMOS pipe; Four, the grid of the 7th NMOS pipe connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS pipe connects the negative pole of local oscillation signal; Four, the drain electrode of the 6th NMOS pipe connects the top crown of the 8th electric capacity, and the drain electrode of the 5th, the 7th NMOS pipe connects the bottom crown of the 8th electric capacity; The grid of the 8th NMOS pipe connects the negative terminal of the tenth resistance (R10), and its drain electrode connects the drain electrode of the 5th PMOS pipe, its source ground; The grid of the 5th PMOS pipe connects the 3rd bias voltage, and its drain electrode connects the grid of the 6th PMOS pipe, and its source electrode connects supply voltage; The grid of the 6th PMOS pipe connects the anode of the 9th resistance, and its drain electrode connects the drain electrode of the tenth NMOS pipe, and its source electrode connects supply voltage; The grid of the tenth NMOS pipe connects the 4th bias voltage, and its drain electrode connects the grid of the 11 NMOS pipe, its source ground; The grid of the 11 NMOS pipe connects the bottom crown of the 9th electric capacity, and its drain electrode connects the negative terminal of the tenth resistance, its source ground; The top crown of the 9th electric capacity connects the negative terminal of the 9th resistance, and its bottom crown connects the grid of the 11 NMOS pipe; The positive termination supply voltage of the tenth resistance, its negative terminal connects the grid of the 9th NMOS pipe; The grid of the 9th NMOS pipe connects the grid of the 8th NMOS pipe, and its drain electrode connects the source electrode of the 12 NMOS pipe, its source ground; The grid of the 12 NMOS pipe connects the 5th bias voltage, and its drain electrode connects the output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS pipe; The positive termination supply voltage of the 11 resistance, its negative terminal connects the output voltage anode; The grid of the 13 NMOS pipe connects the negative terminal of the 13 resistance, and its drain electrode connects the drain electrode of the 7th PMOS pipe, its source ground; The grid of the 7th PMOS pipe connects the 3rd bias voltage, and its drain electrode connects the grid of the 8th PMOS pipe, and its source electrode connects supply voltage; The grid of the 8th PMOS pipe connects the anode of the 12 resistance, and its drain electrode connects the drain electrode of the 15 NMOS pipe, and its source electrode connects supply voltage; The grid of the 15 NMOS pipe connects the 4th bias voltage, and its drain electrode connects the grid of the 16 NMOS pipe, its source ground; The grid of the 16 NMOS pipe connects the bottom crown of the tenth electric capacity, and its drain electrode connects the negative terminal of the 13 resistance, its source ground; The top crown of the tenth electric capacity connects the negative terminal of the 12 resistance, and its bottom crown connects the grid of the 16 NMOS pipe; The positive termination supply voltage of the 13 resistance, its negative terminal connects the grid of the 14 NMOS pipe; The grid of the 14 NMOS pipe connects the grid of the 13 NMOS pipe, and its drain electrode connects the source electrode of the 17 NMOS pipe, its source ground; The grid of the 17 NMOS pipe connects the 5th bias voltage, and its drain electrode connects the output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS pipe; The positive termination supply voltage of the 14 resistance, its negative terminal connects the output voltage negative terminal.
Further, described first, second, the 5th, the 6th resistance is biasing resistor, described the 11, the 14 resistance is load resistance, described the first to fourth, the 6th, the 7th electric capacity is coupling capacitance, described the 8th electric capacity is filter capacitor.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
1. supply voltage is low.Frequency mixer of the present invention can be operated under the low supply voltage of 0.6V.
2. conversion gain is high.The input mutual conductance amplifying stage of frequency mixer of the present invention adopts to recommend and amplifies mutual conductance and strengthen structure, so that mutual conductance strengthens greatly, thereby improves the frequency mixer conversion gain.
3. intermediate frequency-prevention at radio-frequency port isolation is high.Output is striden the resistance amplifying stage based on negative feedback structure, be further reduced so that stride the input impedance of resistance amplifying stage, thereby fluctuate very little so that the voltage of intermediate frequency of resistance amplifying stage input is striden in output, reduced like this voltage feed-through of intermediate-freuqncy signal toward the transconductance stage output, stablize the transconductance stage output voltage, improved electric current utilization ratio and interport isolation.
In sum, transconductance-enhancing passive frequency mixer has characteristics low in energy consumption, that the mutual conductance of input mutual conductance amplifying stage is high, conversion gain is high, interport isolation is good under this 0.6V low supply voltage.
Description of drawings
Fig. 1 is transconductance-enhancing passive frequency mixer circuit theory diagrams under the low supply voltage of the present invention;
Fig. 2 is the conversion gain simulation result figure of transconductance-enhancing passive frequency mixer under the low supply voltage of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
As shown in Figure 1, high-conversion-gain passive frequency mixer under a kind of low supply voltage of the present invention comprises and has mutual conductance and increase powerful input mutual conductance amplifying stage, passive mixing switch pair, and the resistance amplifying stage is striden in output.This frequency mixer adopts to recommend and amplifies mutual conductance enhancing structure, so that mutual conductance strengthens greatly; Simultaneously, output is striden the resistance amplifying stage based on feedback arrangement, is further reduced so that stride the input impedance of resistance amplifying stage, has improved electric current utilization ratio and interport isolation.The characteristics such as this mixer architecture has low in energy consumption, and conversion gain is high, interport isolation is good.
Input mutual conductance amplifying stage comprises as first of radio frequency mutual conductance pipe, the second N-type MOS transistor (hereinafter to be referred as the NMOS pipe) NM1, NM2 and first, the 2nd P type MOS transistor (hereinafter to be referred as the PMOS pipe) PM1, PM2, biasing resistor R1, R2, R5, R6, coupling capacitance C1, C2, C3, C4, be used for reading the 3rd of output common mode level, the 4th resistance R 3, R4, the 3rd NMOS pipe NM3 and the 3rd PMOS pipe PM3 that form common mode feedback circuit first order current source loads common source amplifying circuit, the 4th PMOS pipe PM4 and the 8th resistance R 8 that form common mode feedback circuit second level ohmic load common source amplifying circuit, and the 7th resistance R 7 and the 5th capacitor C 5 that form the RC compensating network; Passive mixing switch is to comprising the 4th to the 7th NMOS pipe NM4-NM7, input coupling capacitance C6, C7, output filter capacitor C8; Output is striden the resistance amplifying stage and is comprised the 8th, the 9th NMOS manages NM8, NM9 and the 13, the 14 NMOS manages NM13, NM14, as the 5th of current source, the 7th PMOS manages PM5, PM7, with the 12 of common grid mode work, the 17 NMOS manages NM12, NM17, load resistance R11 and R14, the 6th of the first order current source loads common source amplifying circuit of composition feedback arrangement, the 8th PMOS manages PM6, PM8 and as current source the tenth, the 15 NMOS manages NM10, NM15, the 11 of the second level ohmic load common source amplifying circuit of composition feedback arrangement, the 16 NMOS manages NM11, NM16 and the tenth, the 13 resistance R 10, R13, and form the 9th of RC compensating network, the 12 resistance R 9, R12 and the 9th, the tenth capacitor C 9, C10.
Input radio frequency signal positive pole connects the top crown of the first capacitor C 1, and the bottom crown of the first capacitor C 1 connects the grid of NMOS pipe NM1; Input radio frequency signal negative pole connects the top crown of the second capacitor C 2, and the bottom crown of the second capacitor C 2 connects the grid of the 2nd NMOS pipe NM2.The grid of the one NMOS pipe NM1 connects the negative terminal of biasing resistor R1, and its drain electrode connects the anode of the 3rd resistance R 3, its source ground; The grid of the 2nd NMOS pipe NM2 connects the negative terminal of biasing resistor R2, and its drain electrode connects the anode of the 4th resistance R 4, its source ground.The anode of biasing resistor R1 and R2 all connects the first bias voltage 1.The top crown of the 3rd capacitor C 3 connects the grid of NMOS pipe NM1, and its bottom crown connects the grid of PMOS pipe PM1; The top crown of the 4th capacitor C 4 connects the grid of the 2nd NMOS pipe NM2, and its bottom crown connects the grid of the 2nd PMOS pipe PM2.The grid of the one PMOS pipe PM1 connects the negative terminal of biasing resistor R5, and its drain electrode connects the anode of the 3rd resistance R 3, and its source electrode connects supply voltage; The grid of the 2nd PMOS pipe PM2 connects the negative terminal of biasing resistor R6, and its drain electrode connects the anode of the 4th resistance R 4, and its source electrode connects supply voltage.The grid of the 3rd NMOS pipe NM3 connects the negative terminal of the third and fourth resistance R 3 and R4, its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS pipe PM3.The grid of the 3rd PMOS pipe PM3 connects the second bias voltage 2, its source ground, and its drain electrode connects the grid of the 4th PMOS pipe PM4.The grid of the 4th PMOS pipe PM4 connects the anode of the 7th resistance R 7, and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance R 5 and the 6th resistance R 6.The drain electrode of positive termination the 4th PMOS pipe PM4 of the 8th resistance R 8, its negativing ending grounding.The top crown of the 5th capacitor C 5 connects the negative terminal of the 7th resistance R 7, its bottom crown ground connection.The top crown of the 6th capacitor C 6 connects the drain electrode of NMOS pipe NM1, and its bottom crown connects the source electrode of the 4th, the 5th NMOS pipe NM4, NM5; The top crown of the 7th capacitor C 7 connects the drain electrode of the 2nd NMOS pipe NM2, and its bottom crown connects the source electrode of the 6th, the 7th NMOS pipe NM6, NM7.Four, the grid of the 7th NMOS pipe NM4, NM7 connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS pipe NM5, NM6 connects the negative pole of local oscillation signal.Four, the drain electrode of the 6th NMOS pipe NM4, NM6 connects the top crown of the 8th capacitor C 8, and the drain electrode of the 5th, the 7th NMOS pipe NM5, NM7 connects the bottom crown of the 8th capacitor C 8.The grid of the 8th NMOS pipe NM8 connects the negative terminal of the tenth resistance R 10, and its drain electrode connects the drain electrode of the 5th PMOS pipe PM5, its source ground.The grid of the 5th PMOS pipe PM5 connects the 3rd bias voltage 3, and its drain electrode connects the grid of the 6th PMOS pipe PM6, and its source electrode connects supply voltage.The grid of the 6th PMOS pipe PM6 connects the anode of the 9th resistance R 9, and its drain electrode connects the drain electrode of the tenth NMOS pipe NM10, and its source electrode connects supply voltage.The grid of the tenth NMOS pipe NM10 connects the 4th bias voltage 4, and its drain electrode connects the grid of the 11 NMOS pipe NM11, its source ground.The grid of the 11 NMOS pipe NM11 connects the bottom crown of the 9th capacitor C 9, and its drain electrode connects the negative terminal of the tenth resistance R 10, its source ground.The top crown of the 9th capacitor C 9 connects the negative terminal of the 9th resistance R 9, and its bottom crown connects the grid of the 11 NMOS pipe NM11.The positive termination supply voltage of the tenth resistance R 10, its negative terminal connect the grid of the 9th NMOS pipe NM9.The grid of the 9th NMOS pipe NM9 connects the grid of the 8th NMOS pipe NM8, and its drain electrode connects the source electrode of the 12 NMOS pipe NM12, its source ground.The grid of the 12 NMOS pipe NM12 connects the 5th bias voltage 5, and its drain electrode connects the output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS pipe NM9.The positive termination supply voltage of the 11 resistance R 11, its negative terminal connects the output voltage anode.The grid of the 13 NMOS pipe NM13 connects the negative terminal of the 13 resistance R 13, and its drain electrode connects the drain electrode of the 7th PMOS pipe PM7, its source ground.The grid of the 7th PMOS pipe PM7 connects the 3rd bias voltage 3, and its drain electrode connects the grid of the 8th PMOS pipe PM8, and its source electrode connects supply voltage.The grid of the 8th PMOS pipe PM8 connects the anode of the 12 resistance R 12, and its drain electrode connects the drain electrode of the 15 NMOS pipe NM15, and its source electrode connects supply voltage.The grid of the 15 NMOS pipe NM15 connects the 4th bias voltage 4, and its drain electrode connects the grid of the 16 NMOS pipe NM16, its source ground.The grid of the 16 NMOS pipe NM16 connects the bottom crown of the tenth capacitor C 10, and its drain electrode connects the negative terminal of the 13 resistance R 13, its source ground.The top crown of the tenth capacitor C 10 connects the negative terminal of the 12 resistance R 12, and its bottom crown connects the grid of the 16 NMOS pipe NM16.The positive termination supply voltage of the 13 resistance R 13, its negative terminal connect the grid of the 14 NMOS pipe NM14.The grid of the 14 NMOS pipe NM14 connects the grid of the 13 NMOS pipe NM13, and its drain electrode connects the source electrode of the 17 NMOS pipe NM17, its source ground.The grid of the 17 NMOS pipe NM17 connects the 5th bias voltage 5, and its drain electrode connects the output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS pipe NM14.The positive termination supply voltage of the 14 resistance R 14, its negative terminal connects the output voltage negative terminal.
Transconductance-enhancing passive frequency mixer under the above-mentioned low supply voltage can work under the 0.6V low supply voltage, and has higher conversion gain and interport isolation preferably.The radio-frequency current signal coupling of input mutual conductance amplifying stage output enters output and strides the resistance amplifying stage to the switch mixer stage after the frequency conversion of mixing switch.In order to obtain higher conversion gain, input mutual conductance amplifying stage has adopted to recommend and has amplified mutual conductance enhancing structure, utilize coupling capacitance C3, C4 the input radio frequency signal to be coupled to the grid of first, second PMOS pipe PM1, PM2 from the grid of first, second NMOS pipe NM1, NM2, and adopt common mode feedback loop to provide direct current biasing for first, second PMOS pipe PM1, PM2, thereby make the transconductance value of input mutual conductance amplifying stage rise to g
Mn+ g
Mp, g wherein
MnBe the transconductance value of first, second NMOS pipe NM1, NM2, g
MpTransconductance value for first, second PMOS pipe PM1, PM2.In order to obtain preferably interport isolation, output is striden the resistance amplifying stage based on feedback arrangement, so that the output frequency range from the 8th, the resistance seen into of the drain terminal of the 13 NMOS pipe NM8, NM13 is very low, the electric current of intermediate frequency that mixing is obtained all sucks load stage, finally by the 9th NMOS pipe NM9 the 8th NMOS pipe NM8 and the 14 NMOS pipe NM14 are copied the current mirror that the 13 NMOS manages NM13, form the intermediate frequency output voltage in output loading.When signal frequency is relatively low, and the 8th, the extremely low equivalent input resistance of the 13 NMOS pipe NM8, NM13 so that mutual conductance amplifying stage output node for the equivalence of output low frequency signal for exchanging ground connection, so that intermediate-freuqncy signal is as far as possible low to improve intermediate frequency-prevention at radio-frequency port isolation in the amplitude of oscillation of this port; For the input radio frequency signal, be connected on the capacitor C 8 of mixing output so that for radiofrequency signal, the same equivalence of transconductance stage output node has reduced the radio-frequency voltage amplitude of oscillation of this Nodes for exchanging ground, has improved electric current utilization ratio and the linearity.Simultaneously, the C5 that between transconductance stage and mixer stage, connects, C6, the impact of blocking-up direct current signal; Mixer stage output meets C7, make mixing after high-frequency signal filtered.
Illustrate that below by simulation comparison the present invention has advantages of high-conversion-gain under the 0.6V low supply voltage.Adopt
The Virtuoso simulation software carries out the emulation of frequency mixer conversion gain.Figure 2 shows that the conversion gain simulation result of transconductance-enhancing passive frequency mixer under the 0.6V low supply voltage of the present invention, as can be seen from the figure, the conversion gain of this frequency mixer can reach more than the 25dB.
Claims (2)
1. high-conversion-gain passive frequency mixer under the low supply voltage is characterized in that: comprise that input mutual conductance amplifying stage, passive mixing switch are to striding the resistance amplifying stage with output;
Wherein, input mutual conductance amplifying stage comprises the NMOS pipe (NM1) as radio frequency mutual conductance pipe, the 2nd NMOS manages (NM2), the one PMOS manages (PM1), the 2nd PMOS manages (PM2), first, second, the 5th, the 6th resistance (R1, R2, R5, R6), first to fourth electric capacity (C1, C2, C3, C4), be used for reading the 3rd resistance (R3) and the 4th resistance (R4) of output common mode level, the 3rd NMOS pipe (NM3) and the 3rd PMOS pipe (PM3) that form common mode feedback circuit first order current source loads common source amplifying circuit, the 4th PMOS pipe (PM4) and the 8th resistance (R8) that form common mode feedback circuit second level ohmic load common source amplifying circuit, and the 7th resistance (R7) and the 5th electric capacity (C5) that form the RC compensating network;
Passive mixing switch is to comprising the 4th to the 7th NMOS pipe (NM4, NM5, NM6, NM7), the 6th to the 8th electric capacity (C6, C7, C8);
Output is striden the resistance amplifying stage and is comprised the 8th, the 9th, the 13, the 14 NMOS manages (NM8, NM9, NM13, NM14), as the 5th of current source, the 7th PMOS manages (PM5, PM7), with the 12 of common grid mode work, the 17 NMOS manages (NM12, NM17), the 11, the 14 resistance (R11, R14), the 6th of the first order current source loads common source amplifying circuit of composition feedback arrangement, the 8th PMOS manages (PM6, PM8) and as current source the tenth, the 15 NMOS manages (NM10, NM15), the 11 of the second level ohmic load common source amplifying circuit of composition feedback arrangement, the 16 NMOS manages (NM11, NM16) and the tenth, the 13 resistance (R10, and form the 9th of RC compensating network R13),, the 12 resistance (R9, R12) and the 9th, the tenth electric capacity (C9, C10);
Wherein:
It is anodal that the top crown of the first electric capacity (C1) connects the input radio frequency signal, and its bottom crown connects the grid of NMOS pipe (NM1); The top crown of the second electric capacity (C2) connects input radio frequency signal negative pole, and its bottom crown connects the grid of the 2nd NMOS pipe (NM2); The grid of the one NMOS pipe (NM1) connects the negative terminal of the first resistance (R1), and its drain electrode connects the anode of the 3rd resistance (R3), its source ground; The grid of the 2nd NMOS pipe (NM2) connects the negative terminal of the second resistance (R2), and its drain electrode connects the anode of the 4th resistance (R4), its source ground; The anode of the first resistance (R1) and the second resistance (R2) all connects the first bias voltage (1); The top crown of the 3rd electric capacity (C3) connects the grid of NMOS pipe (NM1), and its bottom crown connects the grid of PMOS pipe (PM1); The top crown of the 4th electric capacity (C4) connects the grid of the 2nd NMOS pipe (NM2), and its bottom crown connects the grid of the 2nd PMOS pipe (PM2); The grid of the one PMOS pipe (PM1) connects the negative terminal of the 5th resistance (R5), and its drain electrode connects the anode of the 3rd resistance (R3), and its source electrode connects supply voltage; The grid of the 2nd PMOS pipe (PM2) connects the negative terminal of the 6th resistance (R6), and its drain electrode connects the anode of the 4th resistance (R4), and its source electrode connects supply voltage; The grid of the 3rd NMOS pipe (NM3) connects the negative terminal of the 3rd resistance (R3) and the 4th resistance (R4), its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS pipe (PM3); The grid of the 3rd PMOS pipe (PM3) connects the second bias voltage (2), its source ground, and its drain electrode connects the grid of the 4th PMOS pipe (PM4); The grid of the 4th PMOS pipe (PM4) connects the anode of the 7th resistance (R7), and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance (R5) and the 6th resistance (R6); The drain electrode of positive termination the 4th PMOS pipe (PM4) of the 8th resistance (R8), its negativing ending grounding; The top crown of the 5th electric capacity (C5) connects the negative terminal of the 7th resistance (R7), its bottom crown ground connection; The top crown of the 6th electric capacity (C6) connects the drain electrode of NMOS pipe (NM1), and its bottom crown connects the source electrode of the 4th, the 5th NMOS pipe (NM4, NM5); The top crown of the 7th electric capacity (C7) connects the drain electrode of the 2nd NMOS pipe (NM2), and its bottom crown connects the source electrode of the 6th, the 7th NMOS pipe (NM6, NM7); Four, the grid of the 7th NMOS pipe (NM4, NM7) connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS pipe (NM5, NM6) connects the negative pole of local oscillation signal; Four, the drain electrode of the 6th NMOS pipe (NM4, NM6) connects the top crown of the 8th electric capacity (C8), and the drain electrode of the 5th, the 7th NMOS pipe (NM5, NM7) connects the bottom crown of the 8th electric capacity (C8); The grid of the 8th NMOS pipe (NM8) connects the negative terminal of the tenth resistance (R10), and its drain electrode connects the drain electrode of the 5th PMOS pipe (PM5), its source ground; The grid of the 5th PMOS pipe (PM5) connects the 3rd bias voltage (3), and its drain electrode connects the grid of the 6th PMOS pipe (PM6), and its source electrode connects supply voltage; The grid of the 6th PMOS pipe (PM6) connects the anode of the 9th resistance (R9), and its drain electrode connects the drain electrode of the tenth NMOS pipe (NM10), and its source electrode connects supply voltage; The grid of the tenth NMOS pipe (NM10) connects the 4th bias voltage (4), and its drain electrode connects the grid of the 11 NMOS pipe (NM11), its source ground; The grid of the 11 NMOS pipe (NM11) connects the bottom crown of the 9th electric capacity (C9), and its drain electrode connects the negative terminal of the tenth resistance (R10), its source ground; The top crown of the 9th electric capacity (C9) connects the negative terminal of the 9th resistance (R9), and its bottom crown connects the grid of the 11 NMOS pipe (NM11); The positive termination supply voltage of the tenth resistance (R10), its negative terminal connect the grid of the 9th NMOS pipe (NM9); The grid of the 9th NMOS pipe (NM9) connects the grid of the 8th NMOS pipe (NM8), and its drain electrode connects the source electrode of the 12 NMOS pipe (NM12), its source ground; The grid of the 12 NMOS pipe (NM12) connects the 5th bias voltage (5), and its drain electrode connects the output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS pipe (NM9); The positive termination supply voltage of the 11 resistance (R11), its negative terminal connects the output voltage anode; The grid of the 13 NMOS pipe (NM13) connects the negative terminal of the 13 resistance (R13), and its drain electrode connects the drain electrode of the 7th PMOS pipe (PM7), its source ground; The grid of the 7th PMOS pipe (PM7) connects the 3rd bias voltage (3), and its drain electrode connects the grid of the 8th PMOS pipe (PM8), and its source electrode connects supply voltage; The grid of the 8th PMOS pipe (PM8) connects the anode of the 12 resistance (R12), and its drain electrode connects the drain electrode of the 15 NMOS pipe (NM15), and its source electrode connects supply voltage; The grid of the 15 NMOS pipe (NM15) connects the 4th bias voltage (4), and its drain electrode connects the grid of the 16 NMOS pipe (NM16), its source ground; The grid of the 16 NMOS pipe (NM16) connects the bottom crown of the tenth electric capacity (C10), and its drain electrode connects the negative terminal of the 13 resistance (R13), its source ground; The top crown of the tenth electric capacity (C10) connects the negative terminal of the 12 resistance (R12), and its bottom crown connects the grid of the 16 NMOS pipe (NM16); The positive termination supply voltage of the 13 resistance (R13), its negative terminal connect the grid of the 14 NMOS pipe (NM14); The grid of the 14 NMOS pipe (NM14) connects the grid of the 13 NMOS pipe (NM13), and its drain electrode connects the source electrode of the 17 NMOS pipe (NM17), its source ground; The grid of the 17 NMOS pipe (NM17) connects the 5th bias voltage (5), and its drain electrode connects the output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS pipe (NM14); The positive termination supply voltage of the 14 resistance (R14), its negative terminal connects the output voltage negative terminal.
2. high-conversion-gain passive frequency mixer under the described low supply voltage according to claim 1, it is characterized in that: described first, second, the 5th, the 6th resistance (R1, R2, R5, R6) is biasing resistor, described the 11, the 14 resistance (R11, R14) is load resistance, described the first to fourth, the 6th, the 7th electric capacity (C1, C2, C3, C4, C6, C7) is coupling capacitance, and described the 8th electric capacity (C8) is filter capacitor.
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| CN106026930A (en) * | 2016-07-19 | 2016-10-12 | 东南大学 | Low-power-consumption high-conversion-gain passive frequency mixer |
| CN106026930B (en) * | 2016-07-19 | 2018-07-17 | 东南大学 | A kind of low-power consumption high-conversion-gain passive frequency mixer |
| CN109120243A (en) * | 2018-07-23 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | Clock driver circuit |
| CN116723605A (en) * | 2023-08-10 | 2023-09-08 | 上海芯龙半导体技术股份有限公司 | Compensation circuit of LED power supply and LED power supply |
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