CN103077970A - Super junction device and manufacturing method thereof - Google Patents
Super junction device and manufacturing method thereof Download PDFInfo
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- CN103077970A CN103077970A CN2011103301312A CN201110330131A CN103077970A CN 103077970 A CN103077970 A CN 103077970A CN 2011103301312 A CN2011103301312 A CN 2011103301312A CN 201110330131 A CN201110330131 A CN 201110330131A CN 103077970 A CN103077970 A CN 103077970A
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Abstract
The invention discloses a super junction device. Thin layers at all parts of a current flow region are equal in width ratio; the width ratio of at least part of thin layers of a terminal protection structure is less than that of the thin layers of the current flow region; impurities at all parts of the current flow region are equal in total quantity ratio; the total quantity ratio of at least part of impurities of the terminal protection structure is less than that of the impurities of the current flow region; and the bottom part of at least one P-type thin layer located in the terminal protection structure is not contacted with an N+silicon substrate. The invention also discloses a manufacturing method for the super junction device. According to the super junction device disclosed by the invention, the optimum balance of the P/N thin layers of the terminal protection structure is kept, and the breakdown voltage of a device terminal is higher than the reverse breakdown voltage of a device unit. Whereas, the P-type doping total quantity is higher than the N-type doping total quantity in the P/N thin layers of the current flow region, and therefore, the current surge resistance of the device and the consistency of the current surge resistance can be improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of super-junction device; The invention still further relates to a kind of manufacture method of super-junction device.
Background technology
Super junction MOSFET adopts new structure of voltage-sustaining layer, utilize P type semiconductor thin layer and the N type semiconductor thin layer of a series of alternative arrangement under cut-off state, under low voltage, just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted, realize that electric charge compensates mutually, thereby make P type semiconductor thin layer and N type semiconductor thin layer under high-dopant concentration, can realize high puncture voltage, thereby obtain simultaneously low on-resistance and high-breakdown-voltage, the power MOSFET theoretical limit breaks traditions.In US Patent No. 5216275, the P type semiconductor thin layer of above alternative arrangement links to each other with the N+ substrate with the N type semiconductor thin layer; In US Patent No. 6630698B1, middle P type semiconductor thin layer and N type semiconductor thin layer and N+ substrate can have the interval greater than 0.
In the prior art, the formation of P type semiconductor thin layer and N type semiconductor thin layer is a kind of to be then to carry out photoetching and injection by epitaxial growth, repeatedly this process obtains P type semiconductor thin layer and the N type semiconductor thin layer of the thickness that needs repeatedly, among the MOSFET of this technique more than 600V, generally need to repeat more than 5 times, production cost and production cycle are long.Another kind is after the extension that needs thickness by a kind of type of a secondary growth, carries out the etching of groove, inserts afterwards the silicon of opposite types in groove; The method process costs and process cycle are short; But if certain thickness were arranged between this thin layer and the substrate, owing to certain technique change that is etched with of groove, gash depth also just would be easy to change, and therefore causes the device reverse breakdown voltage excursion larger; Simultaneously, under same epitaxial thickness, can to touch the reverse breakdown voltage of N+ substrate than P type semiconductor thin layer and N type semiconductor thin layer not low for the reverse breakdown voltage of device when P type semiconductor thin layer and N type semiconductor thin layer do not touch the N+ substrate.
Summary of the invention
Technical problem to be solved by this invention provides a kind of super-junction device, can improve the anti-over-current shock ability of device and the consistency of this ability.For this reason, the present invention also provides a kind of manufacture method of super-junction device.
For solving the problems of the technologies described above, the invention provides a kind of super-junction device, be formed with a N-type silicon epitaxy layer at a N+ silicon chip, the zone line of super-junction device is the current flowing district, and described current flowing district comprises P type thin layer and the N-type thin layer in the described N-type silicon epitaxy layer of being formed at of a plurality of alternative arrangements; Described terminal protection structure is surrounded on the periphery in described current flowing district, and described terminal protection structure comprises P type thin layer and the N-type thin layer in the described N-type silicon epitaxy layer of being formed at of a plurality of peripheries that are surrounded on described current flowing district and alternative arrangement; Described terminal protection structure is divided into 2 districts and 3 districts, and described 2 districts and described 3 districts all comprise a plurality of described P type thin layers and described N-type thin layer, and wherein said 2 districts are positioned at inboard and are contiguous with described current flowing district, and described 3 districts are positioned at the outside in described 2 districts.
The width of the described N-type thin layer that the width of all described P type thin layers in described current flowing district is identical, all is also identical.
Two adjacent described P type thin layers and the width ratio between the described N-type thin layer are the thin layer Width, and the thin layer Width everywhere in described current flowing district is all identical; The thin layer Width of at least part of described terminal protection structure is less than the thin layer Width in described current flowing district.
The width of the long-pending and described N-type thin layer of the width of adjacent described P type thin layer and p type impurity concentration and the long-pending ratio of N-type impurity concentration are the total impurities ratio, and the described total impurities everywhere in described current flowing district is more identical than all; Less than or equal to the described total impurities ratio in described current flowing district, and the described total impurities of at least part of described terminal protection structure is than the described total impurities ratio less than described current flowing district than all for the described total impurities everywhere of described terminal protection structure.
In all described P type thin layers, the described N+ silicon chip contact of getting along well of at least one bottom that is arranged in the described P type thin layer of described terminal protection structure.
Further improvement is, the described total impurities ratio of at least part of described terminal protection structure is the first ratio, and this first ratio is 1.0～1.1; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
Further improve and be, the width of two adjacent described P type thin layers and described N-type thin layer and for stepping, stepping in described 3 districts of described terminal protection structure is less than the stepping in described current flowing district, the described total impurities ratio at least part of described 3 districts is the first ratio, and this first ratio is 1.0～1.1; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
Further improve and be, the width of two adjacent described P type thin layers and described N-type thin layer and for stepping, the stepping in described 3 districts of described terminal protection structure is less than the stepping of the stepping that has the adjacent described P type thin layer of part and described N-type thin layer in the stepping in described current flowing district, described 2 districts at least less than described current flowing district; The described total impurities ratio at least part of described 3 districts is the first ratio, and this first ratio is 1.0～1.1, and the described total impurities ratio at least part of described 2 districts is the 3rd ratio, and described the 3rd ratio is less than or equal to 1.05 times of described the first ratio; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
Further improve and be, in described current flowing district, one P type back of the body grid are formed at each described P type thin layer top or described P type back of the body grid and are formed at each described P type thin layer top and extend in the described N-type thin layer of each both sides, described P type thin layer top, one source region is formed in each described P type back of the body grid, described N-type silicon epitaxy layer top in described current flowing district is formed with grid oxygen, grid and source electrode, is formed with drain electrode at the back side of described N+ silicon chip.
Described terminal protection structure also comprises at least one P type ring, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate; Described P type ring, described P type thin layer and described channel cutoff ring be structure and by the interior periphery that is surrounded on successively outward described current flowing district in the form of a ring all.
Described P type annular is formed in the superficial layer of described N-type silicon epitaxy layer in described terminal protection structure zone and is adjacent with described outermost p type island region territory; Described P type ring is covered in the described P type thin layer in described 2 districts and the top of described N-type thin layer.
Described channel cutoff annular is formed in the superficial layer of the described N-type silicon epitaxy layer outside the outermost P type thin layer.
Described terminal deielectric-coating be formed on the described N-type silicon epitaxy layer in described terminal protection structure zone and and the outer ledge in described current flowing district separated by a distance, a side in the close described current flowing district of described terminal deielectric-coating has a ledge structure.
The outer ledge that described polysilicon field plate covers the described terminal deielectric-coating of described ledge structure and cover part fully and extends to described current flowing district is to the zone between the described terminal deielectric-coating.
One interlayer film is formed on the described N-type silicon epitaxy layer in described terminal protection structure zone, described terminal deielectric-coating and the described polysilicon field plate.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of super-junction device, comprise the steps:
The width of the long-pending and described N-type thin layer of the width of adjacent described P type thin layer and p type impurity concentration and the long-pending ratio of N-type impurity concentration are the total impurities ratio, and the described total impurities everywhere in described current flowing district is more identical than all; Less than or equal to the described total impurities ratio in described current flowing district, and the described total impurities of at least part of described terminal protection structure is than the described total impurities ratio less than described current flowing district than all for the described total impurities everywhere of described terminal protection structure.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in described terminal protection structure zone; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure.
Step 5, form grid oxygen and polysilicon at described N+ silicon chip; utilize chemical wet etching to form the gate patterns that is formed by described polysilicon in described current flowing district; form at least one polysilicon field plate in described terminal protection structure zone, the outer ledge that described polysilicon field plate covers the described terminal deielectric-coating of described ledge structure and cover part fully and extends to described current flowing district is to the zone between the described terminal deielectric-coating.
Further improvement is, comprises at least the described groove of two kinds of different in width in the described step 2, and the degree of depth that the described groove of different in width is corresponding is also different.More preferably be selected as, described groove comprises that width is 5 microns～6 microns value and 2 microns～3 microns value; After the etching, the degree of depth of the described groove of 5 microns～6 microns value is that the degree of depth of described groove of 32 microns～37 microns, 2 microns～3 microns value is 15 microns～28 microns.
Super-junction device of the present invention is the optimum balance of P type thin layer and N-type thin layer by making terminal protection structure keep the P/N thin layer, makes the puncture voltage of device terminal be higher than the reverse breakdown voltage of device cell.And be the current flowing district at cellular zone, guarantee in the P/N thin layer P type doping total amount more than the N-type total amount of mixing, thereby can improve the power of resisting voltaic impingement of device and the consistency of this ability.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the vertical view of the terminal protection structure of embodiment of the invention super-junction device;
Fig. 2-Fig. 4 is the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention one to three super-junction device.
Embodiment
As shown in Figure 1, be the vertical view of embodiment of the invention super-junction device.On vertical view, the embodiment of the invention can be divided into 1 district, 2 districts and 3 districts.1 district is the current flowing district for the zone line of super-junction device, described current flowing district comprises p type island region territory 25 and the N-type zone in the described N-type silicon epitaxy layer 2 of being formed at of alternative arrangement, and described p type island region territory 25 also namely is formed at the P type thin layer in the described current flowing district, described N-type zone also namely is formed at the N-type thin layer in the described current flowing district; Can arrive drain electrode by source electrode through raceway groove by the N-type zone at described current flowing district electric current, and described p type island region territory 25 is to form depletion region with described N-type zone to bear voltage under reverse blocking state.2 districts and 3 districts are the terminal protection structure zone of described super-junction device; described terminal protection structure does not provide electric current when break-over of device, and being used for bearing from periphery unit, 1 district at reverse blocking state is that the surface in periphery p type island region territory 25 is that lateral voltage and this voltage of voltage from 1 district's periphery cell surface to substrate are longitudinal voliage to this voltage of voltage of device outer-most end surface substrate.At least one P type ring 24 is arranged in 2 districts, is a P type ring 24 among Fig. 1, and these P type ring 24 general P type back of the body grid with 1 district link together; In 2 districts, also have be used to slowing down surface field polycrystalline field plate jumpy sheet P1 and Metal field plate P2, and P type post 23; Also described Metal field plate P2 can be set in 2 districts.3 districts bear the district by P type post 23 and the voltage that the N-type post that is comprised of the N-type silicon epitaxy layer alternately forms, and described P type post 23 also namely is formed at the P type thin layer in the described terminal protection structure, described N-type post also namely is formed at the N-type thin layer in the described terminal protection structure; Metal field plate P2 is arranged in 3 districts, also described Metal field plate P2 can be set in 3 districts; Can have P type ring 24 also can not have in 3 districts, the P type ring at this place was not to be connected (suspension) that links to each other with the P type back of the body grid in current flowing district when P type ring 24 was arranged; Outermost end in 3 districts has channel cutoff ring 21, and described channel cutoff ring 21 adds medium formed thereon by N+ injection region or N+ injection region again or medium adds that metal consists of; At place, four angles additional little P type post 22 can be arranged at described P type post 23, in order to better realization charge balance.As seen from Figure 1, the cellular construction in described current flowing district is that described p type island region territory 25 and N-type zone all are tetragonal structure, namely is made of the cell array in described current flowing district tetragonal described p type island region territory 25 and N-type zone proper alignment on two-dimensional directional.Periphery and described P type ring 24, described P type post 23 and described channel cutoff ring 21 that described terminal protection structure is surrounded on described current flowing district all are tetragonal circulus, also can be tetragonal four jiaos of circuluses that circular arc is arranged.
Described p type island region territory 25 and N-type zone also can be hexagon, octagon and other shape, and the arrangement mode in described p type island region territory 25 and N-type zone also can be at X, and Y-direction is carried out certain dislocation; As long as guarantee that whole arrangement is by certain rule, repeat just passable.Described p type island region territory 25 and N-type zone also can be strip structure, are arranged in one-dimensional square upwards.
Four jiaos additional little P type post 22 among Fig. 1, can design according to the optimized requirement of local charge balance, if the width of described P type post 23 is a, distance between described P type post 23 and the described P type post 23 also is a, and it is the square P type hole of 0.3～0.5a that so described little P type post 22 can adopt the length of side.
As shown in Figure 2, be the sectional view along AA ' among Fig. 1 of the embodiment of the invention one super-junction device.Be formed with a N-type silicon epitaxy layer 2 at a N+ silicon chip 1,1 district is the current flowing district for the zone line of the embodiment of the invention one super-junction device, described current flowing district comprises p type island region territory 25 and the N-type zone in the described N-type silicon epitaxy layer 2 of being formed at of alternative arrangement, and described p type island region territory 25 is the P type post 51 that is formed among Fig. 3 in the groove 41; One P type back of the body grid 3 are formed at each 25 top, described p type island region territory or described P type back of the body grid 3 and are formed at each 25 top, described p type island region territory and extend in the described N-type zone of each both sides, 25 top, described p type island region territory; One source region 11 is formed in each described P type back of the body grid 3, and described source region 11 is comprised of the N+ injection region; Be formed with on described N-type silicon epitaxy layer 2 tops in described current flowing district that grid oxygen 7, grid are namely drawn by polysilicon gate 8 and source electrode is namely drawn by source region 11, metal level 13 is drawn described grid or source electrode by contact hole 10 and described polysilicon gate 8 or described source region 11, and P+ ion implanted region 12 forms ohmic contact between described P type back of the body grid 3 and subsequent metal layer; Be formed with metal layer on back 14 at the back side of described N+ silicon chip 1 and draw drain electrode.
2 districts and 3 districts are the terminal protection structure zone of the embodiment of the invention one super-junction device.The terminal protection structure of the embodiment of the invention one super-junction device is around in the periphery in described current flowing district and comprises at least one P type ring 24, a plurality of P type post 23, one channel cutoff rings 21, one terminal deielectric-coating 6, at least one polysilicon field plate P1 and Metal field plate P2; Also described Metal field plate P2 can be set in 2 districts and 3 districts, be provided with 2 described Metal field plate P2 in the embodiment of the invention one.
Described P type post 23 is that the inboard P type post 23 in P type post 52,3 districts that is formed in the groove 42 is the P type post 54 that is formed in the groove 44 for the P type post 23 that is formed at the outside, P type post 53,3 districts in the groove 43 in 2 districts.The bottom of described P type post 51, P type post 52, P type post 53 and P type post 54 does not penetrate described N-type silicon epitaxy layer 2, its described N+ silicon chip 1 of all getting along well contacts.Described P type post 51, P type post 52, P type post 53 and P type post 54 all are comprised of the P type silicon that is filled in the groove.
Each described P type post 52,53,54 is arranged in order in 21 on the outermost p type island region territory 25 in described current flowing district and described channel cutoff ring, and the N-type silicon epitaxy layer that each described P type post 23 and each described P type post are 23 forms P type post and N-type post alternative expression structure also is P type thin layer and N-type interlaminate formula structure.
The width W that all described P type thin layers in described current flowing district are described P type post 51
P-1Identical and be 5.3 microns, the width W of all described N-type thin layers
N-2Also identical and be 7.7 microns.All described P type thin layers of described terminal protection structure are the width W of described P type post 52,53 and 54
P-2, W
P-3Identical and be 5 microns, the width W of all described N-type thin layers
N-2, W
N-3Also identical and be 8 microns.Two adjacent described P type thin layers and the width ratio between the described N-type thin layer are the thin layer Width, and as from the foregoing, the thin layer Width everywhere in described current flowing district all is 5.3: 7.7; The thin layer Width everywhere of described terminal protection structure all is 5: 8, all less than the thin layer Width in described current flowing district.The width of two adjacent described P type thin layers and described N-type thin layer and for stepping, as from the foregoing, the stepping everywhere in described current flowing district equals the stepping everywhere of described terminal protection structure, namely all is 13 microns.
The width of the long-pending and described N-type thin layer of the width of adjacent described P type thin layer and p type impurity concentration and the long-pending ratio of N-type impurity concentration are the total impurities ratio, and the described total impurities everywhere in described current flowing district is more identical than all; Less than or equal to the described total impurities ratio in described current flowing district, and the described total impurities of at least part of described terminal protection structure is than the described total impurities ratio less than described current flowing district than all for the described total impurities everywhere of described terminal protection structure.When the described total impurities everywhere of described terminal protection structure when reaching best charge balance; the described total impurities ratio everywhere in described current flowing district is 1.1: 1; namely in the current flowing district; described P type thin layer is that the N-type total impurities of the described N-type thin layer that the p type impurity total amount in the described P type post 51 will be adjacent with it is many, the power of resisting voltaic impingement when so just being conducive to improve device and turn-offing in perceptual load circuit.
Described P type ring 24 is formed in the superficial layer of the described N-type silicon epitaxy layer 2 in 2 districts in described terminal protection structure zone and is adjacent with described outermost p type island region territory 25.Described P type ring 24 is coated with a plurality of described P type posts 52.The doping content of described P type ring 24 is greater than the doping content of described P type post 52.Described P type ring 24 outermost p type island region territory 25 from described current flowing district covers at least one described P type post 52 and an adjacent described N-type post outward.The impurity process conditions of the impurity process conditions of described P type ring 24 and described P type back of the body grid 3 are identical to be that described P type ring 24 and described P type back of the body grid 3 are to inject simultaneously formation, and described P type ring 24 also can adopt once to inject separately and form.
Described channel cutoff ring 21 is formed in the superficial layer of described N-type silicon epitaxy layer 2 in outermost P type post 54 outsides.
Described terminal deielectric-coating 6 is formed on the described N-type silicon epitaxy layer 2 in described terminal protection structure zone; one side in the close described current flowing district of described terminal deielectric-coating 6 has a ledge structure, and described terminal deielectric-coating 6 has covered the P type post of described ledge structure bottom to all described P type posts 23 of described outermost P type intercolumniation.The inclination angle of described ledge structure is 10 degree～75 degree.
Described polysilicon field plate P1 is formed on the described terminal deielectric-coating 6, and described polysilicon field plate P1 covers the described terminal deielectric-coating 6 of described ledge structure and cover part fully.The outside that described polysilicon field plate P1 also extends to described current flowing district to the described N-type silicon epitaxy layer 2 between described ledge structure and the extension of described polysilicon field plate P1 be coated with one or more described P type posts 23,2 isolation of described N-type silicon epitaxy layer of the extension of described polysilicon field plate P1 and its bottom have grid oxygen 7 and second medium layer 7A, and the thickness of described second medium layer 7A is greater than the thickness of described grid oxygen 7.Described second medium floor 7A covered each the described P type post 52 that is arranged in 2 districts.Described polysilicon field plate P1 is connected with described polysilicon gate 8.
One interlayer film 9 is formed on the described N-type silicon epitaxy layer 2 in described terminal protection structure zone, described terminal deielectric-coating 6 and the described polysilicon field plate P1, also is formed with described interlayer film 9 in 1 district and is isolated from described current flowing district and metal interlevel.In 2 districts and 3 districts, there are 2 to be formed on the described interlayer film 9 in this enforcement of a plurality of Metal field plate P2 one, described Metal field plate P2 is formed by metal level 13 chemical wet etchings, each described Metal field plate P2 lays respectively on the described P type ring 24 or on the described interlayer film 6 on described P type post 53,54 or the described channel isolation ring 21, and it is that described Metal field plate P2 in the T1 frame is covered on the described ledge structure fully that one of them described Metal field plate P2 is covered on the described ledge structure fully.A be separated by segment distance and not connecting of described Metal field plate P2 in the T1 frame and source electrode, the part of the described Metal field plate P2 in the T1 frame has covered described P type ring 24 fully.Described polysilicon field plate P1 be located thereon described Metal field plate P2 and do not link to each other, also can link to each other by a contact hole 10 between the two.
Outermost end in 3 districts has described channel cutoff ring 21, described channel cutoff ring 21 adds metal formed thereon by N+ injection region or N+ injection region again and consists of, and the N+ injection region of the ring of channel cutoff described in the embodiment of the invention 21 is identical with the formation technique in described source region 11; Be formed with Metal field plate P2, also connect by contact hole 10 and the Metal field plate P2 of being connected at channel cutoff ring 21 described in the embodiment of the invention one; Thereby described channel cutoff ring 21 also can with it on described Metal field plate P2 do not connect this Metal field plate P2 suspended, this Metal field plate P2 also can arrange polysilicon field plate P1, and polysilicon field plate P1 is not set in the embodiment of the invention one.
As shown in Figure 3, be the sectional view along AA ' among Fig. 1 of the embodiment of the invention two super-junction devices.The difference of the embodiment of the invention two and embodiment one is:
The width W that all described P type thin layers in described current flowing district are described P type post 51
P-1Identical and be 5.3 microns, the width W of all described N-type thin layers
N-2Also identical and be 7.7 microns.The width W that described P type thin layer in described 2 districts of described terminal protection structure is described P type post 52
P-2Identical and be 5 microns, the width W of the described N-type thin layer in described 2 districts
N-2Also identical and be 8 microns.Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4 microns.As from the foregoing, the thin layer Width everywhere in described current flowing district all is 5.3: 7.7; The thin layer Width everywhere of described terminal protection structure all is 5: 8, all less than the thin layer Width in described current flowing district.The width of two adjacent described P type thin layers and described N-type thin layer and for stepping, as from the foregoing, the stepping everywhere in described current flowing district all is 13 microns; Stepping in 3 districts of described terminal protection structure is 6.5 microns, is less than the stepping everywhere in described current flowing district.
When the described total impurities everywhere of described terminal protection structure when reaching best charge balance; the described total impurities ratio everywhere in described current flowing district is 1.1: 1; namely in the current flowing district; described P type thin layer is that the N-type total impurities of the described N-type thin layer that the p type impurity total amount in the described P type post 51 will be adjacent with it is many, the power of resisting voltaic impingement when so just being conducive to improve device and turn-offing in perceptual load circuit.Because the micro loading effect of etching, when gash depth was 36 microns in described current flowing district, gash depth was 26 microns in 3 districts, and is less than 36 microns gash depth in 2 districts, 3 districts form a gradual P/N knot with 2 districts in the device terminal, improve the reverse breakdown voltage of device terminal.
As shown in Figure 3, be the sectional view along AA ' among Fig. 1 of the embodiment of the invention three super-junction devices.The difference of the embodiment of the invention three and embodiment one is:
The width W that all described P type thin layers in described current flowing district are described P type post 51
P-1Identical and be 5 microns, the width W of all described N-type thin layers
N-2Also identical and be 8 microns.The width W that described P type thin layer in described 2 districts of described terminal protection structure is described P type post 52
P-2Identical and be 5 microns, the width W of the described N-type thin layer in described 2 districts
N-2Also identical and be 8 microns.Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4.3 microns.As from the foregoing, the thin layer Width everywhere in described current flowing district all is 5: 8; Thin layer Width everywhere in 2 districts of described terminal protection structure all is 5: 8, all equals the thin layer Width in described current flowing district; Thin layer Width everywhere in 3 districts of described terminal protection structure all is 5: 8.6, all less than the thin layer Width in described current flowing district.The width of two adjacent described P type thin layers and described N-type thin layer and for stepping, as from the foregoing, the stepping everywhere in described current flowing district all is 13 microns; Stepping in 3 districts of described terminal protection structure is 6.8 microns, is less than the stepping everywhere in described current flowing district.
When the described total impurities in described 3 districts of described terminal protection structure when reaching best charge balance; the described total impurities ratio everywhere in described current flowing district is 1.07: 1; namely in the current flowing district; described P type thin layer is that the N-type total impurities of the described N-type thin layer that the p type impurity total amount in the described P type post 51 will be adjacent with it is many, the power of resisting voltaic impingement when so just being conducive to improve device and turn-offing in perceptual load circuit.Because the micro loading effect of etching, when gash depth was 36 microns in described current flowing district, gash depth was 26 microns in 3 districts, and is less than 36 microns gash depth in 2 districts, 3 districts form a gradual P/N knot with 2 districts in the device terminal, improve the reverse breakdown voltage of device terminal.
As shown in Figure 4, be the sectional view along AA ' among Fig. 1 of the embodiment of the invention four super-junction devices.The difference of the embodiment of the invention four and embodiment one is:
The width W that all described P type thin layers in described current flowing district are described P type post 51
P-1Identical and be 5 microns, the width W of all described N-type thin layers
N-2Also identical and be 8 microns.
The width of the described P type thin layer in described 2 districts comprises two kinds, and the inside namely and a width W that described P type thin layer is described P type post 52 of described current flowing district adjacency
P-2Identical and be 5 microns, other described P type thin layer is 2.5 microns.The width of the described N-type thin layer of the correspondence of 5 microns described P type thin layer is 6.15 microns in described 2 districts, and the width of the described N-type thin layer of the correspondence of 2.5 microns described P type thin layer is 4.3 microns.
Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4.3 microns.
As from the foregoing, the thin layer Width everywhere in described current flowing district all is 5: 8; The most inboard thin layer Width in 2 districts of described terminal protection structure all is 5: 6.15, and other thin layer Width all is 5: 8.6; Thin layer Width everywhere in 3 districts of described terminal protection structure all is 5: 8.6, all less than the thin layer Width in described current flowing district.The stepping everywhere in described current flowing district all is 13 microns; Stepping in 2 districts of described terminal protection structure comprises 11.15 microns and 6.5 microns two kinds, is less than the stepping everywhere in described current flowing district; Stepping in 3 districts of described terminal protection structure is 6.5 microns, is less than the stepping everywhere in described current flowing district.
When the described total impurities in described 3 districts of described terminal protection structure when reaching best charge balance; the described total impurities ratio everywhere in described current flowing district is 1.07: 1; namely in the current flowing district; described P type thin layer is that the N-type total impurities of the described N-type thin layer that the p type impurity total amount in the described P type post 51 will be adjacent with it is many, the power of resisting voltaic impingement when so just being conducive to improve device and turn-offing in perceptual load circuit.Because the micro loading effect of etching, when gash depth was 36 microns in described current flowing district, gash depth was 26 microns in 3 districts, and is less than 36 microns gash depth in 2 districts, 3 districts form a gradual P/N knot with 2 districts in the device terminal, improve the reverse breakdown voltage of device terminal.
In above-described embodiment one to three, be the position that joins of described P type thin layer and described N-type thin layer at the P/N of two kinds of different steppings thin layer, if the width of a kind of P type thin layer of P/N thin layer and N-type thin layer is respectively W
P-1And W
N-1, the P type thin layer of another kind of P/N thin layer and the width of N-type thin layer are W
P-2And W
N-2, so the width of the N thin layer between the P thin layer of two neighbour different in width should be (W
N-1+ W
N-2)/2,
For the device such as the various structures of Fig. 2～shown in Figure 4, when the puncture voltage of device was 500V～600V, the thickness of wherein said N-type silicon epitaxy layer 2 was about 45 microns, and the doping content of described N-type silicon epitaxy layer 2 is 1E15CM
-3Thickness 800 dusts of grid oxygen 7～1200 dusts, the thickness of polysilicon 8 are 3000 dusts～0000 dust, and the thickness of described terminal deielectric-coating 6 is 5000 dusts～15000 dusts, and the thickness of described interlayer film 9 is 5000 dusts～15000 dusts.
Such as Fig. 2～shown in Figure 4, the manufacture method of the embodiment of the invention one described super-junction device comprises the steps:
As shown in Figure 2, all described P type thin layers in described current flowing district width W that is described P type post 51
P-1Identical and be 5.3 microns, the width W of all described N-type thin layers
N-2Also identical and be 7.7 microns.All described P type thin layers of described terminal protection structure are the width W of described P type post 52,53 and 54
P-2, W
P-3Identical and be 5 microns, the width W of all described N-type thin layers
N-2, W
N-3Also identical and be 8 microns.When the described total impurities everywhere of described terminal protection structure when reaching best charge balance, the described total impurities ratio everywhere in described current flowing district is 1.1: 1.
As shown in Figure 3, all described P type thin layers in described current flowing district width W that is described P type post 51
P-1Identical and be 5.3 microns, the width W of all described N-type thin layers
N-2Also identical and be 7.7 microns.The width W that described P type thin layer in described 2 districts of described terminal protection structure is described P type post 52
P-2Identical and be 5 microns, the width W of the described N-type thin layer in described 2 districts
N-2Also identical and be 8 microns.Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4 microns.When the described total impurities everywhere of described terminal protection structure when reaching best charge balance, the described total impurities ratio everywhere in described current flowing district is 1.1: 1.
As shown in Figure 3, the P/N thin layer also can be width W that all described P type thin layers in described current flowing district are described P type post 51
P-1Identical and be 5 microns, the width W of all described N-type thin layers
N-2Also identical and be 8 microns.The width W that described P type thin layer in described 2 districts of described terminal protection structure is described P type post 52
P-2Identical and be 5 microns, the width W of the described N-type thin layer in described 2 districts
N-2Also identical and be 8 microns.Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4.3 microns.When the described total impurities in described 3 districts of described terminal protection structure when reaching best charge balance, the described total impurities ratio everywhere in described current flowing district is 1.07: 1.
As shown in Figure 4, all described P type thin layers in described current flowing district width W that is described P type post 51
P-1Identical and be 5 microns, the width W of all described N-type thin layers
N-2Also identical and be 8 microns.The width of the described P type thin layer in described 2 districts comprises two kinds, and the inside namely and a width W that described P type thin layer is described P type post 52 of described current flowing district adjacency
P-2Identical and be 5 microns, other described P type thin layer is 2.5 microns.The width of the described N-type thin layer of the correspondence of 5 microns described P type thin layer is 6.15 microns in described 2 districts, and the width of the described N-type thin layer of the correspondence of 2.5 microns described P type thin layer is 4.3 microns.Described P type thin layer in described 3 districts of described terminal protection structure is the width W of described P type post 53 and 54
P-3Identical and be 2.5 microns, the width W of the described N-type thin layer in described 3 districts
N-3Also identical and be 4.3 microns.When the described total impurities in described 3 districts of described terminal protection structure when reaching best charge balance, the described total impurities ratio everywhere in described current flowing district is 1.07: 1.
Step 4, deposition dielectric film also utilize chemical wet etching that thereby the film in 1 district is removed at described terminal protection structure zone formation terminal deielectric-coating 6; One side in the close described current flowing district of described terminal deielectric-coating 6 has a ledge structure.
Step 5, form grid oxygen 7 and polysilicon 8 at described N+ silicon chip 1; utilize chemical wet etching to form the gate patterns that is formed by described polysilicon 8 in described current flowing district; form at least one polysilicon field plate P1 in described terminal protection structure zone, the outer ledge that described polysilicon field plate P1 covers the described terminal deielectric-coating 6 of described ledge structure and cover part fully and extends to described current flowing district is to the zone between the described terminal deielectric-coating 6.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. a super-junction device is formed with a N-type silicon epitaxy layer at a N+ silicon chip, and the zone line of super-junction device is the current flowing district, and described current flowing district comprises P type thin layer and the N-type thin layer in the described N-type silicon epitaxy layer of being formed at of a plurality of alternative arrangements; Described terminal protection structure is surrounded on the periphery in described current flowing district, and described terminal protection structure comprises P type thin layer and the N-type thin layer in the described N-type silicon epitaxy layer of being formed at of a plurality of peripheries that are surrounded on described current flowing district and alternative arrangement; Described terminal protection structure is divided into 2 districts and 3 districts, and described 2 districts and described 3 districts all comprise a plurality of described P type thin layers and described N-type thin layer, and wherein said 2 districts are positioned at inboard and are contiguous with described current flowing district, and described 3 districts are positioned at the outside in described 2 districts;
It is characterized in that: the width of the described N-type thin layer that the width of all described P type thin layers in described current flowing district is identical, all is also identical;
Two adjacent described P type thin layers and the width ratio between the described N-type thin layer are the thin layer Width, and the thin layer Width everywhere in described current flowing district is all identical; The thin layer Width of at least part of described terminal protection structure is less than the thin layer Width in described current flowing district;
The width of the long-pending and described N-type thin layer of the width of adjacent described P type thin layer and p type impurity concentration and the long-pending ratio of N-type impurity concentration are the total impurities ratio, and the described total impurities everywhere in described current flowing district is more identical than all; Less than or equal to the described total impurities ratio in described current flowing district, and the described total impurities of at least part of described terminal protection structure is than the described total impurities ratio less than described current flowing district than all for the described total impurities everywhere of described terminal protection structure;
In all described P type thin layers, the described N+ silicon chip contact of getting along well of at least one bottom that is arranged in the described P type thin layer of described terminal protection structure.
2. super-junction device as claimed in claim 1, it is characterized in that: the described total impurities ratio of at least part of described terminal protection structure is the first ratio, and this first ratio is 1.0～1.1; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
3. super-junction device as claimed in claim 1, it is characterized in that: the width of two adjacent described P type thin layers and described N-type thin layer and for stepping, stepping in described 3 districts of described terminal protection structure is less than the stepping in described current flowing district, the described total impurities ratio at least part of described 3 districts is the first ratio, and this first ratio is 1.0～1.1; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
4. super-junction device as claimed in claim 1, it is characterized in that: the width of two adjacent described P type thin layers and described N-type thin layer and for stepping, the stepping in described 3 districts of described terminal protection structure is less than the stepping of the stepping that has the adjacent described P type thin layer of part and described N-type thin layer in the stepping in described current flowing district, described 2 districts at least less than described current flowing district; The described total impurities ratio at least part of described 3 districts is the first ratio, and this first ratio is 1.0～1.1, and the described total impurities ratio at least part of described 2 districts is the 3rd ratio, and described the 3rd ratio is less than or equal to 1.05 times of described the first ratio; The described total impurities ratio in described current flowing district is the second ratio, and described the second ratio is greater than 1.05 times of described the first ratio.
5. super-junction device as claimed in claim 1, it is characterized in that: in described current flowing district, one P type back of the body grid are formed at each described P type thin layer top or described P type back of the body grid and are formed at each described P type thin layer top and extend in the described N-type thin layer of each both sides, described P type thin layer top, one source region is formed in each described P type back of the body grid, described N-type silicon epitaxy layer top in described current flowing district is formed with grid oxygen, grid and source electrode, is formed with drain electrode at the back side of described N+ silicon chip;
Described terminal protection structure also comprises at least one P type ring, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate; Described P type ring, described P type thin layer and described channel cutoff ring be structure and by the interior periphery that is surrounded on successively outward described current flowing district in the form of a ring all;
Described P type annular is formed in the superficial layer of described N-type silicon epitaxy layer in described terminal protection structure zone and is adjacent with described outermost p type island region territory; Described P type ring is covered in the described P type thin layer in described 2 districts and the top of described N-type thin layer;
Described channel cutoff annular is formed in the superficial layer of the described N-type silicon epitaxy layer outside the outermost P type thin layer;
Described terminal deielectric-coating be formed on the described N-type silicon epitaxy layer in described terminal protection structure zone and and the outer ledge in described current flowing district separated by a distance, a side in the close described current flowing district of described terminal deielectric-coating has a ledge structure;
The outer ledge that described polysilicon field plate covers the described terminal deielectric-coating of described ledge structure and cover part fully and extends to described current flowing district is to the zone between the described terminal deielectric-coating;
One interlayer film is formed on the described N-type silicon epitaxy layer in described terminal protection structure zone, described terminal deielectric-coating and the described polysilicon field plate.
6. the manufacture method of a super-junction device is characterized in that, comprises the steps:
Step 1, form the N-type silicon epitaxy layer at a N+ silicon chip, form the P type back of the body grid in current flowing district and the P type ring in terminal protection structure zone at described N-type silicon epitaxy layer;
Step 2, utilize chemical wet etching to form groove at the described N-type silicon epitaxy layer in described current flowing district and described terminal protection structure zone; The width of the P type thin layer of the width of described groove and follow-up formation is identical, and the spacing between the adjacent described groove is identical with the N-type thin layer of follow-up formation; In all described grooves, the described N+ silicon chip contact of getting along well of at least one bottom that is arranged in the described groove of described terminal protection structure;
Step 3, in described groove, form P type silicon and the silicon on described N-type silicon epitaxy layer surface is removed, thereby form respectively described P type thin layer and the described N-type thin layer of alternative arrangement in described current flowing district and described terminal protection structure zone; The width of the described N-type thin layer that the width of all described P type thin layers in described current flowing district is identical, all is also identical; Two adjacent described P type thin layers and the width ratio between the described N-type thin layer are the thin layer Width, and the thin layer Width everywhere in described current flowing district is all identical; The thin layer Width of at least part of described terminal protection structure is less than the thin layer Width in described current flowing district;
The width of the long-pending and described N-type thin layer of the width of adjacent described P type thin layer and p type impurity concentration and the long-pending ratio of N-type impurity concentration are the total impurities ratio, and the described total impurities everywhere in described current flowing district is more identical than all; Less than or equal to the described total impurities ratio in described current flowing district, and the described total impurities of at least part of described terminal protection structure is than the described total impurities ratio less than described current flowing district than all for the described total impurities everywhere of described terminal protection structure;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in described terminal protection structure zone; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure;
Step 5, form grid oxygen and polysilicon at described N+ silicon chip, utilize chemical wet etching to form the gate patterns that is formed by described polysilicon in described current flowing district, form at least one polysilicon field plate in described terminal protection structure zone, the outer ledge that described polysilicon field plate covers the described terminal deielectric-coating of described ledge structure and cover part fully and extends to described current flowing district is to the zone between the described terminal deielectric-coating;
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Step 7, deposit form interlayer film;
Step 8, carry out chemical wet etching and form contact hole;
Step 9, the ohmic contact that the P+ Implantation forms described P type back of the body grid and subsequent metal layer of carrying out;
Step 10, at described N+ silicon chip surface deposition metal level, and carry out the electrode pattern that chemical wet etching forms described source electrode and described grid;
Step 11, described N+ silicon chip is carried out thinning back side;
Step 12, metallizing at the described N+ silicon chip back side forms drain electrode.
7. the manufacture method of super-junction device as claimed in claim 6 is characterized in that: comprise at least the described groove of two kinds of different in width in the described step 2, the degree of depth that the described groove of different in width is corresponding is also different.
8. the manufacture method of super-junction device as claimed in claim 7, it is characterized in that: described groove comprises that width is 5 microns～6 microns value and 2 microns～3 microns value; After the etching, the degree of depth of the described groove of 5 microns～6 microns value is that the degree of depth of described groove of 32 microns～37 microns, 2 microns～3 microns value is 15 microns～28 microns.
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