CN105633128B - Semiconductor devices with super-junction structures design - Google Patents
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- CN105633128B CN105633128B CN201610098672.XA CN201610098672A CN105633128B CN 105633128 B CN105633128 B CN 105633128B CN 201610098672 A CN201610098672 A CN 201610098672A CN 105633128 B CN105633128 B CN 105633128B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The present invention relates to a kind of semiconductor devices with super-junction structures design applied in power semiconductor field effect transistor device, multiple first columns of the second conduction type formed in the epitaxial layer of an active area of semiconductor devices, multiple second columns of the second conduction type formed in the epitaxial layer of a termination environment of semiconductor devices, transition region between active area and termination environment, configuration is alternateed to which nationality is by the charge balance of their opposite conduction types realization active areas by multiple first columns and multiple third columns, multiple second columns and multiple third columns alternate configuration to which nationality is by the charge balance of their opposite conduction types realization termination environments.
Description
Technical field
Present invention is primarily about field of semiconductor devices, more precisely, being to be related to a kind of apply in power semiconductor
The super-junction structures having in FET device.
Background technique
In power semiconductor field effect transistor devices field, in traditional super-junction structures design, relative to crystal
The cellular of tube device active area designs, and the design of Terminal Design and transition region is a difficult point.General design is in high current
Breakdown or its non-clamped Inductive load switch process UIS easily cause transition region to puncture in advance when occurring, so that
The durability of entire device is lower, or even can not apply in having a little perceptual load circuit.The super junction proposed such as Infineon
Analysis in structure design to puncture place in advance, there is too low breakdown voltage in transition region in discovery, by mistake
The p- column optimization for crossing the active area in area, to realize higher breakdown voltage.In the super of the cell configuration with strip
In grade junction structure design, the problem of equally proposition there is also similar Infineon.There is the end of higher durability in design as a result,
End structure and transition plot structure are the key that obtain high durability super-junction structures design device.
Power metal oxide semiconductor field-effect transistor is typically applied in the device for needing power conversion and power amplification
In part, such as typical power conversion apparatus is exactly double diffusion DMOSFET.The tool usual skill in this field is all known, work is in
Most breakdown voltage BV is by the drift region of device or drift area carrier in the device posed, if attempting to provide higher
Breakdown voltage BV, drift region usually requires the drift region that concentration is lightly doped, however is lightly doped and can also generate thereupon to compare
High conduction resistance value RDSON.Conventional transistor its RDSON and BV2.5It is substantially directly proportional.Therefore for traditional transistor,
As the increase RDSON of breakdown voltage BV is also significantly increased.
Based on the bottleneck that industry faces, super junction transistor structure is widely used on semiconductor devices, such as 1988
The US4754310 United States Patent (USP) of the DJ.COE application of year PHILIPS Co. and the Chen Xing assist in education of University of Electronic Science and Technology in 1993
Award the applied United States Patent (USP) of J.TIHANYI of applied US91101845 United States Patent (USP) and nineteen ninety-five Siemens Company
US5438215 etc..Super junction transistor advantage is that very high off-state breakdown voltage BV can maintained by proposing one kind
While, the method for the very low conducting resistance RDSON of acquisition.Super-junction device contains the alternate p-type being formed in drift region
With n-type doping column.In the off-state of MOSFET element, actually with respect under very low voltage conditions, alternately stand
Column can be completely depleted, so as to maintain very high breakdown voltage, leads to entire p-type and N because of column having lateral depletion
Type column exhausts.It is directly proportional to breakdown voltage BV for the increase of its conducting resistance of super junction transistor RDSON, than traditional half
Conductor structure increases slower.Therefore for identical high-breakdown-voltage BV, super-junction device is than traditional MOSFET device
Part has lower RDSON, and in other words for specified RDSON value, super-junction device has higher than traditional MOSFET
BV。
Each area charge in super-junction device including turning and termination environment requires to balance.Although in active area
P column may be at uniform horizontal ranks in center portion point, easily reach charge balance in this way.However at edge and turning
Place, be but difficult obtain charge balance, thus cause the breakdown voltage BV in these regions lower, and the durability of device compared with
Difference.Various embodiments of the present invention are exactly proposed under the premise of this.
Summary of the invention
It is a in one embodiment of the invention, disclose a kind of semiconductor devices with super-junction structures design, packet
It includes: the substrate of first conduction type and the epitaxial layer of second conduction type positioned at the substrate；In semiconductor
Multiple first columns of the second conduction type formed in the epitaxial layer of one active area of device；At one of semiconductor devices
Multiple second columns of the second conduction type formed in the epitaxial layer of termination environment；One between active area and termination environment
Transition region；It is wherein outer between adjacent second column in the epitaxial layer in active area between adjacent first column and termination environment
Prolong the third column that layer is defined as the first conduction type；Nationality is alternateed by multiple first columns and multiple thirds to which nationality is by it
Opposite conduction type realize the charge balance of active area, nationality is by multiple second columns (P column) and multiple third column (P
Column) alternate the charge balance for realizing termination environment by their opposite conduction types to nationality.
The above-mentioned semiconductor devices with super-junction structures design, the width of the first column are greater than the width of the second column
Degree.
That states has the semiconductor devices of super-junction structures design, and the spacing in active area between adjacent first column is L,
Spacing in termination environment between adjacent second column is L1, wherein in active area in first column of closest transition region
The heart the distance between center of one the second column of closest transition region into termination environment is equal to: 1/2 × L+1/2 × L1.
That states has the semiconductor devices of super-junction structures design, first column of closest transition region in active area
Width be that not to be directly adjacent to the width of other remaining first columns of transition region in S1 and active area be S0, wherein S1
Less than S0.
The semiconductor devices with super-junction structures design stated, wherein limiting the value of (S0-S1) ÷ S0 in 2%-20%
Within the scope of.
That states has the semiconductor devices of super-junction structures design, second column of closest transition region in termination environment
Width be that not to be directly adjacent to the width of other remaining second columns of transition region in T1 and termination environment be T0, wherein T1
Less than T0.
The semiconductor devices with super-junction structures design stated, wherein limiting the value of (T0-T1) ÷ T0 in 2%-20%
Within the scope of.
That states has the semiconductor devices of super-junction structures design, and the spacing in active area between adjacent first column is L,
Spacing in termination environment between adjacent second column is L1, wherein in active area in first column of closest transition region
The heart the distance between center of one the second column of closest transition region into termination environment is equal to: 1/2 × L+1/2 × L2,
Middle L2 is greater than L1.
The depth bounds of the semiconductor devices with super-junction structures design stated, the first column and the second column are in 5um-
Within 80um.
The doping concentration of the semiconductor devices with super-junction structures design stated, the first column and the second column is identical.
Detailed description of the invention
Read it is described further below and referring to the following drawings after, feature and advantage of the invention will be evident:
Fig. 1 is the basic framework of super-junction structures design.
Fig. 2 is the distribution schematic diagram of transition region and active area and termination environment electric field.
Fig. 3 is the schematic diagram of the alternative embodiment of the reduction active area P column of super-junction structures design.
Fig. 4 is the schematic diagram of the embodiment of the increase transition region N column width of super-junction structures design.
Fig. 5 is the schematic diagram of the alternative embodiment of the reduction termination environment P column of super-junction structures design.
Specific embodiment
Below in conjunction with each embodiment, clear and complete elaboration, but described reality are carried out to technical solution of the present invention
Applying example only is the present invention with the embodiment used in illustrating is described herein and not all embodiment, based on the embodiments such as this, this field
Technical staff scheme obtained belongs to protection scope of the present invention without making creative work.
Referring to Fig. 1, the sectional view of a part of active region of typical super-junction device 100 is illustrated, pays attention to the crystal
Pipe structure is only to be convenient for illustrating the contents of the present invention and being not meant to the present invention and be limited to the specific device architecture.It is super
The active region 201 of junction device 100 be provided with one be formed in it is vertical on such as heavy doping N+ type substrate 102 suitably adulterated
Field-effect transistor structure, such as N-channel type MOSFET element, substrate 102 is mainly as drain region and in its 102 bottom surface of substrate
Be provided with one has the electrode of Ohmic contact as drained with substrate.N-type epitaxial layer or the N-type drift suitably adulterated
Layer/drift layer 104 is located at the top of substrate 102, and the doping concentration of drift layer 104 will be lower than the doping concentration of substrate 102.It is super
Tying Super-Junction structure includes the P-type column Pillar120 and N-type column 122 being arranged alternately, their equal shapes
At among drift layer 104.Being marked in source region 201 has P-type column 120 and then has in transition region 202 and termination environment 203
There is P-type column 121.Interval is implanted into several p-type dopants in drift layer 104, forms multiple P-type columns being separated from each other
120 into drift layer 104, and region of the drift layer 104 between adjacent P-type column 120 or P-type column 121 is then
N-type column 122 is constituted, makes active area 201 that there are multiple P-type columns 120 and multiple N-type columns 122 to alternate
Appearance can be taken by their opposite conduction types then to realize charge balance.Have in transition region 202 and termination environment 203 multiple
P-type column 121 alternates appearance with multiple N-type columns 122 and then realizes that charge is put down by their opposite conduction types
Weighing apparatus.Here so-called transition region 202 refers to the region being transitioned between termination environment 203 from active area 201.
In MOSFET shutdown, electric field is established between vertical 120,121 and N of P column column 122, is caused between them
PN junction reverse bias forms depletion layer, by can the area N of vertical conduction exhaust, realized with this can bear in vertical direction it is very high
Breakdown voltage.Notice that super-junction device 100 further includes one be arranged on each P-type column 120 in active area
P-type body zone 106, and N+ source area 108 and the setting of multiple doping including being located in each P-type body zone 106
Multiple grids 112 above 104 upper surface of drift layer.Because structure cell/cellular unit CELL or transistor unit are to repeat
Existing, exemplary description is carried out with an independent unit cell units now, a grid 112 is correspondingly arranged at two neighboring P-type
The top in the respective a part of region of body zone 106, the grid 112 be additionally arranged at simultaneously drift layer 104 be located at this two it is adjacent
The top in the region between P-type body zone 106, a N+ source area 108 in two P-type body zones 106 inside one
It extends under the one side edge part of the grid 112, a N+ source electrode in two P-type body zones 106 inside another one
Area 108 also extends under relatively another lateral edge portions of grid 112, and grid 112 passes through oxide layer 115 and lower section
Drift layer 104 or body zone 106, source area 108 insulate.Wherein source metal 114 contacts source area 108, and contact hole is worn in figure
Transpassivation layer or oxide layer 115 simultaneously extend downwardly into body zone 106, and constituted in contact hole filled with metal material
Embolism 110, so source metal 114 passes through 110 Ohmic contact of metal plug to source area 108.When apply appropriate voltage extremely
Under conditions of on grid 112, region (namely the N-type between the two neighboring P-type body zone 106 can be located in drift layer 104
The top area of column 122) and source area 108 between construct carrier conducting channel, wherein conducting channel is formed in body zone
The region for being located at the lower section of grid 112 at 106 tops and be between source area 108 and drift layer 104, and and source metal
Electronics in 114 source areas 108 with Ohmic contact then enters the vertical N-type column 122 being depleted by conducting channel
And positive charge is neutralized, to restore the N-type conductive characteristic that N-type column 122 is depleted, since vertical n-type column 122 is in device
Open stage there is relatively low resistivity, thus the more conventional MOSFET of whole conducting resistance of super-junction device 100 will be bright
It is aobvious to reduce.
In the embodiment in figure 1, the smaller structure cell knot of cellular construction is used in the terminal structure of super-junction structures design
The spacing L1 between p-type column 121 in structure, such as termination environment 203 is less than the spacing in active area 201 between p-type column 120
L (L1 < L), pays attention to being specifically defined for spacing PITCH here are as follows: the center line of some p-type column 120 in active area 201
The distance between center line to another adjacent p-type column 120 is L, some p-type column 121 in same termination environment 203
The distance between the center line of center line to another adjacent p-type column 121 is L1.It is also maintained at termination environment 203 and mistake simultaneously
Density/the doping concentration for crossing the P- column injection window in area 202 is consistent with the P- column of active area 201.The p-type column of active area 201
The width S 0 of 120 (p-pillar), in the width T0 of the p-type column 120 (p-pillar) of termination environment 203 (containing transition region 202).
It may be implemented by the design of this super-junction structures, the bigger window of the non-equilibrium charge curve of terminal area BV- and higher breakdown
Voltage, due to smaller structure cell for single terminal area structure cell, single p/n column charge is smaller, therefore electric field is entire whole
In end regions more evenly, peak value electric field is lower.Terminal and transition plot structure can also be optimized: in above-mentioned solution
Special due to transition region situation tends to cause even if possessing preferable Terminal Design but super-junction structures design device
It is very fragile, or even the design requirement of Static Breakdown Voltage is not achieved.The reason for this is that transition region 202 bears higher electric field.It is logical
Emulation discovery is crossed, the p/n charge ratio in this region is readjusted, re-establishes a BV-imbalance song in transition region 202
Line may be implemented so that transition region 202 has higher breakdown voltage than cell region namely active area 201, to avoid punch-through
Premature appearance.Electric field curve 251, the electric field of characterization transition region 202 that complete device then works in characterization termination environment 203 are bent
Line 252 characterizes the public domain surrounded under this three curves of the electric field curve 253 of active area 201.Device often designs work
Make at top curve location (namely at lines top of curve 253), and limit breakdown herein is to be provided with transistor crystalline substance
The active area 201 of born of the same parents, the electric field strength at this are really lower than the breakdown voltage of transition region 202 at this time with termination environment 203, therefore
Transition region 202 is not in puncture in advance, and most of avalanche current will be by being provided with transistor unit cell area with termination environment 203
The active area 201 in domain, to improve the breakdown capability of device.
In the embodiment in figure 1, the spacing between the two neighboring P column 120 of active area 201 is L, is had in active area 201
There is most marginal one there is most marginal one close mistake in the P column 120-1 of transition region 202 and termination environment 203
The P column 121-1 in area 202 is crossed, most marginal P column in most marginal P column 120-1 and termination environment 203 in active area 201
The distance between 121-1 is L.The width of P column 120 is S0 in active area 201, and the width of P column 121 is in termination environment 203
T0, wherein the width of P column 120-1 is S0, and the width of P column 120-1 is T0.Two neighboring P column 121 in termination environment 203
Between spacing be L1, limit L1 < L.
In the fig. 3 embodiment, reducing the width for closing on the p- column 120-1 of 201 structure cell side of active area in transition region 202
Size (is reduced to the width S 1 in Fig. 3 by the width S 0 in Fig. 1).In this way, also achieve the breakdown voltage of transition region 202
BV-imbalance curve is reset.The embodiment of Fig. 3 is vertical in addition to the P of a close transition region 202 in active area 201
The width of column 120-1 is reduced to except S1 by S0, other are almost the same with Fig. 1.
In the fig. 3 embodiment, increasing the size of n- column 122 at adjacent terminal end area 203 in transition region 202, we will
The overall width of n- column 122 is divided into two parts in transition region 202, and first part is proximate to that a part of active area 201,
Its width is 1/2L, and second part is proximate to that a part of termination environment 203, and width is 1/2L1, then transition region
The value of the overall width of n- column 122 is equal to [1/2L+1/2L1] in 202.In the embodiments of figure 3 actively by n- column
It is width 1/2L2 that the width of the second part of 122 close termination environment 20 is increased by 1/2L1, and wherein L2 is greater than L1.So
One, resetting for the breakdown voltage BV-imbalance curve of transition region 202 equally also may be implemented.It is final to realize transition
The higher breakdown voltage in area 202 and termination environment 203, so that the higher durability of device.The embodiment of Fig. 3 is in addition to transition region
The width of a N column 122 in 202 close to termination environment 203 becomes [1/2L+1/ by original [1/2L+1/2L1]
2L2] except, other are almost the same with Fig. 1.
According to content described above, in an alternative embodiment, the width of the p-type column 121 in termination environment 203
It is essentially identical, it is all T0.And the spacing in termination environment 203 between two p-type columns 121 of arbitrary neighborhood is set as all for L1, and it is whole
The quantity of p-type column 121 is for 5 or more in petiolarea 203.P-type in p-type column 121 and active area 201 in termination environment 203
The wide association of column 120 is embodied in: the width T0 of terminal p-type column 121 is less than the width of p-type column 120 in active area 201
S0, and the spacing L1 in termination environment 203 between two p-type columns 121 of arbitrary neighborhood is less than arbitrary neighborhood two in active area 201
Spacing L between a p-type column 120.The charge density of p-type column 121 in termination environment 203 (p column injects window density W1/L1)
Equal to the charge density of p-type column 120 in active area 201 (p column injects window density W0/L).
According to content described above, in an alternative embodiment, for transition region 202: (having in transition
201 structural transition of source region is to terminal area 203) p column charge density (injecting window density W1/L1 by terminal side p column) is less than has
Source region or termination environment p column charge density (p column injects window density W0/L), difference are 2%-20% range.At this time namely terminal
The width T1 of area P column 121-1 is set as T1 < T0, and (T0-T1)/T0 is in 2%-20% range.The embodiment in Fig. 5
It embodies, other than T1 < T0, other are almost the same with Fig. 1, in other words, are not directly adjacent to the P of transition region 202 in termination environment 203
The width of type column 121 (namely not including other all p-type columns of P column 121-1) is T0, only P column 121-1
Width be set as T1, wherein requiring T1 < T0.
According to content described above, in an alternative embodiment, for transition region 202: (having in transition
Source structure is transitioned into terminal area) p column charge density (by active area side p column inject window density W0 '/L) be less than active area
Or termination environment p column charge density (p column injects window density W0/L), difference are 2%-20% range.That is S1 < S0, so that (S0-
S1 in other words)/S0 is not directly adjacent to the P of transition region 202 in the embodiment of 2%-20% range, such as Fig. 3 in active area 201
The width of type column 120 (namely not including other all p-type columns of P column 120-1) is S0, only P column 120-1
Width be arranged to S1, wherein require S1 be less than S0.
According to content described above, in an alternative embodiment, for transition region 202: (having in transition
Source structure is transitioned into terminal area) (increase by terminal side n column width degree k1 is k2, value added 2%- to p column charge density
20% range, such as the embodiment of Fig. 4.
According to content described above, in an alternative embodiment, p- column column 120 or 121 structures can pass through
Repeatedly injection and multilayer epitaxial are formed, or are formed using deep etching and the filling of p-type extension.And p- column column 120 or 121
Junction depth range 5um-80um.
More than, by description and accompanying drawings, give the exemplary embodiments of the specific structure of specific embodiment, foregoing invention
Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading
State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention
True intention and range whole variations and modifications.In Claims scope the range of any and all equivalences with it is interior
Hold, is all considered as still belonging to the intent and scope of the invention.
Claims (4)
1. a kind of semiconductor devices with super-junction structures design characterized by comprising
The substrate of one the first conduction type and the epitaxial layer of first conduction type positioned at the substrate；
Multiple first columns of the second conduction type formed in the epitaxial layer of an active area of semiconductor devices；
Multiple second columns of the second conduction type formed in the epitaxial layer of a termination environment of semiconductor devices；
One transition region between active area and termination environment；
The wherein extension in the epitaxial layer in active area between adjacent first column and termination environment between adjacent second column
Layer is defined as the third column of the first conduction type；
Multiple first columns and multiple third columns alternate configuration to which nationality is active by their opposite conduction types realizations
The charge balance in area, multiple second columns and multiple third columns alternate configuration to which nationality is by their opposite conduction types
Realize the charge balance of termination environment；
The width of first column of closest transition region is not to be directly adjacent to transition region in S1 and active area in active area
Other remaining first columns width be S0, wherein S1 be less than S0；
The value of (S0-S1) ÷ S0 is wherein limited within the scope of 2%-20%；
The depth bounds of first column and the second column are within 5um-80um.
2. a kind of semiconductor devices with super-junction structures design according to claim 1, which is characterized in that first is vertical
The width of column is greater than the width of the second column.
3. a kind of semiconductor devices with super-junction structures design according to claim 1, which is characterized in that active area
In spacing between adjacent first column be L, the spacing in termination environment between adjacent second column is L1, wherein in active area most
The center of one the first column of neighbouring transition region is into termination environment between the center of one the second column of closest transition region
Distance be equal to: 1/2 × L+1/2 × L1.
4. a kind of semiconductor devices with super-junction structures design according to claim 1, which is characterized in that first is vertical
The doping concentration of column and the second column is identical.
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| IT202100022547A1 (en) * | 2021-08-30 | 2023-03-02 | St Microelectronics Srl | OPTO-ELECTRONIC DEVICE FOR DETECTION AND LOCATION OF OBJECTS FOR LIDAR APPLICATIONS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931007A (en) * | 2009-06-18 | 2010-12-29 | 富士电机系统株式会社 | Semiconductor device |
| CN104465768A (en) * | 2013-09-17 | 2015-03-25 | 美格纳半导体有限公司 | Super junction semiconductor device |
| CN103077970B (en) * | 2011-10-26 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Super-junction device and manufacture method thereof |
| CN205564755U (en) * | 2016-02-23 | 2016-09-07 | 中航（重庆）微电子有限公司 | Semiconductor device with super knot structural design |
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| JP2006073740A (en) * | 2004-09-01 | 2006-03-16 | Toshiba Corp | Semiconductor device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101931007A (en) * | 2009-06-18 | 2010-12-29 | 富士电机系统株式会社 | Semiconductor device |
| CN103077970B (en) * | 2011-10-26 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Super-junction device and manufacture method thereof |
| CN104465768A (en) * | 2013-09-17 | 2015-03-25 | 美格纳半导体有限公司 | Super junction semiconductor device |
| CN205564755U (en) * | 2016-02-23 | 2016-09-07 | 中航（重庆）微电子有限公司 | Semiconductor device with super knot structural design |
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| IT202100022547A1 (en) * | 2021-08-30 | 2023-03-02 | St Microelectronics Srl | OPTO-ELECTRONIC DEVICE FOR DETECTION AND LOCATION OF OBJECTS FOR LIDAR APPLICATIONS |
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