CN102738207B

CN102738207B - Super junction device terminal protection structure and manufacturing method thereof

Info

Publication number: CN102738207B
Application number: CN201110086240.4A
Authority: CN
Inventors: 肖胜安
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-04-07
Filing date: 2011-04-07
Publication date: 2014-12-10
Anticipated expiration: 2031-04-07
Also published as: CN102738207A

Abstract

The invention discloses a terminal protection structure of a super junction device. The composite structure of polysilicon field plates and metal field plates is employed, and a group of polysilicon field plates and metal field plates simultaneously cover the step structure of a terminal dielectric film, thus an electric field on the device surface is eased. According to the invention, a P-type ring with a high concentration is kept under a field plate, thus the current processing capability of the application of the device in an inductive circuit is improved. In the terminal protection structure provided by the invention, the depth of a P-type column and a N-type column is lower than the depth of a P-type area and a N-type area in a current flowing area to ensure that the device is turned off when the device is applied in the inductive circuit and that the position where an avalanche breakdown occurs in the terminal protection structure is close to the position of the obverse of a silicon chip when a current overshoot occurs, and to improve the capacity of anti-overshoot current of the device. The invention further discloses the super junction device terminal protection structure and a manufacturing method thereof. According to the invention, the breakdown characteristic, the current processing capability and the reliability of the device is improved without process cost increasement.

Description

The terminal protection structure of super-junction device and manufacture method

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of terminal protection structure of super-junction device; The invention still further relates to a kind of manufacture method of terminal protection structure of super-junction device.

Background technology

Super junction MOSFET adopts new structure of voltage-sustaining layer, utilize P type semiconductor thin layer and the N type semiconductor thin layer of a series of alternative arrangement under low voltage, just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted under cut-off state, realizing electric charge compensates mutually, thereby make P type semiconductor thin layer and N type semiconductor thin layer can realize high puncture voltage under high-dopant concentration, thereby obtain low on-resistance and high-breakdown-voltage, power MOSFET theoretical limit breaks traditions simultaneously.The same with existing DMOS device, a super junction MOSFET is formed by a lot of unit repeated arrangement; Due to the consistency of each unit, between the unit in parallel in the middle of device, surface potential is basically identical, does not conventionally have the problem of voltage breakdown, but unit and the substrate surface electrical potential of outmost turns are variant, particularly working under cut-off state, voltage difference is larger, is easy to puncture; Periphery in the periphery unit of device will increase terminal protection structure, and this technology is very important.

To existing device as high pressure VDMOS, existing diffusing protection loop technique, field plate techniques is as floating barnyard plate technique, resistive field plate technology, equipotential ring technology, field limiting ring technology, knot termination extension technology etc.; But for super-junction device, because the withstand voltage mode of the withstand voltage mode of device cell and traditional VDMOS is very different, the terminal protection structure of corresponding high reliability needs otherwise designed.There have been some about the terminal protection structure of super junction MOSFET, in terminal, also adopted the P type of alternative arrangement and N-type post to add the field plate on it, while needing, added cut-off ring.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of terminal protection structure of super-junction device, can improve voltage endurance, current handling capability and the reliability of device, does not also increase process costs.

For solving the problems of the technologies described above, the invention provides a kind of terminal protection structure of super-junction device, on a N+ silicon chip, be formed with a N-type epitaxial loayer, the zone line of super-junction device is current flowing district, described current flowing district comprises the Yu HeNXing region, p type island region in the described N-type epitaxial loayer of being formed at of alternative arrangement, one P type back of the body grid (P-BODY) are formed at top, territory, p type island region described in each or described P type back of the body grid and are formed at top, territory, p type island region described in each and extend in the described N-type region of both sides, top, territory, p type island region described in each, one source region is formed at described in each in P type back of the body grid, described N-type epitaxial loayer top in described current flowing district is formed with grid oxygen, grid and source electrode, the back side at described N+ silicon chip is formed with drain electrode.The terminal protection structure of described super-junction device is surrounded on the periphery in described current flowing district and comprises at least one P type ring, a plurality of P type post, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate and a plurality of Metal field plate; Described P type ring, described P type post and described channel cutoff ring be structure by the interior periphery that is surrounded on successively outward described current flowing district in the form of a ring all.Described in each, P type cylindricality is formed in P type post in the described N-type epitaxial loayer in described terminal protection structure region and described in each and is arranged in order territory, outermost p type island region and the described channel cutoff interannular in described current flowing district, described in each P type post and described in each N-type epitaxial loayer of P type intercolumniation form P type post and N-type post alternative expression structure.Described P type annular is formed in the superficial layer of described N-type silicon epitaxy layer in described terminal protection structure region and is adjacent with territory, described outermost p type island region.Described channel cutoff annular is formed in the superficial layer of the described N-type epitaxial loayer outside outermost P type post.Described terminal deielectric-coating is formed on the described N-type silicon epitaxy layer in described terminal protection structure region; one side in the close described current flowing district of described terminal deielectric-coating has a ledge structure, and described terminal deielectric-coating has covered the P type post of described ledge structure bottom to all described P type post of described outermost P type intercolumniation.Polysilicon field plate is formed on described terminal deielectric-coating, and described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely.One interlayer film is formed on the described N-type epitaxial loayer in described terminal protection structure region, described terminal deielectric-coating and described polysilicon field plate; Described a plurality of Metal field plate is formed on described interlayer film, and described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely.

Further improve and be, the depth as shallow in territory, p type island region in current flowing district described in the depth ratio of P type post described at least one.

Further improving is that described at least one group, the width of P type post and the width ratio of described N-type post are greater than the width in territory, described p type island region and the width ratio in described N-type region in described current flowing district.

Further improve and be, identical with the width ratio of described N-type post or successively decrease along described current flowing district toward the width of P type post described in described channel cutoff ring direction.

Further improve and be, identical or successively decrease along described current flowing district toward the degree of depth of P type post described in described channel cutoff ring direction.

Further improve and be, described P type ring covers P type post and a described N-type post described at least one outward from territory, described outermost p type island region.

Further improving is that the impurity concentration of described P type ring is greater than the impurity concentration of described P type post.

Further improve is that the impurity process conditions of described P type ring are identical with the impurity process conditions of described P type back of the body grid.

Further improve is that the described Metal field plate being positioned on the described interlayer film on described P type ring has at least the whole coverings of a part or part to cover described P type ring.

Further improving is that the described Metal field plate being positioned on the described interlayer film on described P type ring is connected with described source electrode or is suspended on described interlayer film.

Further improving is that described polysilicon field plate is connected with described grid or is suspended on described terminal deielectric-coating.

Further improve and be, it is connected or connected that described polysilicon field plate and be located thereon and is positioned at the described Metal field plate that described ledge structure outside the described source electrode of getting along well be connected.

Further improve is that the inclination angle of described ledge structure is 10 degree～75 degree.

Further improvement is, is coated with described Metal field plate or described polysilicon field plate on described channel cutoff ring, and the described Metal field plate or the described polysilicon field plate that are covered on described channel cutoff ring are connected or suspend with described channel cutoff ring.

Further improvement is, covers the described polysilicon field plate suspending and be coated with Metal field plate on described channel cutoff ring on described polysilicon field plate, and described Metal field plate is connected or suspends with described polysilicon field plate.

Further improve and be, the circulus that is square or described P type post in the circulus of the above P type post of top plan view is tetragonal four jiaos of structures that have circular arc.

Further improve and be, at the quadrangle of the circulus of described P type post, become to have additional P type post.Described additional P type post is connected or separates with described P type post.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of the first super-junction device provided by the invention comprises the steps:

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, on described N-type silicon epitaxy layer, form the P type back of the body grid in current flowing district and the P type ring in terminal protection structure region.

Step 2, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in described current flowing district and described terminal protection structure region.

Step 3, in described groove, form P type silicon and the silicon of described N-type epi-layer surface removed, thus in described current flowing district, form alternative arrangement Yu HeNXing region, described p type island region, in described terminal protection structure region, form described P type post and the described N-type post of alternative arrangement.

Step 4, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure.

Step 5, on described N+ silicon chip, form grid oxygen and polysilicon; utilize chemical wet etching in described current flowing district, to form the gate patterns being formed by described polysilicon; in described terminal protection structure region, form at least one polysilicon field plate, described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely.

Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.

Step 7, deposit form interlayer film.

Step 8, carry out chemical wet etching and form contact hole.

Step 9, the ohmic contact that P+ Implantation forms described P type back of the body grid and subsequent metal layer of carrying out.

Step 10, at described N+ silicon chip surface deposition metal level, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plates, described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely.

Step 11, described N+ silicon chip is carried out to thinning back side.

Step 12, the formation drain electrode of metallizing at the described N+ silicon chip back side.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of super-junction device comprises the steps: described in the second provided by the invention

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in current flowing district and terminal protection structure region.

Step 2, in described groove, form P type silicon and the silicon of described N-type epi-layer surface removed, thus in described current flowing district, form alternative arrangement Yu HeNXing region, described p type island region, in described terminal protection structure region, form described P type post and the described N-type post of alternative arrangement.

Step 3, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure.

Step 4, the P type back of the body grid that form current flowing district on described N-type silicon epitaxy layer and the P type ring in terminal protection structure region.

Step 7, deposit form interlayer film.

Step 8, carry out chemical wet etching and form contact hole.

Step 11, described N+ silicon chip is carried out to thinning back side.

For solving the problems of the technologies described above, provided by the invention described in the third manufacture method of the terminal protection structure of super-junction device comprise the steps:

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, utilize photoetching and Implantation in terminal protection structure region, to form P type ring.

Step 2, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in current flowing district and terminal protection structure region.

Step 5, the current flowing district on described N-type silicon epitaxy layer form P type back of the body grid.

Step 6, on described N+ silicon chip, form grid oxygen and polysilicon; utilize chemical wet etching in described current flowing district, to form the gate patterns being formed by described polysilicon; in described terminal protection structure region, form at least one polysilicon field plate, described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely.

Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.

Step 8, deposit form interlayer film.

Step 9, carry out chemical wet etching and form contact hole.

Step 10, the ohmic contact that P+ Implantation forms described P type back of the body grid and subsequent metal layer of carrying out.

Step 11, at described N+ silicon chip surface deposition metal level, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plates, described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely.

Step 12, described N+ silicon chip is carried out to thinning back side.

Step 13, the formation drain electrode of metallizing at the described N+ silicon chip back side.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of the 4th kind of described super-junction device provided by the invention comprises the steps:

Step 6, utilize Implantation and push away the current flowing district of trap technique on described N-type silicon epitaxy layer and form P type back of the body grid.

Step 8, deposit form interlayer film.

Step 9, carry out chemical wet etching and form contact hole.

Step 12, described N+ silicon chip is carried out to thinning back side.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of the 5th kind of described super-junction device provided by the invention comprises the steps:

Step 1, on a N+ silicon chip epitaxial growth one deck N-type silicon, by photoetching, in described N-type silicon, define the injection zone of p type impurity and inject p type impurity.

The technique of step 2, repeating step 1 5～7 times; obtain the N-type silicon epitaxy layer being formed by multilayer N-type silicon; the p type impurity that is formed at the same area in each floor N-type silicon forms the territory, p type island region in current flowing district and the P type post in terminal protection structure region, thereby in described current flowing district, forms the Yu HeNXing region, described p type island region of alternative arrangement and described P type post and the described N-type post that forms alternative arrangement in terminal protection structure region.

Step 3, the formation P type back of the body grid that carry out photoetching and the described current flowing district of Implantation on described N-type silicon epitaxy layer and described terminal protection structure region form P type ring.

Step 7, deposit form interlayer film.

Step 8, carry out chemical wet etching and form contact hole.

Step 11, described N+ silicon chip is carried out to thinning back side.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of the 6th kind of described super-junction device provided by the invention comprises the steps:

Step 3, carry out photoetching, Implantation and push away trap in described terminal protection structure region, forming P type ring.

Step 4, carry out photoetching and Implantation at the formation P in described current flowing district type back of the body grid.

Step 5, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure.

Step 8, deposit form interlayer film.

Step 9, carry out chemical wet etching and form contact hole.

Step 12, described N+ silicon chip is carried out to thinning back side.

For solving the problems of the technologies described above, the manufacture method of the terminal protection structure of the 7th kind of described super-junction device provided by the invention comprises the steps:

Step 6, carry out photoetching, Implantation and push away trap at the formation P in described current flowing district type back of the body grid.

Step 8, deposit form interlayer film.

Step 9, carry out chemical wet etching and form contact hole.

Step 12, described N+ silicon chip is carried out to thinning back side.

The present invention utilizes charge compensation, field plate techniques and the equipotential ring technology of P/N thin layer by combination; particularly, by being the optimization of most peripheral p type island region and the joint portion between terminal protection structure in current flowing district in most peripheral unit, can improve device withstand voltage characteristic and obtain high current handling capability.Concrete reason is as follows: the present invention adopts the combining structure of polysilicon field plate and Metal field plate in the region of described current flowing district and described terminal protection structure combination, can relax the electric field of device surface, thereby can improve the voltage endurance of device; It is described P type ring that the present invention also keeps a higher P district of concentration under field plate, the current handling capability in the time of can improving device and apply in inductive circuit; Simultaneously, in described terminal protection structure of the present invention, P/N post is that the degree of depth of described P type post and described N-type post is described p type island region in current flowing district and the degree of depth in described N-type district lower than device temporary location, when in the time of can guaranteeing to apply in inductive circuit, device turn-offs and current over pulse occurs, the position that class avalanche breakdown in described terminal protection structure occurs guarantees in the position near front side of silicon wafer, thereby can make to puncture holoe carrier while occurring, can just reach negative electrode through shorter distance, the anti-overshoot current ability of device in the circuit of inductive element existence strengthened; In addition, in described terminal protection structure of the present invention, also adopt the P/N post of different depth, different steppings, can further reduce surface field, improved the voltage endurance of device; Channel cutoff ring of the present invention can prevent that thereby the N-type surface of device perimeter from easily forming inversion layer and occurring leaky due to the existence of surface field.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the vertical view one of the terminal protection structure of embodiment of the present invention super-junction device;

Fig. 2 is the vertical view two of the terminal protection structure of embodiment of the present invention super-junction device;

Fig. 3-Fig. 9 is the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention one to seven super-junction device.

Embodiment

As shown in Figure 1, be the vertical view one of the terminal protection structure of embodiment of the present invention super-junction device.On vertical view, the embodiment of the present invention can be divided into 1st district, 2nd district and 3rd district.1st district is that the zone line of super-junction device is current flowing district, and described current flowing district comprises the 25HeNXing region, territory, p type island region in the described N-type epitaxial loayer of being formed at of alternative arrangement; At described current flowing district electric current, can by source electrode, through raceway groove, arrive drain electrode by N-type region, and territory, described p type island region 25 is to bear voltage under reverse blocking state together with formation depletion region, described N-type region.The terminal protection structure region that 2nd district and 3rd district are described super-junction device; described in when break-over of device, terminal protection structure does not provide electric current, at reverse blocking state, for bearing from 1 periphery unit, district, is that the surface in territory, periphery p type island region 25 to this voltage of voltage of device outer-most end surface substrate, be lateral voltage He Cong 1 district's periphery cell surface is lateral voltage to this voltage of voltage of substrate.In 2nd district, having at least one P type ring 24, is a P type ring 24 in Fig. 1, and this P type ring 24 is general to link together with the P type back of the body grid in 1st district; In 2nd district, also have for slowing down surface field polycrystalline field plate jumpy sheet P1 and Metal field plate P2, and P type post 23.3rd district bear district by P type post 23 and the voltage that the N-type post being comprised of N-type epitaxial loayer alternately forms, in 3rd district, there is Metal field plate P1, in 3rd district, can have P type ring 24 also can not have, while having P type ring 24, the P type in the P type Huan Shibuyu current flowing district at this place back of the body grid connect (suspension) being connected; Outermost end in 3rd district has channel cutoff ring 21, and described channel cutoff ring 21 adds medium formed thereon by N+ injection region or N+ injection region again or medium adds that metal forms; At described P type post 23, at place, four angles, can there is additional little P type post 22, in order to better to realize charge balance.As seen from Figure 1, the cellular construction in described current flowing district is that 25HeNXing region, territory, described p type island region is all strip structure; Periphery and described P type ring 24, described P type post 23 and described channel cutoff ring 21 that described terminal protection structure is surrounded on described current flowing district are all tetragonal circulus, also can be tetragonal four jiaos of circuluses that have circular arc.

As shown in Figure 2; it is the vertical view two of the terminal protection structure of embodiment of the present invention super-junction device; structure difference is as shown in Figure 1; cellular construction in described current flowing district is that 25HeNXing region, territory, described p type island region is all tetragonal structure, 25HeNXing region, territory, tetragonal described p type island region proper alignment on two-dimensional directional, consists of the cell array in described current flowing district.25HeNXing region, territory, described p type island region can be also hexagon, octagon and other shape, and the arrangement mode in 25HeNXing region, territory, described p type island region also can be at X, and Y-direction is carried out certain dislocation; As long as guarantee that whole arrangement is by certain rule, repeat just passable.

The additional little P type post 22 of four jiaos in Fig. 1 and Fig. 2, can design according to the optimized requirement of local charge balance, if the width of described P type post 23 is a, distance between described P type post 23 and described P type post 23 is also a, and it is the square P type hole of 0.3～0.5a that so described little P type post 22 can adopt the length of side.

As shown in Figure 3, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention one super-junction device.The zone line that is formed with N-type epitaxial loayer 2nd, 1 district and is the embodiment of the present invention one super-junction device on a N+ silicon chip 1 is current flowing district, and described current flowing district comprises the 25HeNXing region, territory, p type island region in the described N-type epitaxial loayer 2 of being formed at of alternative arrangement, one P type back of the body grid 3 are formed at 25 tops, territory, p type island region described in each or described P type back of the body grid 3 and are formed at 25 tops, territory, p type island region described in each and extend in the described N-type region of 25 both sides, top, territory, p type island region described in each, one source region 11 is formed at described in each in P type back of the body grid 3, described N-type epitaxial loayer 2 tops in described current flowing district are formed with grid oxygen 7, grid by polysilicon gate 8, is drawn and source electrode is drawn by source region 11, metal level 13 is drawn described grid or source electrode by contact hole 10 and described polysilicon gate 8 or described source region 11, P+ ion implanted region 12 forms ohmic contact between described P type back of the body grid 3 and subsequent metal layer, at the back side of described N+ silicon chip 1, be formed with metal layer on back 14 and draw drain electrode.

2nd district and 3rd district are the terminal protection structure region of the embodiment of the present invention one super-junction device.The terminal protection structure of the embodiment of the present invention one super-junction device is around in the periphery in described current flowing district and comprises at least one P type ring 24; a plurality of P type posts 23; one channel cutoff ring 21, one terminal deielectric-coating 6, at least one polysilicon field plate P1 and a plurality of Metal field plate P2.Described P Xing Zhu23 2nd district are that the P type post 23 that the P type post 23 of P type post 5-1,3 inner sides, district is P type post 5-2,3 outsides, district is P type post 5-3.

Described in each, P type post 5-1,5-2,5-3 are formed at P type post 5-1,5-2,5-3 in the described N-type epitaxial loayer 2 in described terminal protection structure region and described in each and are arranged in order in 21, the territory, outermost p type island region 25 in described current flowing district and described channel cutoff ring, described in each P type post 23 and described in each N-type epitaxial loayer of 23, P type post form P type post and N-type post alternative expression structure.Territory, described p type island region 25 and described P type post 5-1,5-2,5-3 fill P type silicon again and form in described groove after forming groove in described N-type epitaxial loayer.The deep equality of described P type post 5-1,5-2,5-3 and be all less than the degree of depth in territory, described p type island region.

Described P type ring 24 is formed in the superficial layer of the described N-type silicon epitaxy layer 2 in 2nd district in described terminal protection structure region and is adjacent with territory 25, described outermost p type island region.Described P type ring 24 is coated with a plurality of described P type post 5-1.The doping content of described P type ring 24 is greater than the doping content of described P type post 5-1.

Described channel cutoff ring 21 is formed in the superficial layer of the described N-type epitaxial loayer 2 outside outermost P type post 5-3.

Described terminal deielectric-coating 6 is formed on the described N-type silicon epitaxy layer 2 in described terminal protection structure region; one side in the close described current flowing district of described terminal deielectric-coating 6 has a ledge structure, and described terminal deielectric-coating 6 has covered the P type post of described ledge structure bottom to all described P type post 23 of described outermost P type intercolumniation.Described ledge structure is arranged in 3rd district and does not cover described P type ring 24, and the inclination angle of described ledge structure is 10 degree～75 degree.

Described polysilicon field plate P1 is formed on described terminal deielectric-coating 6, and described polysilicon field plate P1 covers terminal deielectric-coating 6 described in described ledge structure cover part completely.Polysilicon field plate P1 and 2 isolation of described N-type epitaxial loayer of not covering described terminal deielectric-coating 6 have grid oxygen 7.Described polysilicon field plate P1 is separated with a segment distance mutually with described polysilicon gate 8.

It is upper that one interlayer film 9 is formed at the described N-type epitaxial loayer 2 in described terminal protection structure region, described terminal deielectric-coating 6 and described polysilicon field plate P1, is also formed with described interlayer film 9 and is isolated from described current flowing district and metal interlevel in 1st district.In 2nd district and 3rd district, described a plurality of Metal field plate P2 is formed on described interlayer film 9, described Metal field plate P2 is formed by metal level 13 chemical wet etchings, described in each, Metal field plate P2 lays respectively on the described interlayer film 6 on described P type ring 24 or on described P type post 5-2,5-3 or described channel isolation ring 21, and described in one of them, to be covered in completely on described ledge structure be that described Metal field plate P2 in T1 frame is covered on described ledge structure completely to Metal field plate P2.Described Metal field plate P2 in T1 frame is connected with source electrode, and a part of the described Metal field plate P2 in T1 frame has covered described P type ring 24 completely.Described polysilicon field plate P1, with to be located thereon and to be positioned at the described Metal field plate P2 that described ledge structure outside the described source electrode of getting along well be connected connected by a contact hole 10, can not be connected between the two yet.

The described P type post of alternative arrangement that described P type ring in 2nd district is formed by described P type post 5-1 and N-type epitaxial loayer 2 for 24 times and the stepping of described N-type post are less than or equal to described p type island region in 1st district and the stepping in described N-type district, and the described P type post in 2nd district and the width ratio of described N-type post are more than or equal to described p type island region in 1st district and the width ratio in described N-type district; For example: the width of the described p type island region in 1st district is 5 microns and described N-type district while being 10 microns of width, and P type post described in 2nd district and described N-type post can be 7 microns and 8 microns or 6 microns and 9 microns or 5 microns and 10 microns.Described P type post 5-2,5-3 in 3rd district and N-type epitaxial loayer form described P type post and the described N-type rod structure of alternative arrangement and bear district as voltage, on the described P type post in 3rd district and described N-type rod structure, are also formed with polysilicon field plate P1 and Metal field plate P2; From 3rd district in the most close 2nd district, to 3 interval described P type post 5-2 of outermost end, the stepping of 5-3, can change, total impurities amount in described P type post 5-2,5-3 also can change with the ratio of the N total impurities of the described N-type post of same even depth, for example, and the mode that direction from described current flowing district toward described channel cutoff district proportionally diminishes from the inside to surface changes adjustment: be 1～1 at the ratio of the inside.35, in outermost, can be 1～0.65。Outermost end in 3rd district has described channel cutoff ring 21, described channel cutoff ring 21 adds metal formed thereon by N+ injection region or N+ injection region again and forms, and is formed with in embodiments of the present invention Metal field plate P2 and is connected with described Metal field plate P2 by contact hole 10 on described channel cutoff ring 21; Thereby described channel cutoff ring 21 also can not be connected with the described Metal field plate P2 on it, this Metal field plate P2 is suspended, this Metal field plate P2 also can arrange polysilicon field plate P1, and polysilicon field plate P1 is not set in the embodiment of the present invention one.

As shown in Figure 4, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention two super-junction devices.The embodiment of the present invention two with the difference of embodiment mono-is: in 2nd district, be also that described in T1 block diagram, Metal field plate P2 is not connected with source electrode, the ledge structure of described terminal deielectric-coating 6 is positioned on described P type ring 24, and Metal field plate P2 described in T1 block diagram has covered the described P type of part ring 24.Polysilicon field plate P1 described in described T1 block diagram is come to form by outermost polysilicon gate 8 extensions in described current flowing district, and this polysilicon field plate P1 is also connected with described grid.The setting of the described P type post of the embodiment of the present invention two and described channel cutoff ring 21 and other Metal field plate or polysilicon field plate and the embodiment of the present invention one identical.

As shown in Figure 5, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention three super-junction devices.The embodiment of the present invention three with the difference of the embodiment of the present invention two is: Metal field plate P2 described in T1 block diagram is connected with described source electrode, and a part of this Metal field plate P2 has covered the described P type of part ring 24.

As shown in Figure 6, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention four super-junction devices.The embodiment of the present invention four with the difference of the embodiment of the present invention three is: the part extending in 3rd district of the described polysilicon field plate P1 in T1 block diagram is not connected with the Metal field plate P2 on it.

As shown in Figure 7, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention five super-junction devices.The difference of the embodiment of the present invention four and the embodiment of the present invention three is: have at least a degree of depth that is arranged in the 3 outermost described P type post 5-3 in district to be less than the degree of depth of the described P type post 5-1 in described 2nd district.

As shown in Figure 8, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention six super-junction devices.The difference of the embodiment of the present invention six and the embodiment of the present invention one is: territory, described p type island region 25 and described P type post 5-1, 5-2, 5-3 forms groove 4 in described N-type epitaxial loayer 2, 4-1, after 4-2 and 4-3 again at described groove 4, 4-1, in 4-2 and 4-3, fill that P type silicon forms, but adopt repeated technique extension on N+ silicon chip 1 to form multilayer N-type silicon and at selection area, inject p type impurity after each layer of N-type silicon forms, by each layer of N-type silicon, form together described N-type silicon epitaxy layer 2, p type impurity by the same area of each floor forms respectively the territory, described p type island region 25 in 1st district together, described P type post 5-2 in described P Xing Zhu5-1He 3rd district in 2nd district, 5-3.

As shown in Figure 9, be the sectional view along AA ' in Fig. 1 of the terminal protection structure of the embodiment of the present invention seven super-junction devices.The difference of the embodiment of the present invention seven and the embodiment of the present invention six is: have at least a degree of depth that is arranged in the 3 outermost described P type post 5-3 in district to be less than the degree of depth of the described P type post 5-1 in described 2nd district.

For the device of the various structures as shown in Fig. 3～Fig. 9, when the puncture voltage of device requires to be greater than 600V, the thickness of wherein said N-type silicon epitaxy layer 2 is 40 microns～60 microns, and the degree of depth in territory, p type island region 25 described in 1st district is 35 microns～50 microns; Thickness 800 dust～1200 dusts of grid oxygen 7, the thickness of polysilicon 8 is 3000 dust～0000 dusts, and the thickness of described terminal deielectric-coating 6 is 5000 dust～15000 dusts, and the thickness of described interlayer film 9 is 5000 dust～15000 dusts.

As shown in Fig. 3～Fig. 7, the manufacture method of the terminal protection structure of super-junction device comprises the steps: described in the embodiment of the present invention one

Step 1, on a N+ silicon chip 1, form N-type silicon epitaxy layer 2, on described N-type silicon epitaxy layer 2, form the P type back of the body grid 3 in current flowing district and the P type ring 24 in terminal protection structure region.

Step 2, utilize chemical wet etching in described current flowing district 1st district form groove 4, and 2nd district and 3rd district form groove 4-1,4-2 and 4-3 in described terminal protection structure region.The degree of depth of described groove 4,4-1,4-2 and 4-3 arrives on N+ silicon chip 1 or is only retained in described N-type silicon epitaxy layer 2.Described groove 4-1, the 4-2 in 2nd district and 3rd district and the degree of depth of 4-3 are less than the degree of depth of the described groove 4 in 1st district.

For as Fig. 3～while all equating as groove 4-1,4-2 as described between Fig. 6 and 4-3, can adopt the direction of Twi-lithography and etching to form respectively the described groove 4 of different depth and described groove 4-1,4-2 and the 4-3 in 2nd district and 3rd district; Also can utilize the micro loading effect of etching to realize the formation of groove of the different depth in 1st district and 2,3 intervals, for example: to 5 microns of wide grooves 4 in 1st district, when its degree of depth reaches 45 microns, groove 4-1,4-2 and the 4-3 of 2 microns wide in 2 and 3 districts, its degree of depth is only had an appointment 25 microns, by adopting the width groove different from 1st district in 2nd district with 3rd district, just can obtain the groove structure of different depth like this.

While being less than described groove 4-1, the 4-2 of 2nd district and inner side, 3rd district for the described groove 4-3 in 3 districts outsides as shown in Figure 7, can adopt third photo etching and etching to realize respectively; Also can utilize the micro loading effect of etching to realize, for example, to 5 microns of wide grooves 4 in 1st district, when its degree of depth reaches 45 microns, groove 4-1 and the 4-2 of other 2 microns wide of employings in 2 and 3 districts, its degree of depth is only had an appointment 25 microns, adopts the groove 4-3 of 1 micron of one group of width in 3 district's outermost end, and its degree of depth is only had an appointment 10 microns, by adopting two kinds of grooves that width is different from 1 sector width in 2nd district with 3rd district, just can obtain the groove structure of three kinds of different depths like this.

Step 3, in described groove 4,4-1,4-2 and 4-3, form P type silicon and the silicon on described N-type epitaxial loayer 2 surfaces removed, thus in described current flowing district, form alternative arrangement Yu HeNXing region, described p type island region, in described terminal protection structure region, form described P type post and the described N-type post of alternative arrangement.

Thereby step 4, deposition dielectric film also utilize chemical wet etching that the film in 1st district is removed and in described terminal protection structure region, forms terminal deielectric-coating 6; One side in the close described current flowing district of described terminal deielectric-coating 6 has a ledge structure.

Step 5, on described N+ silicon chip 1, form grid oxygen 7 and polysilicon 8; utilize chemical wet etching in described current flowing district, to form the gate patterns being formed by described polysilicon 8; in described terminal protection structure region, form at least one polysilicon field plate P1, described polysilicon field plate P1 covers terminal deielectric-coating 6 described in described ledge structure cover part completely.

Step 6, utilize photoetching and ion implantation technology to form source region 11 and channel cutoff ring 21.

Step 7, deposit form interlayer film 9.

Step 8, carry out chemical wet etching and form contact hole 10.

Step 9, the ohmic contact that P+ Implantation forms described P type back of the body grid 3 and subsequent metal layer 13 of carrying out.

Step 10, at described N+ silicon chip 1 surface deposition metal level 13, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plate P2, described in each, Metal field plate P2 lays respectively on described P type ring 24 or described P type post 23 is on the described interlayer film 9 on described P type post 5-1,5-2 and 5-3, and described in one of them, Metal field plate P2 is that described Metal field plate P2 in T1 block diagram is covered on described ledge structure completely.

Step 11, described N+ silicon chip 1 is carried out to thinning back side.

Step 12, at described N+ silicon chip 1 back side, grow metal layer on back 14 formation drain electrode.

Described in the embodiment of the present invention two, the difference of the manufacture method of the terminal protection structure of super-junction device and the embodiment of the present invention one is: the step that forms described P type back of the body grid 3 and described P type ring 24 is not to be placed in step 1 in the step before forming described groove, but be placed in the next step that forms described terminal deielectric-coating 6, is in the next step of the step 4 in the embodiment of the present invention one.

Described in the embodiment of the present invention three, the difference of the manufacture method of the terminal protection structure of super-junction device and the embodiment of the present invention one is: in step 1, in the step before forming described groove, retained the step that forms described P type ring 24; And the step that forms described P type back of the body grid 3 is placed in the next step that forms described terminal deielectric-coating 6, be in the next step of the step 4 in the embodiment of the present invention one.

Described in the embodiment of the present invention four, the difference of the manufacture method of the terminal protection structure of super-junction device and the embodiment of the present invention one is: in step 1, in the step before forming described groove, retained the step that forms described P type ring 24; And the step that forms described P type back of the body grid 3 is placed in the next step that forms described gate patterns and described polysilicon field plate P2, be in the next step of the step 5 in the embodiment of the present invention one.

As shown in Figure 8 and Figure 9, described in the embodiment of the present invention five, the manufacture method of the terminal protection structure of super-junction device comprises the steps:

Step 1, on a N+ silicon chip 1 epitaxial growth one deck N-type silicon, by photoetching, in described N-type silicon, define the injection zone of p type impurity and inject p type impurity.

The technique of step 2, repeating step 1 5～7 times, obtain the N-type silicon epitaxy layer 2 being formed by multilayer N-type silicon, the p type impurity that is formed at the same area in each floor N-type silicon forms the territory, p type island region 25 in current flowing district and the P type post 23 in terminal protection structure region, and described P type post 23 comprises P type post 5-2 and the 5-3 that is formed at the P type post 5-1 in 2nd district, the inner side that is formed at 3rd district and outside; Thereby in described current flowing district, form the Yu HeNXing region, described p type island region of alternative arrangement and described P type post and the described N-type post that forms alternative arrangement in terminal protection structure region.

As shown in Figure 8, the 6 layers of described N-type silicon of having grown altogether, different according to the degree of depth of the P type post 5-1 in 25,2 districts, described type region in 1st district and the P type post 5-2 in 3rd district and 5-3, the graphical layout of the mask plate of the p type impurity injection zone after each layer of described N-type silicon forms is also different, by regulating the injection number of times of p type impurity to regulate the degree of depth of described type region 25 and P type post 23 described in each.Wherein, in the described N-type silicon of 6 floor in 1st district, at formation 25 places, territory, described p type island region, all carry out p type impurity injection, inject for totally 6 times; In 2nd district and 3rd district, in rear 4 layers of described N-type silicon, at formation described P type post 23 places, all carry out p type impurity injection, inject for totally 4 times.Therefore formed described in each degree of depth of P type post 23 all identical and be all less than the degree of depth in territory, described p type island region 25.

As shown in Figure 9, four described P type post 5-3 in 3 outsides, district only carry out p type impurity injection at formation described P type post 5-3 place in the described N-type silicon of rear 2 floor, inject for totally 2 times.Therefore the degree of depth of formed described P type post 5-3 is all less than the degree of depth of described P type post 5-1 and 5-2.

Step 3, the formation P type back of the body grid 3 that carry out photoetching and the described current flowing district of Implantation on described N-type silicon epitaxy layer and described terminal protection structure region form P type ring 24.

Step 7, deposit form interlayer film 9.

Step 8, carry out chemical wet etching and form contact hole 10.

Step 10, at described N+ silicon chip 1 surface deposition metal level 13, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plate P2, described in each, Metal field plate P2 lays respectively on the described interlayer film 9 on described P type ring 24 or on described P type post 5-1,5-2 and 5-3, and described in one of them, Metal field plate P2 is covered on described ledge structure completely.

Step 11, described N+ silicon chip 1 is carried out to thinning back side.

Step 12, the metal layer on back 14 of growing at described N+ silicon chip 1 back side form drain electrode.

Described in the embodiment of the present invention six, the difference of the manufacture method of the terminal protection structure of super-junction device and the embodiment of the present invention five is: the step that simultaneously forms P type back of the body grid 3 and described P type ring 24 in the step 3 of the embodiment of the present invention five is separated into two steps, and two steps after separating are: first carry out photoetching, Implantation and push away trap in described terminal protection structure region, forming P type ring 24; And then next step carries out photoetching, Implantation again at the formation P in described current flowing district type back of the body grid.

Described in the embodiment of the present invention seven, the difference of the manufacture method of the terminal protection structure of super-junction device and the embodiment of the present invention five is: the step that simultaneously forms P type back of the body grid 3 and described P type ring 24 in the step 3 of the embodiment of the present invention five is separated into two steps, and two steps after separating are: first carry out photoetching, Implantation and push away trap in described terminal protection structure region, forming P type ring 24; Again by carry out photoetching, Implantation and push away trap the step of the formation P in described current flowing district type back of the body grid be placed on the step that forms described gate patterns and described polysilicon field plate P1 be the embodiment of the present invention five step 5 after in a step.

By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. the terminal protection structure of a super-junction device, on a N+ silicon chip, be formed with a N-type epitaxial loayer, the zone line of super-junction device is current flowing district, described current flowing district comprises the Yu HeNXing region, p type island region in the described N-type epitaxial loayer of being formed at of alternative arrangement, one P type back of the body grid are formed at top, territory, p type island region described in each or described P type back of the body grid and are formed at top, territory, p type island region described in each and extend in the described N-type region of both sides, top, territory, p type island region described in each, one source region is formed at described in each in P type back of the body grid, described N-type epitaxial loayer top in described current flowing district is formed with grid oxygen, grid and source electrode, the back side at described N+ silicon chip is formed with drain electrode, it is characterized in that:

The terminal protection structure of described super-junction device is surrounded on the periphery in described current flowing district and comprises at least one P type ring, a plurality of P type post, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate and a plurality of Metal field plate; Described P type ring, described P type post and described channel cutoff ring be structure by the interior periphery that is surrounded on successively outward described current flowing district in the form of a ring all;

Described in each, P type cylindricality is formed in P type post in the described N-type epitaxial loayer in described terminal protection structure region and described in each and is arranged in order territory, outermost p type island region and the described channel cutoff interannular in described current flowing district, described in each P type post and described in each N-type epitaxial loayer of P type intercolumniation form P type post and N-type post alternative expression structure;

Described P type annular is formed in the superficial layer of described N-type silicon epitaxy layer in described terminal protection structure region and is adjacent with territory, described outermost p type island region;

Described channel cutoff annular is formed in the superficial layer of the described N-type epitaxial loayer outside outermost P type post;

Described terminal deielectric-coating is formed on the described N-type silicon epitaxy layer in described terminal protection structure region, one side in the close described current flowing district of described terminal deielectric-coating has a ledge structure, and described terminal deielectric-coating has covered the P type post of described ledge structure bottom to all described P type post of described outermost P type intercolumniation;

Described polysilicon field plate is formed on described terminal deielectric-coating, and described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely;

One interlayer film is formed on the described N-type epitaxial loayer in described terminal protection structure region, described terminal deielectric-coating and described polysilicon field plate; Described a plurality of Metal field plate is formed on described interlayer film, and described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely.

2. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: the depth as shallow in the territory, p type island region in current flowing district described in the depth ratio of P type post described at least one.

3. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: described at least one group, the width of P type post and the width ratio of described N-type post are greater than the width in territory, described p type island region and the width ratio in described N-type region in described current flowing district.

4. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: identical with the width ratio of described N-type post or successively decrease along described current flowing district toward the width of P type post described in described channel cutoff ring direction.

5. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: identical or successively decrease along described current flowing district toward the degree of depth of P type post described in described channel cutoff ring direction.

6. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: described P type ring territory, outermost p type island region from described current flowing district covers described at least one P type post and N-type post described at least one outward.

7. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: the impurity concentration of described P type ring is greater than the impurity concentration of described P type post.

8. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: the impurity process conditions of described P type ring are identical with the impurity process conditions of described P type back of the body grid.

9. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: be positioned at described Metal field plate on the described interlayer film on described P type ring and have at least a part all to cover or part covers described P type ring.

10. the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that: the described Metal field plate being positioned on the described interlayer film on described P type ring is connected with described source electrode or is suspended on described interlayer film.

11. terminal protection structures of super-junction device as claimed in claim 1, is characterized in that: described polysilicon field plate is connected with described grid or is suspended on described terminal deielectric-coating.

12. terminal protection structures of super-junction device as claimed in claim 1, is characterized in that: described polysilicon field plate be located thereon and be positioned at that described Metal field plate that described ledge structure outside the described source electrode of getting along well be connected is connected or connected.

13. terminal protection structures of super-junction device as claimed in claim 1, is characterized in that: the inclination angle of described ledge structure is 10 degree～75 degree.

14. terminal protection structures of super-junction device as claimed in claim 1; it is characterized in that: on described channel cutoff ring, be coated with described Metal field plate or described polysilicon field plate, the described Metal field plate or the described polysilicon field plate that are covered on described channel cutoff ring are connected or suspend with described channel cutoff ring.

15. terminal protection structures of super-junction device as claimed in claim 1; it is characterized in that: on described channel cutoff ring, cover the described polysilicon field plate suspending and be coated with Metal field plate on described polysilicon field plate, described Metal field plate is connected or suspends with described polysilicon field plate.

16. terminal protection structures of super-junction device as claimed in claim 1, is characterized in that: the circulus that is square or described P type post in the circulus of the above P type post of top plan view is tetragonal four jiaos of structures that have circular arc.

17. terminal protection structures of super-junction device as claimed in claim 1, is characterized in that: the quadrangle in the circulus of described P type post becomes to have additional P type post.

18. terminal protection structures of super-junction device as claimed in claim 17, is characterized in that: described additional P type post is connected or separates with described P type post.

19. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, on described N-type silicon epitaxy layer, form the P type back of the body grid in current flowing district and the P type ring in terminal protection structure region;

Step 2, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in described current flowing district and described terminal protection structure region;

Step 3, in described groove, form P type silicon and the silicon of described N-type epi-layer surface removed, thus in described current flowing district, form alternative arrangement Yu HeNXing region, described p type island region, in described terminal protection structure region, form described P type post and the described N-type post of alternative arrangement;

Step 4, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure;

Step 5, on described N+ silicon chip, form grid oxygen and polysilicon, utilize chemical wet etching in described current flowing district, to form the gate patterns being formed by described polysilicon, in described terminal protection structure region, form at least one polysilicon field plate, described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely;

Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;

Step 7, deposit form interlayer film;

Step 8, carry out chemical wet etching and form contact hole;

Step 9, the ohmic contact that P+ Implantation forms described P type back of the body grid and subsequent metal layer of carrying out;

Step 10, at described N+ silicon chip surface deposition metal level, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plates, described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely;

Step 11, described N+ silicon chip is carried out to thinning back side;

20. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in current flowing district and terminal protection structure region;

Step 2, in described groove, form P type silicon and the silicon of described N-type epi-layer surface removed, thus in described current flowing district, form alternative arrangement Yu HeNXing region, described p type island region, in described terminal protection structure region, form described P type post and the described N-type post of alternative arrangement;

Step 3, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure;

Step 4, the P type back of the body grid that form current flowing district on described N-type silicon epitaxy layer and the P type ring in terminal protection structure region;

Step 7, deposit form interlayer film;

Step 8, carry out chemical wet etching and form contact hole;

Step 11, described N+ silicon chip is carried out to thinning back side;

21. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 1, on a N+ silicon chip, form N-type silicon epitaxy layer, utilize photoetching and Implantation in terminal protection structure region, to form P type ring;

Step 2, utilize chemical wet etching to form groove on the described N-type epitaxial loayer in current flowing district and terminal protection structure region;

Step 5, the current flowing district on described N-type silicon epitaxy layer form P type back of the body grid;

Step 6, on described N+ silicon chip, form grid oxygen and polysilicon, utilize chemical wet etching in described current flowing district, to form the gate patterns being formed by described polysilicon, in described terminal protection structure region, form at least one polysilicon field plate, described polysilicon field plate covers terminal deielectric-coating described in described ledge structure cover part completely;

Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;

Step 8, deposit form interlayer film;

Step 9, carry out chemical wet etching and form contact hole;

Step 10, the ohmic contact that P+ Implantation forms described P type back of the body grid and subsequent metal layer of carrying out;

Step 11, at described N+ silicon chip surface deposition metal level, and carry out chemical wet etching and form the electrode pattern of described source electrode and described grid and form a plurality of Metal field plates, described in each, Metal field plate lays respectively on the described interlayer film on described P type ring or on described P type post, and described in one of them, Metal field plate is covered on described ledge structure completely;

Step 12, described N+ silicon chip is carried out to thinning back side;

22. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 6, utilize Implantation and push away the current flowing district of trap technique on described N-type silicon epitaxy layer and form P type back of the body grid;

Step 8, deposit form interlayer film;

Step 9, carry out chemical wet etching and form contact hole;

Step 12, described N+ silicon chip is carried out to thinning back side;

23. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 1, on a N+ silicon chip epitaxial growth one deck N-type silicon, by photoetching, in described N-type silicon, define the injection zone of p type impurity and inject p type impurity;

The technique of step 2, repeating step 1 5～7 times, obtain the N-type silicon epitaxy layer being formed by multilayer N-type silicon, the p type impurity that is formed at the same area in each floor N-type silicon forms the territory, p type island region in current flowing district and the P type post in terminal protection structure region, thereby in described current flowing district, forms the Yu HeNXing region, described p type island region of alternative arrangement and described P type post and the described N-type post that forms alternative arrangement in terminal protection structure region;

Step 3, the formation P type back of the body grid that carry out photoetching and the described current flowing district of Implantation on described N-type silicon epitaxy layer and described terminal protection structure region form P type ring;

Step 7, deposit form interlayer film;

Step 8, carry out chemical wet etching and form contact hole;

Step 11, described N+ silicon chip is carried out to thinning back side;

24. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 3, carry out photoetching, Implantation and push away trap in described terminal protection structure region, forming P type ring;

Step 4, carry out photoetching and Implantation at the formation P in described current flowing district type back of the body grid;

Step 5, deposition dielectric film also utilize chemical wet etching in described terminal protection structure region, to form terminal deielectric-coating; One side in the close described current flowing district of described terminal deielectric-coating has a ledge structure;

Step 8, deposit form interlayer film;

Step 9, carry out chemical wet etching and form contact hole;

Step 12, described N+ silicon chip is carried out to thinning back side;

25. 1 kinds of manufacture methods of the terminal protection structure of super-junction device as claimed in claim 1, is characterized in that, comprise the steps:

Step 6, carry out photoetching, Implantation and push away trap at the formation P in described current flowing district type back of the body grid;

Step 8, deposit form interlayer film;

Step 9, carry out chemical wet etching and form contact hole;

Step 12, described N+ silicon chip is carried out to thinning back side;