CN102738207A - Super junction device terminal protection structure and manufacturing method thereof - Google Patents

Super junction device terminal protection structure and manufacturing method thereof Download PDF

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CN102738207A
CN102738207A CN2011100862404A CN201110086240A CN102738207A CN 102738207 A CN102738207 A CN 102738207A CN 2011100862404 A CN2011100862404 A CN 2011100862404A CN 201110086240 A CN201110086240 A CN 201110086240A CN 102738207 A CN102738207 A CN 102738207A
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protection structure
terminal protection
field plate
electric current
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CN102738207B (en
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肖胜安
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a terminal protection structure of a super junction device. The composite structure of polysilicon field plates and metal field plates is employed, and a group of polysilicon field plates and metal field plates simultaneously cover the step structure of a terminal dielectric film, thus an electric field on the device surface is eased. According to the invention, a P-type ring with a high concentration is kept under a field plate, thus the current processing capability of the application of the device in an inductive circuit is improved. In the terminal protection structure provided by the invention, the depth of a P-type column and a N-type column is lower than the depth of a P-type area and a N-type area in a current flowing area to ensure that the device is turned off when the device is applied in the inductive circuit and that the position where an avalanche breakdown occurs in the terminal protection structure is close to the position of the obverse of a silicon chip when a current overshoot occurs, and to improve the capacity of anti-overshoot current of the device. The invention further discloses the super junction device terminal protection structure and a manufacturing method thereof. According to the invention, the breakdown characteristic, the current processing capability and the reliability of the device is improved without process cost increasement.

Description

The terminal protection structure of super junction device and manufacturing approach
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of terminal protection structure of super junction device; The invention still further relates to a kind of manufacturing approach of terminal protection structure of super junction device.
Background technology
Super junction MOSFET adopts new structure of voltage-sustaining layer; Utilize a series of P type semiconductor thin layer of alternately arranging and N type semiconductor thin layer under cut-off state, under low voltage, just said P type semiconductor thin layer and N type semiconductor thin layer to be exhausted; Realize that electric charge compensates each other; Thereby make P type semiconductor thin layer and N type semiconductor thin layer under high-dopant concentration, can realize high puncture voltage, thereby obtain low on-resistance and high-breakdown-voltage simultaneously, the power MOSFET theoretical limit breaks traditions.The same with existing DMOS device, a super junction MOSFET is formed by a lot of unit repeated arrangement; Because the consistency of each unit, be in surface potential basically identical between the unit of the parallel connection in the middle of the device, there is not the problem of voltage breakdown usually; But the unit and the substrate surface electrical potential of outmost turns are variant; Particularly working under the cut-off state, voltage difference is bigger, is easy to puncture; Periphery in the periphery unit of device will increase terminal protection structure, and should technology very important.
To existing device such as high pressure VDMOS, existing diffusing protection loop technique, field plate techniques is like floating barnyard plate technique, resistive field plate technique, and equipotential ring is technological, field limiting ring technology, knot termination extension technology etc.; But for the super junction device, because the withstand voltage mode of the withstand voltage mode of device cell and traditional VDMOS is very different, the terminal protection structure of high reliability needs otherwise designed accordingly.Some terminal protection structures about super junction MOSFET have been arranged, also adopted P type and the N type post alternately arranged to add the field plate on it at the terminal, added when needing by ring.
Summary of the invention
Technical problem to be solved by this invention provides a kind of terminal protection structure of super junction device, can improve voltage endurance, current handling capability and the reliability of device, does not also increase the technology cost.
For solving the problems of the technologies described above; The present invention provides a kind of terminal protection structure of super junction device; On a N+ silicon chip, be formed with a N type epitaxial loayer; The zone line of super junction device is the electric current flow region; Said electric current flow region comprises the p type island region territory and N type zone in the said N type epitaxial loayer that be formed at of alternately arranging, and P type back of the body grid (P-BODY) are formed at each top, said p type island region territory or said P type back of the body grid and are formed at each top, said p type island region territory and extend in the said N type zone of each both sides, top, said p type island region territory, and a source region is formed at each said P type and carries on the back in grid; Said N type epitaxial loayer top at said electric current flow region is formed with grid oxygen, grid and source electrode, is formed with drain electrode at the back side of said N+ silicon chip.The terminal protection structure of said super junction device is surrounded on the periphery of said electric current flow region and comprises at least one P type ring, a plurality of P type post, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate and a plurality of metal field plate; Said P type ring, said P type post and said channel cutoff ring be structure and by the interior periphery that is surrounded on said electric current flow region outward successively in the form of a ring all.Each said P type cylindricality is formed in the regional said N type epitaxial loayer of said terminal protection structure and each said P type post is arranged in order outermost p type island region territory and said channel cutoff interannular in said electric current flow region, and the N type epitaxial loayer of each said P type post and each said P type intercolumniation is formed P type post and N type post alternative expression structure.Said P type annular is formed in the superficial layer of said N type silicon epitaxy layer in said terminal protection structure zone and is adjacent with said outermost p type island region territory.Said channel cutoff annular is formed in the superficial layer of the said N type epitaxial loayer outside the outermost P type post.Said terminal deielectric-coating is formed on the said N type silicon epitaxy layer in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure, and said terminal deielectric-coating has covered the P type post of said ledge structure bottom all said P type posts to said outermost P type intercolumniation.The polysilicon field plate is formed on the deielectric-coating of said terminal, and said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.One interlayer film is formed on said N type epitaxial loayer, said terminal deielectric-coating and the said polysilicon field plate in said terminal protection structure zone; Said a plurality of metal field plate is formed on the said interlayer film, and each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Further improve and be the depth as shallow in p type island region territory in the said electric current flow region of the depth ratio of at least one said P type post.
Further improve is that the width ratio of the width of at least one group of said P type post and said N type post is greater than the width in the said p type island region territory of said electric current flow region and the width ratio in said N type zone.
Further improve and be, the width along said electric current flow region toward the said P type of said channel cutoff ring direction post is identical with the width ratio of said N type post or successively decrease.
Further improve and be, the degree of depth along said electric current flow region toward the said P type of said channel cutoff ring direction post is identical or successively decrease.
Further improving is that said P type ring covers at least one said P type post and a said N type post outward from said outermost p type island region territory.
Further improving is that the impurity concentration of said P type ring is greater than the impurity concentration of said P type post.
Further improve is that the impurity process conditions of said P type ring are identical with the impurity process conditions of said P type back of the body grid.
Further improve is that the said metal field plate that is positioned on the said interlayer film on the said P type ring has at least whole coverings of a part or part to cover said P type ring.
Further improve and be, be positioned at said metal field plate on the said interlayer film on the said P type ring and link to each other with said source electrode or be suspended on the said interlayer film.
Further improving is that said polysilicon field plate links to each other with said grid or is suspended on the deielectric-coating of said terminal.
Further improve and be, said polysilicon field plate and position are on it and to be positioned at the said metal field plate that the said ledge structure outside and the said source electrode of getting along well link to each other continuous or continuous.
Further improve is that the inclination angle of said ledge structure is 10 degree～75 degree.
Further improve and be, on said channel cutoff ring, be coated with said metal field plate or said polysilicon field plate, be covered in said metal field plate or said polysilicon field plate on the said channel cutoff ring and be connected with said channel cutoff ring or suspend.
Further improvement is, is covering the said polysilicon field plate that suspends on the said channel cutoff ring and on said polysilicon field plate, is being coated with the metal field plate, and said metal field plate links to each other with said polysilicon field plate or suspends.
Further improving and be, is that the circulus of square or said P type post is tetragonal four jiaos of structures that circular arc is arranged in the circulus of the above P type post of top plan view.
Further improve and be, become to have additional P type post at the quadrangle of the circulus of said P type post.Said additional P type post links to each other with said P type post or separates.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of first kind of super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, on said N type silicon epitaxy layer, form the P type back of the body grid of electric current flow region and the P type ring in terminal protection structure zone.
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in said electric current flow region and said terminal protection structure zone, to form groove.
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 7, deposit cambium layer.
Step 8, carry out chemical wet etching and form contact hole.
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 11, said N+ silicon chip is carried out thinning back side.
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of second kind of said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize chemical wet etching on the regional said N type epitaxial loayer of electric current flow region and terminal protection structure, to form groove.
Step 2, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post.
Step 3, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 4, the P type back of the body grid that on said N type silicon epitaxy layer, form the electric current flow region and the regional P type ring of terminal protection structure.
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 7, deposit cambium layer.
Step 8, carry out chemical wet etching and form contact hole.
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 11, said N+ silicon chip is carried out thinning back side.
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of the third said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize photoetching and ion to be infused in terminal protection structure zone formation P type ring.
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in electric current flow region and terminal protection structure zone, to form groove.
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 5, the electric current flow region on said N type silicon epitaxy layer form P type back of the body grid.
Step 6, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 8, deposit cambium layer.
Step 9, carry out chemical wet etching and form contact hole.
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 12, said N+ silicon chip is carried out thinning back side.
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of the 4th kind of said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize photoetching and ion to be infused in terminal protection structure zone formation P type ring.
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in electric current flow region and terminal protection structure zone, to form groove.
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 6, utilize ion to inject and push away the electric current flow region of trap technology on said N type silicon epitaxy layer and form P type back of the body grid.
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 8, deposit cambium layer.
Step 9, carry out chemical wet etching and form contact hole.
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 12, said N+ silicon chip is carried out thinning back side.
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of the 5th kind of said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching.
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region.
Step 3, carry out formation P type back of the body grid and said terminal protection structure zone that photoetching and ion be infused in the said electric current flow region on the said N type silicon epitaxy layer and form P type ring.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 7, deposit cambium layer.
Step 8, carry out chemical wet etching and form contact hole.
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 11, said N+ silicon chip is carried out thinning back side.
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of the 6th kind of said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching.
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region.
Step 3, carry out photoetching, ion and inject and push away trap and form P type ring in said terminal protection structure zone.
Step 4, carry out the formation P type back of the body grid that photoetching and ion are infused in said electric current flow region.
Step 5, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 6, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 8, deposit cambium layer.
Step 9, carry out chemical wet etching and form contact hole.
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 12, said N+ silicon chip is carried out thinning back side.
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
For solving the problems of the technologies described above, the manufacturing approach of the terminal protection structure of the 7th kind of said super junction device provided by the invention comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching.
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region.
Step 3, carry out photoetching, ion and inject and push away trap and form P type ring in said terminal protection structure zone.
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure.
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully.
Step 6, carry out photoetching, ion and inject and push away trap at the formation P of said electric current flow region type back of the body grid.
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring.
Film between step 8, deposit cambium layer.
Step 9, carry out chemical wet etching and form contact hole.
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out.
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
Step 12, said N+ silicon chip is carried out thinning back side.
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
Charge compensation, field plate techniques and the equipotential ring technology of the present invention through combining to utilize the P/N thin layer; Particularly, can improve the device withstand voltage characteristic and obtain high current handling capability through being the most peripheral p type island region of electric current flow region and the optimization of the joint portion between the terminal protection structure in the most peripheral unit.Concrete reason is following: the present invention adopts the combining structure of polysilicon field plate and metal field plate in the zone of said electric current flow region and the combination of said terminal protection structure, can relax the electric field of device surface, thereby can improve the voltage endurance of device; The present invention also keeps the higher P district of concentration under field plate be said P type ring, the current handling capability in the time of can improving device and in inductive circuit, use; Simultaneously; The P/N post is that to be lower than the device temporary location be said p type island region and the degree of depth in said N type district in the electric current flow region for the degree of depth of said P type post and said N type post in the said terminal protection structure of the present invention; Device turn-offs and when current over pulse takes place in the time of can guaranteeing in inductive circuit to use; The position that class avalanche breakdown in the said terminal protection structure takes place guarantees in the position near the silicon chip front; Holoe carrier can just reach negative electrode through short distance when puncturing generation thereby can make, and make the anti-overshoot current ability reinforcement of device in the circuit that inductive element exists; In addition, also adopt the P/N post of different depth, different steppings in the said terminal protection structure of the present invention, can further reduce surface field, improved the voltage endurance of device; Channel cutoff ring of the present invention can prevent that the surperficial existence owing to surface field of the N type of device perimeter is prone to form inversion layer and thereby leaky occurs.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the vertical view one of the terminal protection structure of embodiment of the invention super junction device;
Fig. 2 is the vertical view two of the terminal protection structure of embodiment of the invention super junction device;
Fig. 3-Fig. 9 is the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention one to seven super junction device.
Embodiment
As shown in Figure 1, be the vertical view one of the terminal protection structure of embodiment of the invention super junction device.On vertical view, the embodiment of the invention can be divided into 1 district, 2 districts and 3 districts.1 district is the electric current flow region for the zone line of super junction device, and said electric current flow region comprises the p type island region territory 25 and N type zone in the said N type epitaxial loayer that be formed at of alternately arranging; Can arrive drain electrode by source electrode through raceway groove through N type zone at said electric current flow region electric current, and said p type island region territory 25 is under reverse blocking state, to form depletion region with said N type zone to bear voltage.2 districts and 3 districts are the terminal protection structure zone of said super junction device; Said terminal protection structure does not provide electric current when break-over of device, and being used to bear from periphery unit, 1 district at reverse blocking state is that the surface in periphery p type island region territory 25 is that lateral voltage and this voltage of voltage from 1 district's periphery cell surface to substrate are lateral voltage to this voltage of voltage of device outer-most end surface substrate.At least one P type ring 24 is arranged in 2 districts, is a P type ring 24 among Fig. 1, and these P type ring 24 general P type back of the body grid with 1 district link together; In 2 districts, also have and be used to slow down surface field polycrystalline jumpy field plate P1 and metal field plate P2, and P type post 23.3 districts bear the district by P type post 23 and the voltage that the N type post of being made up of N type epitaxial loayer alternately forms; Metal field plate P1 is arranged in 3 districts; Can have P type ring 24 also can not have in 3 districts, the P type ring at this place was not to be connected (suspension) that links to each other with the P type back of the body grid of electric current flow region when P type ring 24 was arranged; Outermost end in 3 districts has channel cutoff ring 21, and said channel cutoff ring 21 adds medium formed thereon again by N+ injection region or N+ injection region or medium adds that metal constitutes; At place, four angles additional little P type post 22 can be arranged at said P type post 23, in order to better realization charge balance.Can find out that by Fig. 1 the cellular construction of said electric current flow region is that said p type island region territory 25 all is a strip structure with N type zone; Periphery and said P type ring 24, said P type post 23 and said channel cutoff ring 21 that said terminal protection structure is surrounded on said electric current flow region all are tetragonal circulus, also can be tetragonal four jiaos of circuluses that circular arc is arranged.
As shown in Figure 2; It is the vertical view two of the terminal protection structure of embodiment of the invention super junction device; Be with structure difference as shown in Figure 1; Cellular construction at said electric current flow region is that said p type island region territory 25 all is a tetragonal structure with N type zone, promptly is made up of the cell array of said electric current flow region tetragonal said p type island region territory 25 and N type zone proper alignment on two-dimensional directional.Said p type island region territory 25 also can be hexagon, octagon and other shape with N type zone, and the arrangement mode in said p type island region territory 25 and N type zone also can carry out certain dislocation at X and Y direction; As long as guarantee that whole arrangement is by certain rule, repeat to occur just passable.
Four jiaos additional little P type post 22 among Fig. 1 and Fig. 2; Can design according to the optimized requirement of local charge balance; If the width of said P type post 23 is a; Distance between said P type post 23 and the said P type post 23 also is a, and it is the square P type hole of 0.3～0.5a that so said little P type post 22 can adopt the length of side.
As shown in Figure 3, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention one super junction device.On a N+ silicon chip 1, being formed with a N type epitaxial loayer 2,1 districts is the electric current flow region for the zone line of the embodiment of the invention one super junction device, and said electric current flow region comprises the p type island region territory 25 and N type zone in the said N type epitaxial loayer 2 that be formed at of alternately arranging; One P type back of the body grid 3 are formed at each 25 top, said p type island region territory or said P type back of the body grid 3 and are formed at each 25 top, said p type island region territory and extend in the said N type zone of each both sides, 25 top, said p type island region territory; One source region 11 is formed in each said P type back of the body grid 3; Be formed with on said N type epitaxial loayer 2 tops of said electric current flow region that grid oxygen 7, grid are promptly drawn by polysilicon gate 8 and source electrode is promptly drawn by source region 11; Metal level 13 is drawn said grid or source electrode through contact hole 10 and said polysilicon gate 8 or said source region 11, and P+ ion implanted region 12 forms ohmic contact between said P type back of the body grid 3 and subsequent metal layer; Be formed with metal layer on back 14 at the back side of said N+ silicon chip 1 and draw drain electrode.
2 districts and 3 districts are the terminal protection structure zone of the embodiment of the invention one super junction device.The terminal protection structure of the embodiment of the invention one super junction device is around in the periphery of said electric current flow region and comprises at least one P type ring 24; A plurality of P type posts 23; One channel cutoff ring, 21, one terminal deielectric-coating 6, at least one polysilicon field plate P1 and a plurality of metal field plate P2.Said P type post 23 is that the inboard P type post 23 in P type post 5-1,3 districts is P type post 5-3 for the P type post outside P type post 5-2,3 districts 23 in 2 districts.
Each said P type post 5-1,5-2,5-3 are formed in the said N type epitaxial loayer 2 in said terminal protection structure zone and each said P type post 5-1,5-2,5-3 are arranged in order in 21 on the outermost p type island region territory 25 of said electric current flow region and said channel cutoff ring, and the N type epitaxial loayer that each said P type post 23 and each said P type post are 23 is formed P type post and N type post alternative expression structure.The formation of P type silicon is filled after all in said N type epitaxial loayer, forming groove with said P type post 5-1,5-2,5-3 again in said p type island region territory 25 in said groove.The deep equality of said P type post 5-1,5-2,5-3 and all less than the degree of depth in said p type island region territory.
Said P type ring 24 is formed in the superficial layer of the said N type silicon epitaxy layer 2 in 2 districts in said terminal protection structure zone and is adjacent with said outermost p type island region territory 25.Said P type ring 24 is coated with a plurality of said P type post 5-1.The doping content of said P type ring 24 is greater than the doping content of said P type post 5-1.
Said channel cutoff ring 21 is formed in the superficial layer of the said N type epitaxial loayer 2 outside the outermost P type post 5-3.
Said terminal deielectric-coating 6 is formed on the said N type silicon epitaxy layer 2 in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating 6 has a ledge structure, and said terminal deielectric-coating 6 has covered the P type post of said ledge structure bottom all said P type posts 23 to said outermost P type intercolumniation.Said ledge structure is arranged in 3 districts and does not cover said P type ring 24, and the inclination angle of said ledge structure is 10 degree～75 degree.
Said polysilicon field plate P1 is formed on the said terminal deielectric-coating 6, and said polysilicon field plate P1 covers the said terminal of said ledge structure and cover part deielectric-coating 6 fully.Polysilicon field plate P1 and 2 isolation of said N type epitaxial loayer of not covering said terminal deielectric-coating 6 have grid oxygen 7.Said polysilicon field plate P1 is separated with a segment distance mutually with said polysilicon gate 8.
One interlayer film 9 is formed on said N type epitaxial loayer 2, said terminal deielectric-coating 6 and the said polysilicon field plate P1 in said terminal protection structure zone, also is formed with said interlayer film 9 in 1 district and is isolated from said electric current flow region and metal interlevel.In 2 districts and 3 districts; Said a plurality of metal field plate P2 is formed on the said interlayer film 9; Said metal field plate P2 is formed by metal level 13 chemical wet etchings; Each said metal field plate P2 lays respectively on the said P type ring 24 or on the said interlayer film 6 on said P type post 5-2,5-3 or the said channel isolation ring 21, and it is that said metal field plate P2 in the T1 frame is covered on the said ledge structure fully that one of them said metal field plate P2 is covered on the said ledge structure fully.Said metal field plate P2 in the T1 frame is connected with source electrode, and the part of the said metal field plate P2 in the T1 frame has covered said P type ring 24 fully.Said polysilicon field plate P1 and position are on it and to be positioned at the said metal field plate P2 that the said ledge structure outside and the said source electrode of getting along well link to each other continuous through a contact hole 10, also can not link to each other between the two.
The said P type post of alternately arranging that said P type ring in 2 districts 24 times is formed by said P type post 5-1 and N type epitaxial loayer 2 and the stepping of said N type post are smaller or equal to the stepping in said p type island region in 1 district and said N type district, and the said P type post in 2 districts and the width ratio of said N type post are more than or equal to the width ratio in said p type island region in 1 district and said N type district; For example: when the width of the said p type island region in 1 district is 5 microns when being 10 microns of width with said N type district, P type post described in 2 districts and said N type post can be 7 microns and 8 microns or 6 microns and 9 microns or 5 microns and 10 microns.Said P type post 5-2 in 3 districts, 5-3 and N type epitaxial loayer form the said P type post alternately arranged and said N type rod structure and bear the district as voltage, also are formed with polysilicon field plate P1 and metal field plate P2 on the said P type post in 3 districts and the said N type rod structure; From changing to 3 interval said P type post 5-2 of outermost end, the stepping of 5-3 near 3 districts in 2 districts; Total impurities amount among said P type post 5-2, the 5-3 also can change with ratio with the N total impurities of the said N type post of even depth; And the mode that promptly proportionally diminishes from said electric current flow region toward the direction in said channel cutoff district from the inside to surface changes adjustment, and for example: at the ratio of the inside is 1～1.35, can be 1～0 in outermost.65。Outermost end in 3 districts has said channel cutoff ring 21; Said channel cutoff ring 21 adds metal formed thereon again by N+ injection region or N+ injection region and constitutes, and is formed with metal field plate P2 on the said in embodiments of the present invention channel cutoff ring 21, also is connected with said metal field plate P2 through contact hole 10; Thereby said channel cutoff ring 21 also can not be connected with the said metal field plate P2 on it this metal field plate P2 is suspended, this metal field plate P2 also can be provided with polysilicon field plate P1, and polysilicon field plate P1 is not set in the embodiment of the invention one.
As shown in Figure 4, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention two super junction devices.The embodiment of the invention two with the difference of embodiment one is: also be that the P2 of metal field plate described in the T1 block diagram is not connected with source electrode in 2 districts; The ledge structure of said terminal deielectric-coating 6 is positioned on the said P type ring 24, and the P2 of metal field plate described in the T1 block diagram has covered the said P type of part ring 24.Polysilicon field plate P1 described in the said T1 block diagram is come to form by outermost polysilicon gate 8 extensions of said electric current flow region, and this polysilicon field plate P1 also links to each other with said grid.The said P type post of the embodiment of the invention two is identical with the setting of said channel cutoff ring 21 and other metal field plate or polysilicon field plate and the embodiment of the invention one.
As shown in Figure 5, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention three super junction devices.The embodiment of the invention three with the difference of the embodiment of the invention two is: the P2 of metal field plate described in the T1 block diagram links to each other with said source electrode, and the part of this metal field plate P2 has covered the said P type of part ring 24.
As shown in Figure 6, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention four super junction devices.The embodiment of the invention four with the difference of the embodiment of the invention three is: the part that extends in 3 districts of the said polysilicon field plate P1 in the T1 block diagram is not connected with metal field plate P2 on it.
As shown in Figure 7, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention five super junction devices.The difference of the embodiment of the invention four and the embodiment of the invention three is: have a degree of depth that is arranged in the degree of depth of the outermost said P type post 5-3 in 3 districts less than the said P type post 5-1 in said 2 districts at least.
As shown in Figure 8, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention six super junction devices.The difference of the embodiment of the invention six and the embodiment of the invention one is: said p type island region territory 25 and said P type post 5-1,5-2,5-3 form behind groove 4,4-1,4-2 and the 4-3 in said groove 4,4-1,4-2 and 4-3, to fill P type silicon and form in said N type epitaxial loayer 2 again; Inject p type impurity but adopt repeated technology extension on N+ silicon chip 1 to form multilayer N type silicon and form the back at selection area at each layer N type silicon; Form said N type silicon epitaxy layer 2 together by each layer N type silicon, form said P type post 5-1 and said P type post 5-2, the 5-3 in 3 districts in 25,2 districts, said p type island region territory in 1 district together respectively by the p type impurity of the same area of each layer.
As shown in Figure 9, be the sectional view along AA ' among Fig. 1 of the terminal protection structure of the embodiment of the invention seven super junction devices.The difference of the embodiment of the invention seven and the embodiment of the invention six is: have a degree of depth that is arranged in the degree of depth of the outermost said P type post 5-3 in 3 districts less than the said P type post 5-1 in said 2 districts at least.
For the device like the various structures of Fig. 3～shown in Figure 9, when the puncture voltage of device required greater than 600V, the thickness of wherein said N type silicon epitaxy layer 2 was 40 microns～60 microns, and the degree of depth in p type island region territory 25 described in 1 district is 35 microns～50 microns; Thickness 800 dusts～1200 dusts of grid oxygen 7, the thickness of polysilicon 8 are 3000 dusts～0000 dust, and the thickness of said terminal deielectric-coating 6 is 5000 dusts～15000 dusts, and the thickness of said interlayer film 9 is 5000 dusts～15000 dusts.
Like Fig. 3～shown in Figure 7, the manufacturing approach of the terminal protection structure of the embodiment of the invention one said super junction device comprises the steps:
Step 1, on a N+ silicon chip 1, form N type silicon epitaxy layer 2, on said N type silicon epitaxy layer 2, form the P type back of the body grid 3 of electric current flow region and the P type ring 24 in terminal protection structure zone.
Step 2, utilize chemical wet etching promptly to form groove 4 and i.e. 2 districts and 3 districts formation groove 4-1,4-2 and 4-3 in 1 district in said terminal protection structure zone at said electric current flow region.The degree of depth of said groove 4,4-1,4-2 and 4-3 arrives on the N+ silicon chip 1 or only is retained in said N type silicon epitaxy layer 2.The degree of depth of said groove 4-1,4-2 and the 4-3 in 2 districts and 3 districts is less than the degree of depth of the said groove 4 in 1 district.
For like Fig. 3～when all equating, can adopt the direction of Twi-lithography and etching to form the said groove 4 of different depth and said groove 4-1,4-2 and the 4-3 in 2 districts and 3 districts respectively like said groove 4-1,4-2 and 4-3 between Fig. 6; Also can utilize the micro loading effect of etching to realize the formation of the groove of 1 district and 2,3 interval different depths; For example: to 5 microns wide grooves 4 in 1 district; When its degree of depth reaches 45 microns, 2 microns wide groove 4-1,4-2 and 4-3 in 2 and 3 districts, its degree of depth is only had an appointment 25 microns; Through adopting the width groove different with 3 districts, just can obtain the groove structure of different depth like this with 1 district in 2 districts.
During less than the said groove 4-1 of 2 districts and inboard, 3 districts, 4-2, can adopt third photo etching and etching to come to realize respectively for the said groove 4-3 in the outside, 3 districts as shown in Figure 7; Also can utilize the micro loading effect of etching to realize, for example to 5 microns wide grooves 4 in 1 district, when its degree of depth reaches 45 microns; The groove 4-1 and the 4-2 of other 2 microns wide of employings in 2 and 3 districts; Its degree of depth is only had an appointment 25 microns, adopts the groove 4-3 of 1 micron of one group of width in 3 district's outermost end, and its degree of depth is only had an appointment 10 microns; Through adopting two kinds of grooves that width is different with 1 sector width with 3 districts, just can obtain the groove structure of three kinds of different depths like this in 2 districts.
Step 3, in said groove 4,4-1,4-2 and 4-3, form P type silicon and the silicon on said N type epitaxial loayer 2 surfaces are removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post.
Thereby step 4, deposition dielectric film also utilize chemical wet etching that the film in 1 district is removed the deielectric-coating 6 at formation terminal, said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating 6 has a ledge structure.
Step 5, on said N+ silicon chip 1, form grid oxygen 7 and polysilicon 8; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon 8 at said electric current flow region; Form at least one polysilicon field plate P1 in said terminal protection structure zone, said polysilicon field plate P1 covers the said terminal of said ledge structure and cover part deielectric-coating 6 fully.
Step 6, utilize photoetching and ion implantation technology to form source region 11 and channel cutoff ring 21.
Film 9 between step 7, deposit cambium layer.
Step 8, carry out chemical wet etching and form contact hole 10.
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid 3 of formation and subsequent metal layer 13 of carrying out.
Step 10, at said N+ silicon chip 1 surface deposition metal level 13; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plate P2; Each said metal field plate P2 lays respectively on the said P type ring 24 or said P type post 23 is on the said interlayer film 9 on said P type post 5-1,5-2 and the 5-3, and one of them said metal field plate P2 is that the said metal field plate P2 in the T1 block diagram is covered on the said ledge structure fully.
Step 11, said N+ silicon chip 1 is carried out thinning back side.
Step 12, growth metal layer on back 14 and formation drain electrode at said N+ silicon chip 1 back side.
The manufacturing approach of the terminal protection structure of the embodiment of the invention two said super junction devices and the difference of the embodiment of the invention one are: the step that forms said P type back of the body grid 3 and said P type ring 24 is not to be placed in the step 1 promptly in the step before forming said groove, is in the next step of the step 4 in the embodiment of the invention one but be placed in the next procedure that forms said terminal deielectric-coating 6.
The manufacturing approach of the terminal protection structure of the embodiment of the invention three said super junction devices and the difference of the embodiment of the invention one are: in step 1, promptly kept the step that forms said P type ring 24 in the step before forming said groove; And the step that will form said P type back of the body grid 3 to be placed in the next procedure that forms said terminal deielectric-coating 6 be in the next step of the step 4 in the embodiment of the invention one.
The manufacturing approach of the terminal protection structure of the embodiment of the invention four said super junction devices and the difference of the embodiment of the invention one are: in step 1, promptly kept the step that forms said P type ring 24 in the step before forming said groove; And the step that will form said P type back of the body grid 3 to be placed in the next procedure that forms said gate patterns and said polysilicon field plate P2 be in the next step of the step 5 in the embodiment of the invention one.
Like Fig. 8 and shown in Figure 9, the manufacturing approach of the terminal protection structure of the embodiment of the invention five said super junction devices comprises the steps:
Step 1, on a N+ silicon chip 1 epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching.
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer 2 formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post 23 in p type island region territory 25 with the terminal protection structure zone of electric current flow region, and said P type post 23 comprises the P type post 5-2 and the 5-3 in the P type post 5-1 that is formed at 2 districts, the inboard that is formed at 3 districts and the outside; Thereby form the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region.
As shown in Figure 8; The 6 layers of said N type silicon of having grown altogether; The degree of depth according to the P type post 5-2 in the P type post 5-1 in 25,2 districts, the zone of the said type in 1 district and 3 districts and 5-3 is different; The graphical layout of the mask of the p type impurity injection zone after the said N type of each layer silicon forms is also different, regulates the degree of depth of said type zone 25 and each said P type post 23 through the injection number of times of regulating p type impurity.Wherein, all carry out p type impurity at formation 25 places, said p type island region territory in 6 layers of said N type silicon in 1 district and inject, inject for totally 6 times; In 2 districts and 3 districts, in back 4 layers of said N type silicon, all carry out p type impurity and inject, inject for totally 4 times at the said P type post of formation 23 places.So the degree of depth of formed each said P type post 23 is all identical and all less than the degree of depth in said p type island region territory 25.
As shown in Figure 9, four said P type post 5-3 in the outside, 3 districts only carry out p type impurity at the said P type post 5-3 of formation place and inject in back 2 layers of said N type silicon, inject for totally 2 times.So the degree of depth of formed said P type post 5-3 is all less than the degree of depth of said P type post 5-1 and 5-2.
Step 3, carry out formation P type back of the body grid 3 and said terminal protection structure zone that photoetching and ion be infused in the said electric current flow region on the said N type silicon epitaxy layer and form P type ring 24.
Thereby step 4, deposition dielectric film also utilize chemical wet etching that the film in 1 district is removed the deielectric-coating 6 at formation terminal, said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating 6 has a ledge structure.
Step 5, on said N+ silicon chip 1, form grid oxygen 7 and polysilicon 8; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon 8 at said electric current flow region; Form at least one polysilicon field plate P1 in said terminal protection structure zone, said polysilicon field plate P1 covers the said terminal of said ledge structure and cover part deielectric-coating 6 fully.
Step 6, utilize photoetching and ion implantation technology to form source region 11 and channel cutoff ring 21.
Film 9 between step 7, deposit cambium layer.
Step 8, carry out chemical wet etching and form contact hole 10.
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid 3 of formation and subsequent metal layer 13 of carrying out.
Step 10, at said N+ silicon chip 1 surface deposition metal level 13; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plate P2; Each said metal field plate P2 lays respectively on the said P type ring 24 or on the said interlayer film 9 on said P type post 5-1,5-2 and the 5-3, one of them said metal field plate P2 is covered on the said ledge structure fully.
Step 11, said N+ silicon chip 1 is carried out thinning back side.
Step 12, growth metal layer on back 14 formation drain electrodes at said N+ silicon chip 1 back side.
The manufacturing approach of the terminal protection structure of the embodiment of the invention six said super junction devices and the difference of the embodiment of the invention five are: the step that forms P type back of the body grid 3 and said P type ring 24 in the step 3 of the embodiment of the invention five simultaneously is separated into two steps, and two steps after separating are: carry out photoetching earlier, ion injects and push away trap forming P type ring 24 in said terminal protection structure zone; And then next step carries out the formation P type back of the body grid that photoetching, ion are infused in said electric current flow region again.
The manufacturing approach of the terminal protection structure of the embodiment of the invention seven said super junction devices and the difference of the embodiment of the invention five are: the step that forms P type back of the body grid 3 and said P type ring 24 in the step 3 of the embodiment of the invention five simultaneously is separated into two steps, and two steps after separating are: carry out photoetching earlier, ion injects and push away trap forming P type ring 24 in said terminal protection structure zone; To carry out again photoetching, ion inject and push away trap the step of the formation P of said electric current flow region type back of the body grid be placed on the step that forms said gate patterns and said polysilicon field plate P1 be the embodiment of the invention five step 5 after one go on foot.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims (25)

1. the terminal protection structure of a super junction device; On a N+ silicon chip, be formed with a N type epitaxial loayer; The zone line of super junction device is the electric current flow region; Said electric current flow region comprises the p type island region territory and N type zone in the said N type epitaxial loayer that be formed at of alternately arranging, and P type back of the body grid are formed at each top, said p type island region territory or said P type back of the body grid and are formed at each top, said p type island region territory and extend in the said N type zone of each both sides, top, said p type island region territory, and a source region is formed at each said P type and carries on the back in grid; Said N type epitaxial loayer top at said electric current flow region is formed with grid oxygen, grid and source electrode, is formed with drain electrode at the back side of said N+ silicon chip; It is characterized in that:
The terminal protection structure of said super junction device is surrounded on the periphery of said electric current flow region and comprises at least one P type ring, a plurality of P type post, a channel cutoff ring, a terminal deielectric-coating, at least one polysilicon field plate and a plurality of metal field plate; Said P type ring, said P type post and said channel cutoff ring be structure and by the interior periphery that is surrounded on said electric current flow region outward successively in the form of a ring all;
Each said P type cylindricality is formed in the regional said N type epitaxial loayer of said terminal protection structure and each said P type post is arranged in order outermost p type island region territory and said channel cutoff interannular in said electric current flow region, and the N type epitaxial loayer of each said P type post and each said P type intercolumniation is formed P type post and N type post alternative expression structure;
Said P type annular is formed in the superficial layer of said N type silicon epitaxy layer in said terminal protection structure zone and is adjacent with said outermost p type island region territory;
Said channel cutoff annular is formed in the superficial layer of the said N type epitaxial loayer outside the outermost P type post;
Said terminal deielectric-coating is formed on the said N type silicon epitaxy layer in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure, and said terminal deielectric-coating has covered the P type post of said ledge structure bottom all said P type posts to said outermost P type intercolumniation;
Said polysilicon field plate is formed on the deielectric-coating of said terminal, and said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
One interlayer film is formed on said N type epitaxial loayer, said terminal deielectric-coating and the said polysilicon field plate in said terminal protection structure zone; Said a plurality of metal field plate is formed on the said interlayer film, and each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully.
2. the terminal protection structure of super junction device according to claim 1 is characterized in that: the depth as shallow in the p type island region territory of the said electric current flow region of depth ratio of at least one said P type post.
3. the terminal protection structure of super junction device according to claim 1, it is characterized in that: the width ratio of the width of at least one group of said P type post and said N type post is greater than the width in the said p type island region territory of said electric current flow region and the width ratio in said N type zone.
4. the terminal protection structure of super junction device according to claim 1 is characterized in that: the width along said electric current flow region toward the said P type of said channel cutoff ring direction post is identical with the width ratio of said N type post or successively decrease.
5. the terminal protection structure of super junction device according to claim 1 is characterized in that: the degree of depth along said electric current flow region toward the said P type of said channel cutoff ring direction post is identical or successively decrease.
6. the terminal protection structure of super junction device according to claim 1, it is characterized in that: said P type ring outermost p type island region territory from said electric current flow region covers at least one said P type post and a said N type post outward.
7. the terminal protection structure of super junction device according to claim 1, it is characterized in that: the impurity concentration of said P type ring is greater than the impurity concentration of said P type post.
8. the terminal protection structure of super junction device according to claim 1, it is characterized in that: the impurity process conditions of said P type ring are identical with the impurity process conditions of said P type back of the body grid.
9. the terminal protection structure of super junction device according to claim 1 is characterized in that: be positioned at said metal field plate on the said interlayer film on the said P type ring and have at least a part all to cover or part covers said P type ring.
10. the terminal protection structure of super junction device according to claim 1 is characterized in that: be positioned at said metal field plate on the said interlayer film on the said P type ring and link to each other with said source electrode or be suspended on the said interlayer film.
11. the terminal protection structure of super junction device according to claim 1, it is characterized in that: said polysilicon field plate links to each other with said grid or is suspended on the deielectric-coating of said terminal.
12. the terminal protection structure of super junction device according to claim 1 is characterized in that: said polysilicon field plate and position are on it and be positioned at that said metal field plate that the said ledge structure outside and the said source electrode of getting along well link to each other links to each other or continuous.
13. the terminal protection structure of super junction device according to claim 1 is characterized in that: the inclination angle of said ledge structure is 10 degree～75 degree.
14. the terminal protection structure of super junction device according to claim 1; It is characterized in that: on said channel cutoff ring, be coated with said metal field plate or said polysilicon field plate, be covered in said metal field plate or said polysilicon field plate on the said channel cutoff ring and be connected with said channel cutoff ring or suspend.
15. the terminal protection structure of super junction device according to claim 1; It is characterized in that: covering the said polysilicon field plate that suspends on the said channel cutoff ring and on said polysilicon field plate, be coated with the metal field plate, said metal field plate links to each other with said polysilicon field plate or suspends.
16. the terminal protection structure of super junction device according to claim 1 is characterized in that: in the circulus of the above P type post of top plan view is that the circulus of square or said P type post is tetragonal four jiaos of structures that circular arc is arranged.
17. the terminal protection structure of super junction device according to claim 1 is characterized in that: the quadrangle in the circulus of said P type post becomes to have additional P type post.
18. the terminal protection structure like the said super junction device of claim 17 is characterized in that: said additional P type post links to each other with said P type post or separates.
19. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, on said N type silicon epitaxy layer, form the P type back of the body grid of electric current flow region and the P type ring in terminal protection structure zone;
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in said electric current flow region and said terminal protection structure zone, to form groove;
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 7, deposit cambium layer;
Step 8, carry out chemical wet etching and form contact hole;
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 11, said N+ silicon chip is carried out thinning back side;
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
20. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize chemical wet etching on the regional said N type epitaxial loayer of electric current flow region and terminal protection structure, to form groove;
Step 2, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post;
Step 3, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 4, the P type back of the body grid that on said N type silicon epitaxy layer, form the electric current flow region and the regional P type ring of terminal protection structure;
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 7, deposit cambium layer;
Step 8, carry out chemical wet etching and form contact hole;
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 11, said N+ silicon chip is carried out thinning back side;
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
21. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize photoetching and ion to be infused in terminal protection structure zone formation P type ring;
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in electric current flow region and terminal protection structure zone, to form groove;
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 5, the electric current flow region on said N type silicon epitaxy layer form P type back of the body grid;
Step 6, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 8, deposit cambium layer;
Step 9, carry out chemical wet etching and form contact hole;
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 12, said N+ silicon chip is carried out thinning back side;
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
22. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip, form N type silicon epitaxy layer, utilize photoetching and ion to be infused in terminal protection structure zone formation P type ring;
Step 2, utilize chemical wet etching on the said N type epitaxial loayer in electric current flow region and terminal protection structure zone, to form groove;
Step 3, in said groove, form P type silicon and the silicon of said N type epi-layer surface is removed, thereby in said electric current flow region, form the said p type island region territory of alternately arranging forms alternately arrangement with N type zone, in said terminal protection structure zone said P type post and said N type post;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 6, utilize ion to inject and push away the electric current flow region of trap technology on said N type silicon epitaxy layer and form P type back of the body grid;
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 8, deposit cambium layer;
Step 9, carry out chemical wet etching and form contact hole;
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 12, said N+ silicon chip is carried out thinning back side;
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
23. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching;
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region;
Step 3, carry out formation P type back of the body grid and said terminal protection structure zone that photoetching and ion be infused in the said electric current flow region on the said N type silicon epitaxy layer and form P type ring;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 6, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 7, deposit cambium layer;
Step 8, carry out chemical wet etching and form contact hole;
Step 9, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 10, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 11, said N+ silicon chip is carried out thinning back side;
Step 12, metallizing at the said N+ silicon chip back side forms drain electrode.
24. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching;
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region;
Step 3, carry out photoetching, ion and inject and push away trap and form P type ring in said terminal protection structure zone;
Step 4, carry out the formation P type back of the body grid that photoetching and ion are infused in said electric current flow region;
Step 5, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 6, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 8, deposit cambium layer;
Step 9, carry out chemical wet etching and form contact hole;
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 12, said N+ silicon chip is carried out thinning back side;
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
25. the manufacturing approach of the terminal protection structure of super junction device according to claim 1 is characterized in that, comprises the steps:
Step 1, on a N+ silicon chip epitaxial growth one deck N type silicon, define the injection zone of p type impurity and inject p type impurity in said N type silicon through photoetching;
The technology of step 2, repeating step 1 5～7 times; Obtain the N type silicon epitaxy layer formed by multilayer N type silicon; The p type impurity that is formed at the same area in each layer N type silicon is formed the P type post in the p type island region territory and the terminal protection structure zone of electric current flow region, thereby forms the said p type island region territory and the N type zone of alternately arranging and in the terminal protection structure zone, form said P type post and the said N type post of alternately arranging at said electric current flow region;
Step 3, carry out photoetching, ion and inject and push away trap and form P type ring in said terminal protection structure zone;
Step 4, deposition dielectric film also utilize chemical wet etching to form the terminal deielectric-coating in said terminal protection structure zone; Side near said electric current flow region of said terminal deielectric-coating has a ledge structure;
Step 5, on said N+ silicon chip, form grid oxygen and polysilicon; Utilize chemical wet etching to form the gate patterns of forming by said polysilicon at said electric current flow region; Form at least one polysilicon field plate in said terminal protection structure zone, said polysilicon field plate covers the said terminal of said ledge structure and cover part deielectric-coating fully;
Step 6, carry out photoetching, ion and inject and push away trap at the formation P of said electric current flow region type back of the body grid;
Step 7, utilize photoetching and ion implantation technology to form source region and channel cutoff ring;
Film between step 8, deposit cambium layer;
Step 9, carry out chemical wet etching and form contact hole;
Step 10, the ohmic contact that the P+ ion injects said P type back of the body grid of formation and subsequent metal layer of carrying out;
Step 11, at said N+ silicon chip surface deposition metal level; And carry out chemical wet etching and form the electrode pattern of said source electrode and said grid and form a plurality of metal field plates; Each said metal field plate lays respectively on the said P type ring or on the said interlayer film on the said P type post, one of them said metal field plate is covered on the said ledge structure fully;
Step 12, said N+ silicon chip is carried out thinning back side;
Step 13, metallizing at the said N+ silicon chip back side forms drain electrode.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576740A (en) * 2013-10-28 2015-04-29 美格纳半导体有限公司 Semiconductor device
CN108735801A (en) * 2018-05-29 2018-11-02 电子科技大学 A kind of superjunction power DMOS device
CN112002643A (en) * 2020-08-21 2020-11-27 上海华虹宏力半导体制造有限公司 Method for manufacturing super junction device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020195627A1 (en) * 2001-06-26 2002-12-26 International Rectifier Corp. Lateral superjunction semiconductor device
US20040065934A1 (en) * 2002-08-27 2004-04-08 International Rectifier Corp. Bidirectional shallow trench superjunction device with resurf region
CN1790714A (en) * 2004-12-13 2006-06-21 株式会社电装 Semiconductor device and method of manufacturing the same
WO2008136874A1 (en) * 2007-05-04 2008-11-13 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
CN101465370A (en) * 2007-12-17 2009-06-24 株式会社电装 Halbleitervorrichtung mit super junction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020195627A1 (en) * 2001-06-26 2002-12-26 International Rectifier Corp. Lateral superjunction semiconductor device
US20040065934A1 (en) * 2002-08-27 2004-04-08 International Rectifier Corp. Bidirectional shallow trench superjunction device with resurf region
CN1790714A (en) * 2004-12-13 2006-06-21 株式会社电装 Semiconductor device and method of manufacturing the same
WO2008136874A1 (en) * 2007-05-04 2008-11-13 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
CN101465370A (en) * 2007-12-17 2009-06-24 株式会社电装 Halbleitervorrichtung mit super junction

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576740A (en) * 2013-10-28 2015-04-29 美格纳半导体有限公司 Semiconductor device
CN108735801A (en) * 2018-05-29 2018-11-02 电子科技大学 A kind of superjunction power DMOS device
CN112002643A (en) * 2020-08-21 2020-11-27 上海华虹宏力半导体制造有限公司 Method for manufacturing super junction device
CN112002643B (en) * 2020-08-21 2023-08-22 上海华虹宏力半导体制造有限公司 Method for manufacturing super junction device

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