CN112993008A - Charge balance device and method of manufacturing the same - Google Patents
Charge balance device and method of manufacturing the same Download PDFInfo
- Publication number
- CN112993008A CN112993008A CN201911280574.8A CN201911280574A CN112993008A CN 112993008 A CN112993008 A CN 112993008A CN 201911280574 A CN201911280574 A CN 201911280574A CN 112993008 A CN112993008 A CN 112993008A
- Authority
- CN
- China
- Prior art keywords
- charge balance
- layer
- region
- epitaxial layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 41
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 27
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000008569 process Effects 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 317
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 229910002601 GaN Inorganic materials 0.000 claims description 11
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 11
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 11
- 229910003460 diamond Inorganic materials 0.000 claims description 11
- 239000010432 diamond Substances 0.000 claims description 11
- 229910052580 B4C Inorganic materials 0.000 claims description 9
- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 10
- 230000006872 improvement Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 229910001195 gallium oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention discloses a charge balance device.A drift region comprises more than one charge balance layer; the type of the conductive carrier of the drift region is a first conductivity type; the charge balance layer includes: a first epitaxial layer of a first conductivity type and a plurality of first doped regions of a second conductivity type doping formed in selected regions of the first epitaxial layer; the junction depth of each first doping region is smaller than the thickness of the first epitaxial layer, and a space is reserved between the first doping regions; the first epitaxial layer and each first doped region in the charge balance layer are charge balanced, and the first epitaxial layer and each first doped region in the charge balance layer are fully depleted when the drift region is subjected to a reverse bias. The invention discloses a manufacturing method of a charge balance device. The invention can reduce the specific on-resistance, the turn-on energy loss and the switch dynamic loss of the device, can be well suitable for devices formed by semiconductor materials with impurities which are not easy to diffuse, such as silicon carbide and the like, and has the advantages of easier realization of the process and lower cost.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a charge balance device; the invention also relates to a method for manufacturing the charge balance device.
Background
In semiconductor technology, charge balance structures or super junction designs can bring significant improvements in performance to semiconductor devices. In a general sense, the design of the charge balance structure can effectively reduce the resistance of the drift region, thereby reducing the conduction energy loss of the semiconductor device per unit area. In a conventional silicon-based charge balance device or super junction device, a structure in which two vertical conductive pillars having different conductive types are alternated can be formed by means of ion implantation and diffusion processes. However, in the wide bandgap semiconductor silicon carbide, the impurity ions have too low a diffusion rate and an ion implantation range. Therefore, under similar conditions, impurity ions cannot reach the depth that can be achieved in the silicon process by using ion implantation in the silicon carbide epitaxial layer. Therefore, in silicon carbide-based semiconductor devices, higher process conditions, such as higher ion implantation energy or annealing temperature, need to be applied.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a charge balance device, which can reduce the specific on-resistance, the turn-on energy loss and the switching dynamic loss of the device, can be well suitable for devices formed by semiconductor materials with impurities such as silicon carbide and the like which are not easy to diffuse, and has compatible forming process with the existing semiconductor manufacturing equipment such as ion implantation equipment, thereby enabling the process to be easier to realize and the cost to be lower. Therefore, the invention also provides a manufacturing method of the charge balance device.
In order to solve the above technical problems, the drift region of the charge balance device provided by the invention comprises more than one charge balance layer; the drift region has a first conductivity type of a conductive carrier.
The charge balance layer includes: a first epitaxial layer of a first conductivity type and a plurality of first doped regions of a second conductivity type doping formed in selected regions of the first epitaxial layer; each first doping region extends from the surface of the first epitaxial layer to the inside of the first epitaxial layer, the junction depth of each first doping region is smaller than the thickness of the first epitaxial layer, and a space is reserved between the first doping regions.
The first epitaxial layer and each of the first doped regions in the charge balance layer are charge balanced, and the first epitaxial layer and each of the first doped regions in the charge balance layer are fully depleted from each other when the drift region is reverse biased.
In a further improvement, the bottom most layer of the charge balance layer is formed on a semiconductor substrate of the first conductivity type.
In a further improvement, the semiconductor substrate comprises the following materials: silicon carbide, silicon, gallium nitride, diamond, aluminum nitride, boron carbide.
In a further improvement, the charge balance device is a charge balance schottky diode, further comprising:
and the cathode is formed on the back surface of the semiconductor substrate and consists of a back metal layer.
And a second epitaxial layer of the first conduction type is formed on the surface of the charge balance layer at the topmost layer.
A plurality of second doped regions of a second conductivity type dopant formed in selected regions of said second epitaxial layer; each second doped region extends from the surface of the second epitaxial layer to the inside of the second epitaxial layer, the junction depth of each second doped region is smaller than the thickness of the second epitaxial layer, and a space is formed between the second doped regions.
A Schottky metal layer is formed on the surface of the second epitaxial layer on which the second doped region is formed; and Schottky contact is formed on the surfaces of the Schottky metal layer and the second epitaxial layer, and ohmic contact is formed between the Schottky metal layer and the second doped region.
And an anode consisting of a front metal layer is formed on the surface of the Schottky metal layer.
In a further improvement, the charge balance device is a charge balance field effect transistor comprising:
and a second epitaxial layer of the first conductivity type is formed on the surface of the charge balance layer at the topmost layer, and the second epitaxial layer is used as a component of the drift region.
And forming a base region doped with a second conductive type in the second epitaxial layer.
The gate structure comprises a gate oxide layer and a polysilicon gate.
The source region is formed in the base region.
The surface of the base region covered by the gate structure is used to form a channel connecting the source region and the drift region.
The top of the source region is connected to a source electrode consisting of a front metal layer through a contact hole; the contact hole at the bottom of the source electrode also penetrates through the source region and the base region to be contacted.
And forming a drain region by the semiconductor substrate.
And the drain electrode is formed by a back metal layer formed on the back of the drain region.
The gate structure is a planar gate, the gate structure covers the surface of the base region and extends to the surface of the drift region outside the base region, and the surface of the base region covered by the front surface of the gate structure is used for forming the channel.
Or, the grid structure is a trench grid, the grid oxide layer is formed on the bottom surface and the side surface of the grid groove, the polysilicon grid is filled in the grid groove, the grid groove penetrates through the base region, and the surface of the base region covered by the side surface of the polysilicon grid is used for forming the channel.
In a further improvement, the first doped region is an ion implanted region.
The further improvement is that the charge balance device is of an N type, the first conductivity type is of an N type, and the second conductivity type is of a P type; or the charge balance device is of a P type, the first conduction type is of a P type, and the second conduction type is of an N type.
In order to solve the above technical problem, in the manufacturing method of the charge balance device provided by the present invention, the drift region of the charge balance device includes more than one charge balance layer; the type of the conductive carrier of the drift region is a first conductivity type; the method comprises the following steps:
step one, forming a first epitaxial layer of a first conductivity type by adopting an epitaxial growth process.
Step two, a plurality of first doping regions doped with the second conductivity type are formed in the selected region of the first epitaxial layer by adopting a photoetching definition and ion implantation process; the charge balance layer is composed of each first doping region and the first epitaxial layer.
Each first doping region extends from the surface of the first epitaxial layer to the inside of the first epitaxial layer, the junction depth of each first doping region is smaller than the thickness of the first epitaxial layer, and a space is reserved between the first doping regions.
The first epitaxial layer and each of the first doped regions in the charge balance layer are charge balanced, and the first epitaxial layer and each of the first doped regions in the charge balance layer are fully depleted from each other when the drift region is reverse biased.
Repeating steps one and two to form all the charge balance layers needed in the drift region.
In a further improvement, the bottom most layer of the charge balance layer is formed on a semiconductor substrate of the first conductivity type.
In a further improvement, the semiconductor substrate comprises the following materials: silicon carbide, silicon, gallium nitride, diamond, aluminum nitride, boron carbide.
In a further improvement, the charge balance device is a charge balance schottky diode, further comprising the steps of:
and step three, forming a second epitaxial layer of the first conduction type on the surface of the charge balance layer at the topmost layer.
Step four, a plurality of second doping regions doped with the second conductivity type are formed in the selected region of the second epitaxial layer by adopting a photoetching definition and ion implantation process; each second doped region extends from the surface of the second epitaxial layer to the inside of the second epitaxial layer, the junction depth of each second doped region is smaller than the thickness of the second epitaxial layer, and a space is formed between the second doped regions.
Fifthly, forming a Schottky metal layer on the surface of the second epitaxial layer on which the second doped region is formed; and Schottky contact is formed on the surfaces of the Schottky metal layer and the second epitaxial layer, and ohmic contact is formed between the Schottky metal layer and the second doped region.
And sixthly, forming a front metal layer on the surface of the Schottky metal layer, and forming an anode by using the front metal layer.
And seventhly, forming a back metal layer on the back of the semiconductor substrate, wherein the back metal layer forms a cathode.
In a further improvement, the charge balance device is a charge balance field effect transistor, further comprising the steps of:
and thirdly, forming a second epitaxial layer of the first conduction type on the surface of the charge balance layer at the topmost layer, wherein the second epitaxial layer is used as a component of the drift region.
And fourthly, forming a base region doped with the second conduction type in the second epitaxial layer.
And step five, forming a source region in the base region.
Sixthly, forming a grid structure, wherein the grid structure comprises a stacked structure of a grid oxide layer and a polysilicon grid; the surface of the base region covered by the gate structure is used to form a channel connecting the source region and the drift region.
Forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode; the top of the source region is connected to a source electrode consisting of a front metal layer through a contact hole; the contact hole at the bottom of the source electrode also penetrates through the source region and the base region to be contacted.
Step eight, forming a drain region by the semiconductor substrate; and forming a back metal layer on the back of the drain region, wherein the back metal layer forms a drain electrode.
The gate structure is a planar gate, the gate structure covers the surface of the base region and extends to the surface of the drift region outside the base region, and the surface of the base region covered by the front surface of the gate structure is used for forming the channel.
Or, the grid structure is a trench grid, the grid oxide layer is formed on the bottom surface and the side surface of the grid groove, the polysilicon grid is filled in the grid groove, the grid groove penetrates through the base region, and the surface of the base region covered by the side surface of the polysilicon grid is used for forming the channel.
The further improvement is that the charge balance device is of an N type, the first conductivity type is of an N type, and the second conductivity type is of a P type; or the charge balance device is of a P type, the first conduction type is of a P type, and the second conduction type is of an N type.
The invention has the advantages that the drift region adopts more than one layer of charge balance layer structure, which is different from the prior art that the charge balance structure adopts a super junction structure, namely a structure formed by alternately arranging P-type columns and N-type columns, the charge balance layer adopts a first epitaxial layer of a first conduction type to form a plurality of first doping regions with junction depth smaller than that of the first epitaxial layer, the first doping regions ensure to realize charge balance with the first epitaxial layer, the design of the drift region with the charge balance layer can improve the doping concentration of the drift region to ensure that the device performance breaks the one-dimensional limit of the traditional device, and the drift region has smaller specific on-resistance and on-state energy consumption than the prior device under the same breakdown voltage, namely: the charge balance layer can realize depletion in reverse bias of the drift region, thereby improving the breakdown voltage of the device, or reducing the specific on-resistance, the turn-on energy loss and the dynamic loss of the switch of the device under the condition of keeping the withstand voltage of the device unchanged.
In addition, the arrangement that the junction depth of the first doping region of the charge balance layer is smaller than that of the first epitaxial layer enables the first doping region to realize charge balance between the first doping region and the first epitaxial layer under the condition that the first doping region does not longitudinally penetrate through the first epitaxial layer, so that the difficulty of the formation process of the first doping region can be reduced, and the charge balance device is particularly useful in devices formed by semiconductor materials with impurities which are not easy to diffuse, for example, in a silicon carbide-based power device, because the existing silicon carbide-based power device cannot form a super junction structure or other charge balance structures due to the limitation of impurity diffusion, the specific on-resistance of the existing silicon carbide-based power device is not easy to reduce; the charge balance structure of the invention can still form a charge balance layer in the drift region of the silicon carbide-based power device because the requirement on the junction depth of the first doping region is reduced, thereby improving the performance of the semiconductor material power device which is similar to silicon carbide and has difficult diffusion of impurities; in addition to silicon carbide semiconductor materials, the present invention can also be applied to power devices including a series of semiconductor materials such as silicon, gallium nitride, diamond, aluminum nitride, gallium oxide, and the like.
In addition, the forming process of the first epitaxial layer and the first doping region of the charge balance layer is compatible with the existing semiconductor manufacturing equipment such as ion implantation equipment, so that the process is easier to realize and the cost is lower.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural view of a charge balance device according to a first embodiment of the present invention;
fig. 2 is a schematic structural view of a charge balance device according to a second embodiment of the present invention;
FIGS. 3A-3F are schematic diagrams of device structures at various steps of a method for fabricating a charge balance device according to a first embodiment of the present invention;
fig. 4A to 4I are schematic views of device structures in steps of a method for manufacturing a charge balance device according to a second embodiment of the present invention.
Detailed Description
Referring to fig. 1, a charge balance structure according to an embodiment of the present invention includes a drift region of a charge balance device including at least one charge balance layer 2; the drift region has a first conductivity type of a conductive carrier.
The charge balance layer 2 includes: a first epitaxial layer 3 of a first conductivity type and a plurality of first doped regions 4 of a second conductivity type doping formed in selected regions of said first epitaxial layer 3; each first doping region 4 extends from the surface of the first epitaxial layer 3 to the inside of the first epitaxial layer 3, the junction depth of each first doping region 4 is smaller than the thickness of the first epitaxial layer 3, and a space is formed between each first doping region 4.
The first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are charge balanced, and the first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are fully depleted from each other when the drift region is reverse biased.
The lowermost charge balance layer 2 is formed on a semiconductor substrate 1 of the first conductivity type.
The material of the semiconductor substrate 1 is silicon carbide. In other embodiments can also be: the semiconductor substrate 1 is made of silicon, gallium nitride, diamond, aluminum nitride and boron carbide.
In the embodiment of the invention, the drift region adopts more than one layer of charge balance layer 2 structure, which is different from the prior art that the charge balance structure adopts a super junction structure, namely a structure formed by alternately arranging P-type columns and N-type columns, the charge balance layer 2 of the embodiment of the invention adopts a first epitaxial layer 3 of a first conduction type to form a plurality of first doping regions 4 with junction depth smaller than that of the first epitaxial layer 3, the first doping regions 4 ensure to realize charge balance with the first epitaxial layer 3, the design of the drift region with the charge balance layer 2 can improve the doping concentration of the drift region to lead the device performance to break through the one-dimensional limitation of the traditional device, and the device has smaller specific on-resistance and on-state energy consumption than the prior device under the same breakdown voltage, namely: the charge balance layer 2 of the embodiment of the invention can realize depletion in reverse bias of the drift region, thereby improving the breakdown voltage of the device, or reducing the specific on-resistance, the turn-on energy loss and the dynamic loss of the switch of the device under the condition of keeping the withstand voltage of the device unchanged.
In addition, the junction depth of the first doping region 4 of the charge balance layer 2 according to the embodiment of the present invention is smaller than that of the first epitaxial layer 3, so that the first doping region 4 can realize charge balance between the first doping region 4 and the first epitaxial layer 3 without longitudinally penetrating through the first epitaxial layer 3, which can reduce the difficulty of the formation process of the first doping region 4, and is particularly useful in devices formed by semiconductor materials in which some impurities are not easily diffused, for example, in a silicon carbide-based power device, because the existing silicon carbide-based power device cannot form a super junction structure or other charge balance structures due to the limitation of impurity diffusion, the specific on resistance of the existing silicon carbide-based power device is not easily reduced; in the charge balance structure of the embodiment of the present invention, since the requirement for the junction depth of the first doped region 4 is reduced, the charge balance layer 2 can still be formed in the drift region of the silicon carbide-based power device, so as to improve the performance of the semiconductor material power device, which is similar to silicon carbide and has impurities that are not easy to diffuse; the first embodiment of the present invention can be applied to a power device including a series of semiconductor materials of silicon, gallium nitride, diamond, aluminum nitride, gallium oxide, and the like, in addition to the silicon carbide semiconductor material.
In addition, the forming processes of the first epitaxial layer 3 and the first doped region 4 of the charge balance layer 2 according to the first embodiment of the present invention are compatible with the existing semiconductor manufacturing equipment such as ion implantation equipment, so that the processes can be realized more easily and the cost can be lower.
Fig. 1 is a schematic structural diagram of a charge balance device according to a first embodiment of the present invention; the drift region of the charge balance device of the first embodiment of the invention comprises more than one charge balance layer 2; the drift region has a first conductivity type of a conductive carrier.
The charge balance layer 2 includes: a first epitaxial layer 3 of a first conductivity type and a plurality of first doped regions 4 of a second conductivity type doping formed in selected regions of said first epitaxial layer 3; each first doping region 4 extends from the surface of the first epitaxial layer 3 to the inside of the first epitaxial layer 3, the junction depth of each first doping region 4 is smaller than the thickness of the first epitaxial layer 3, and a space is formed between each first doping region 4.
The first doped region 4 is an ion implantation region. The doping amount of the first doping region 4 should be less than 1.1x10 after normalization13cm-2So that it can be guaranteed that it can be completely exhausted.
The first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are charge balanced, and the first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are fully depleted from each other when the drift region is reverse biased.
The lowermost charge balance layer 2 is formed on a semiconductor substrate 1 of the first conductivity type.
The material of the semiconductor substrate 1 is silicon carbide. In other embodiments can also be: the semiconductor substrate 1 is made of silicon, gallium nitride, diamond, aluminum nitride and boron carbide.
In a first embodiment of the present invention, the charge balance device is a charge balance schottky diode, and further includes:
a cathode 105 composed of a back metal layer formed on the back surface of the semiconductor substrate 1.
A second epitaxial layer 101 of the first conductivity type is formed on the surface of the charge balance layer 2 at the topmost layer.
A plurality of second doped regions 102 doped with a second conductivity type formed in selected regions of the second epitaxial layer 101; each of the second doped regions 102 extends from the surface of the second epitaxial layer 101 toward the inside of the second epitaxial layer 101, the junction depth of each of the second doped regions 102 is smaller than the thickness of the second epitaxial layer 101, and a space is provided between each of the second doped regions 102.
In the first embodiment of the present invention, the implantation dose of the second doped region 102 is 1 × 1013cm-2The doping concentration of the second doping region 102 is generally 2 × 1016cm-3。
A schottky metal layer 103 is formed on the surface of the second epitaxial layer 101 on which the second doped region 102 is formed; the schottky metal layer 103 forms a schottky contact with the surface of the second epitaxial layer 101, and the schottky metal layer 103 forms an ohmic contact with the second doped region 102.
The schottky metal layer 103 may be selected from different metals to form different schottky barriers. A lower schottky barrier may lower the turn-on voltage of the diode and increase the current carrying capability of the diode, but may also increase the leakage current. The schottky metal layer 103 may be titanium (Ti), nickel (Ni), cobalt (Co), or silicide.
An anode composed of a front metal layer 104 is formed on the surface of the schottky metal layer 103.
The charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type. In other embodiments can also be: the charge balance device is of a P type, the first conductivity type is of a P type, and the second conductivity type is of an N type.
Fig. 2 is a schematic structural diagram of a charge balance device according to a second embodiment of the present invention; the drift region of the charge balance device of the second embodiment of the invention comprises more than one charge balance layer 2; the drift region has a first conductivity type of a conductive carrier.
The charge balance layer 2 includes: a first epitaxial layer 3 of a first conductivity type and a plurality of first doped regions 4 of a second conductivity type doping formed in selected regions of said first epitaxial layer 3; each first doping region 4 extends from the surface of the first epitaxial layer 3 to the inside of the first epitaxial layer 3, the junction depth of each first doping region 4 is smaller than the thickness of the first epitaxial layer 3, and a space is formed between each first doping region 4.
The first doped region 4 is an ion implantation region.
The first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are charge balanced, and the first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are fully depleted from each other when the drift region is reverse biased.
The lowermost charge balance layer 2 is formed on a semiconductor substrate 1 of the first conductivity type.
The material of the semiconductor substrate 1 is silicon carbide. In other embodiments can also be: the semiconductor substrate 1 is made of silicon, gallium nitride, diamond, aluminum nitride and boron carbide.
The charge balance device is a charge balance field effect transistor, comprising:
and a second epitaxial layer 201 of the first conductivity type formed on the surface of the topmost charge balance layer 2, wherein the second epitaxial layer 201 is used as a component of the drift region.
A base region 202 doped with a second conductivity type is formed in the second epitaxial layer 201.
A gate structure comprising a stacked structure of a gate oxide layer 204 and a polysilicon gate 205.
A source region 203 is formed in the base region 202.
The surface of the base region 202 covered by the gate structure is used to form a channel connecting the source region 203 and the drift region.
The top of the source region 203 is connected to a source electrode composed of a front metal layer 208 through a contact hole 207; the contact hole 207 at the bottom of the source electrode also penetrates through the source region 203 to be contacted with the base region 202. The contact hole 207 passes through the interlayer film 206. The thickness of the interlayer film 206 tends to exceed 1 μm.
And forming a drain region by the semiconductor substrate 1.
The drain 209 is composed of a back metal layer formed on the back surface of the drain region.
In the second embodiment of the present invention, the gate structure is a planar gate, the gate structure covers the surface of the base region 202 and extends to the surface of the drift region outside the base region 202, and the surface of the base region 202 covered by the front surface of the gate structure is used for forming the channel. In other embodiments can also be: the gate structure is a trench gate, the gate oxide layer 204 is formed on the bottom surface and the side surface of the gate trench, the polysilicon gate 205 is filled in the gate trench, the gate trench penetrates through the base region 202, and the surface of the base region 202 covered by the side surface of the polysilicon gate 205 is used for forming the channel.
The charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type. In other embodiments can also be: the charge balance device is of a P type, the first conductivity type is of a P type, and the second conductivity type is of an N type.
Fig. 3A to 3F are schematic diagrams of device structures in steps of a method for manufacturing a charge balance device according to a first embodiment of the present invention; in the method for manufacturing a charge balance device according to the first embodiment of the present invention, the drift region of the charge balance device includes more than one charge balance layer 2; the type of the conductive carrier of the drift region is a first conductivity type; the method comprises the following steps:
step one, as shown in fig. 3A, a first epitaxial layer 3 of a first conductivity type is formed by an epitaxial growth process.
The lowermost charge balance layer 2 is formed on a semiconductor substrate 1 of the first conductivity type.
In the method according to the first embodiment of the present invention, the material of the semiconductor substrate 1 is silicon carbide. In other embodiments the method can also be: the material of the semiconductor substrate 1 includes silicon, gallium nitride, diamond, aluminum nitride, and boron carbide.
Step two, as shown in fig. 3B, a plurality of first doped regions 4 doped with a second conductivity type are formed in the selected region of the first epitaxial layer 3 by using a lithography definition plus ion implantation process; the charge balance layer 2 is composed of each of the first doped regions 4 and the first epitaxial layer 3.
Each first doping region 4 extends from the surface of the first epitaxial layer 3 to the inside of the first epitaxial layer 3, the junction depth of each first doping region 4 is smaller than the thickness of the first epitaxial layer 3, and a space is formed between each first doping region 4.
The first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are charge balanced, and the first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are fully depleted from each other when the drift region is reverse biased.
As shown in fig. 3C, all the charge balance layer 2 required in the drift region is formed by repeating the first and second steps. In fig. 3C, it is shown that two layers of the charge balance layer 2 are formed.
The charge balance device is a charge balance Schottky diode, and further comprises the following steps:
step three, as shown in fig. 3D, a second epitaxial layer 101 of the first conductivity type is formed on the surface of the charge balance layer 2 at the topmost layer.
Step four, as shown in fig. 3E, a plurality of second conductive type doped second doped regions 102 are formed in the selected region of the second epitaxial layer 101 by using a lithography definition and ion implantation process; each of the second doped regions 102 extends from the surface of the second epitaxial layer 101 toward the inside of the second epitaxial layer 101, the junction depth of each of the second doped regions 102 is smaller than the thickness of the second epitaxial layer 101, and a space is provided between each of the second doped regions 102.
Step five, as shown in fig. 3F, forming a schottky metal layer 103 on the surface of the second epitaxial layer 101 on which the second doped region 102 is formed; the schottky metal layer 103 forms a schottky contact with the surface of the second epitaxial layer 101, and the schottky metal layer 103 forms an ohmic contact with the second doped region 102.
Sixthly, as shown in fig. 1, a front metal layer 104 is formed on the surface of the schottky metal layer 103, and the front metal layer 104 constitutes an anode.
Step seven, as shown in fig. 1, forming a back metal layer on the back surface of the semiconductor substrate 1, and forming a cathode 105 from the back metal layer.
The charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type. In other embodiments the method can also be: the charge balance device is of a P type, the first conductivity type is of a P type, and the second conductivity type is of an N type.
Fig. 4A to 4F are schematic diagrams of device structures in steps of a method for manufacturing a charge balance device according to a second embodiment of the present invention; in the method for manufacturing a charge balance device according to the second embodiment of the present invention, the drift region of the charge balance device includes more than one charge balance layer 2; the type of the conductive carrier of the drift region is a first conductivity type; the method comprises the following steps:
step one, as shown in fig. 4A, a first epitaxial layer 3 of a first conductivity type is formed by using an epitaxial growth process.
The lowermost charge balance layer 2 is formed on a semiconductor substrate 1 of the first conductivity type.
In the method according to the second embodiment of the present invention, the material of the semiconductor substrate 1 is silicon carbide. In other embodiments the method can also be: the material of the semiconductor substrate 1 includes silicon, gallium nitride, diamond, aluminum nitride, and boron carbide.
Step two, as shown in fig. 4B, a plurality of first doped regions 4 doped with a second conductivity type are formed in the selected region of the first epitaxial layer 3 by using a lithography definition plus ion implantation process; the charge balance layer 2 is composed of each of the first doped regions 4 and the first epitaxial layer 3.
Each first doping region 4 extends from the surface of the first epitaxial layer 3 to the inside of the first epitaxial layer 3, the junction depth of each first doping region 4 is smaller than the thickness of the first epitaxial layer 3, and a space is formed between each first doping region 4.
The first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are charge balanced, and the first epitaxial layer 3 and each of the first doped regions 4 in the charge balance layer 2 are fully depleted from each other when the drift region is reverse biased.
As shown in fig. 4C, all the charge balance layers 2 required in the drift region are formed by repeating the first and second steps. In fig. 4C, two layers of the charge balance layer 2 are shown to be formed.
The charge balance device is a charge balance field effect transistor, and further comprises the following steps:
step three, as shown in fig. 4D, a second epitaxial layer 201 of the first conductivity type is formed on the surface of the charge balance layer 2 at the topmost layer, and the second epitaxial layer 201 is used as a component of the drift region.
Step four, as shown in fig. 4E, a base region 202 doped with the second conductivity type is formed in the second epitaxial layer 201.
Step five, as shown in fig. 4F, a source region 203 is formed in the base region 202.
And step six, forming a gate structure, wherein the gate structure comprises an overlapped structure of a gate oxide layer 204 and a polysilicon gate 205. The surface of the base region 202 covered by the gate structure is used to form a channel connecting the source region 203 and the drift region.
The gate structure is a planar gate, the gate structure covers the surface of the base region 202 and extends to the surface of the drift region outside the base region 202, and the surface of the base region 202 covered by the front surface of the gate structure is used for forming the channel. As shown in fig. 4G, first, the gate oxide layer 204 and the polysilicon gate 205 are grown or deposited; for silicon carbide material devices, the gate oxide layer 204 is typically formed using a deposition process. Thereafter, as illustrated in fig. 4H, a lithography definition plus etching process is performed to form the gate structure in the selected region.
In other embodiments, the method can also be: the gate structure is a trench gate, the gate oxide layer 204 is formed on the bottom surface and the side surface of the gate trench, the polysilicon gate 205 is filled in the gate trench, the gate trench penetrates through the base region 202, and the surface of the base region 202 covered by the side surface of the polysilicon gate 205 is used for forming the channel.
Step seven, as shown in fig. 4I, an interlayer film 206 is formed.
As shown in fig. 2, forming a contact hole 207, forming a front metal layer 208, and patterning the front metal layer 208 to form a source and a gate; the top of the source region 203 is connected to a source electrode composed of a front metal layer 208 through a contact hole 207; the contact hole 207 at the bottom of the source electrode also penetrates through the source region 203 to be contacted with the base region 202.
Step eight, forming a drain region by the semiconductor substrate 1; a back metal layer is formed on the back of the drain region, and the drain 209 is formed by the back metal layer.
The charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type. In other embodiments the method can also be: the charge balance device is of a P type, the first conductivity type is of a P type, and the second conductivity type is of an N type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A charge balance device, characterized by: the drift region of the charge balance device comprises more than one charge balance layer; the type of the conductive carrier of the drift region is a first conductivity type;
the charge balance layer includes: a first epitaxial layer of a first conductivity type and a plurality of first doped regions of a second conductivity type doping formed in selected regions of the first epitaxial layer; each first doping region extends from the surface of the first epitaxial layer to the inside of the first epitaxial layer, the junction depth of each first doping region is smaller than the thickness of the first epitaxial layer, and a space is reserved between the first doping regions;
the first epitaxial layer and each of the first doped regions in the charge balance layer are charge balanced, and the first epitaxial layer and each of the first doped regions in the charge balance layer are fully depleted from each other when the drift region is reverse biased.
2. The charge balance device of claim 1, wherein: the bottom layer of the charge balance layer is formed on the semiconductor substrate of the first conduction type.
3. The charge balance device of claim 2, wherein: the material of the semiconductor substrate comprises: silicon carbide, silicon, gallium nitride, diamond, aluminum nitride, boron carbide.
4. The charge balance device of claim 2, wherein: the charge balance device is a charge balance Schottky diode, and further comprises:
a cathode composed of a back metal layer formed on the back surface of the semiconductor substrate;
forming a second epitaxial layer of the first conduction type on the surface of the charge balance layer at the topmost layer;
a plurality of second doped regions of a second conductivity type dopant formed in selected regions of said second epitaxial layer; each second doped region extends from the surface of the second epitaxial layer to the inside of the second epitaxial layer, the junction depth of each second doped region is smaller than the thickness of the second epitaxial layer, and a space is reserved between the second doped regions;
a Schottky metal layer is formed on the surface of the second epitaxial layer on which the second doped region is formed; a Schottky contact is formed on the surfaces of the Schottky metal layer and the second epitaxial layer, and an ohmic contact is formed between the Schottky metal layer and the second doped region;
and an anode consisting of a front metal layer is formed on the surface of the Schottky metal layer.
5. The charge balance device of claim 2, wherein: the charge balance device is a charge balance field effect transistor, comprising:
a second epitaxial layer of the first conductivity type formed on the surface of the charge balance layer at the topmost layer, the second epitaxial layer being a component of the drift region;
a base region doped with a second conductive type is formed in the second epitaxial layer;
the grid structure comprises a grid oxide layer and a polysilicon grid in a superposed structure;
the source region is formed in the base region;
the surface of the base region covered by the gate structure is used for forming a channel connecting the source region and the drift region;
the top of the source region is connected to a source electrode consisting of a front metal layer through a contact hole; the contact hole at the bottom of the source electrode also penetrates through the source region and is contacted with the base region;
forming a drain region by the semiconductor substrate;
and the drain electrode is formed by a back metal layer formed on the back of the drain region.
6. The charge balance device of claim 5, wherein: the gate structure is a planar gate, the gate structure covers the surface of the base region and extends to the surface of the drift region outside the base region, and the surface of the base region covered by the front surface of the gate structure is used for forming the channel;
or, the grid structure is a trench grid, the grid oxide layer is formed on the bottom surface and the side surface of the grid groove, the polysilicon grid is filled in the grid groove, the grid groove penetrates through the base region, and the surface of the base region covered by the side surface of the polysilicon grid is used for forming the channel.
7. The charge balance device of claim 1, wherein: the first doped region is an ion implantation region.
8. A charge balance device as claimed in any one of claims 1 to 7 wherein: the charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type; or the charge balance device is of a P type, the first conduction type is of a P type, and the second conduction type is of an N type.
9. A method of fabricating a charge balance device, comprising: the drift region of the charge balance device comprises more than one charge balance layer; the type of the conductive carrier of the drift region is a first conductivity type; the method comprises the following steps:
step one, forming a first epitaxial layer of a first conductivity type by adopting an epitaxial growth process;
step two, a plurality of first doping regions doped with the second conductivity type are formed in the selected region of the first epitaxial layer by adopting a photoetching definition and ion implantation process; the charge balance layer is formed by each first doping area and the first epitaxial layer;
each first doping region extends from the surface of the first epitaxial layer to the inside of the first epitaxial layer, the junction depth of each first doping region is smaller than the thickness of the first epitaxial layer, and a space is reserved between the first doping regions;
the first epitaxial layer and each first doping region in the charge balance layer are in charge balance, and the first epitaxial layer and each first doping region in the charge balance layer are fully depleted when the drift region is subjected to reverse bias;
repeating steps one and two to form all the charge balance layers needed in the drift region.
10. The method of manufacturing a charge balance device of claim 9, wherein: the bottom layer of the charge balance layer is formed on the semiconductor substrate of the first conduction type.
11. The method of manufacturing a charge balance device of claim 10, wherein: the material of the semiconductor substrate comprises: silicon carbide, silicon, gallium nitride, diamond, aluminum nitride, boron carbide.
12. The method of manufacturing a charge balance device of claim 10, wherein: the charge balance device is a charge balance Schottky diode, and further comprises the following steps:
step three, forming a second epitaxial layer of the first conduction type on the surface of the charge balance layer at the topmost layer;
step four, a plurality of second doping regions doped with the second conductivity type are formed in the selected region of the second epitaxial layer by adopting a photoetching definition and ion implantation process; each second doped region extends from the surface of the second epitaxial layer to the inside of the second epitaxial layer, the junction depth of each second doped region is smaller than the thickness of the second epitaxial layer, and a space is reserved between the second doped regions;
fifthly, forming a Schottky metal layer on the surface of the second epitaxial layer on which the second doped region is formed; a Schottky contact is formed on the surfaces of the Schottky metal layer and the second epitaxial layer, and an ohmic contact is formed between the Schottky metal layer and the second doped region;
forming a front metal layer on the surface of the Schottky metal layer, and forming an anode by using the front metal layer;
and seventhly, forming a back metal layer on the back of the semiconductor substrate, wherein the back metal layer forms a cathode.
13. The method of manufacturing a charge balance device of claim 10, wherein: the charge balance device is a charge balance field effect transistor, and further comprises the following steps:
forming a second epitaxial layer of the first conduction type on the surface of the charge balance layer at the topmost layer, wherein the second epitaxial layer is used as a component of the drift region;
forming a base region doped with a second conductive type in the second epitaxial layer;
fifthly, forming a source region in the base region;
sixthly, forming a grid structure, wherein the grid structure comprises a stacked structure of a grid oxide layer and a polysilicon grid; the surface of the base region covered by the gate structure is used for forming a channel connecting the source region and the drift region;
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode; the top of the source region is connected to a source electrode consisting of a front metal layer through a contact hole; the contact hole at the bottom of the source electrode also penetrates through the source region and is contacted with the base region;
step eight, forming a drain region by the semiconductor substrate; and forming a back metal layer on the back of the drain region, wherein the back metal layer forms a drain electrode.
14. The method of manufacturing a charge balance device of claim 13, wherein: the gate structure is a planar gate, the gate structure covers the surface of the base region and extends to the surface of the drift region outside the base region, and the surface of the base region covered by the front surface of the gate structure is used for forming the channel;
or, the grid structure is a trench grid, the grid oxide layer is formed on the bottom surface and the side surface of the grid groove, the polysilicon grid is filled in the grid groove, the grid groove penetrates through the base region, and the surface of the base region covered by the side surface of the polysilicon grid is used for forming the channel.
15. A method of fabricating a charge balance device according to any of claims 9 to 14, wherein: the charge balance device is of an N type, the first conduction type is of an N type, and the second conduction type is of a P type; or the charge balance device is of a P type, the first conduction type is of a P type, and the second conduction type is of an N type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911280574.8A CN112993008A (en) | 2019-12-13 | 2019-12-13 | Charge balance device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911280574.8A CN112993008A (en) | 2019-12-13 | 2019-12-13 | Charge balance device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112993008A true CN112993008A (en) | 2021-06-18 |
Family
ID=76332217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911280574.8A Pending CN112993008A (en) | 2019-12-13 | 2019-12-13 | Charge balance device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112993008A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117525155A (en) * | 2024-01-05 | 2024-02-06 | 深圳天狼芯半导体有限公司 | MOSFET integrated with SBD diode and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007251023A (en) * | 2006-03-17 | 2007-09-27 | Toyota Motor Corp | Semiconductor device with superjunction structure, and its manufacturing method |
| JP2014017326A (en) * | 2012-07-06 | 2014-01-30 | Rohm Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| CN107221561A (en) * | 2017-06-29 | 2017-09-29 | 全球能源互联网研究院 | A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof |
| CN108369963A (en) * | 2015-12-15 | 2018-08-03 | 通用电气公司 | The edge termination of silicon carbide super junction power device designs |
| CN108780806A (en) * | 2016-03-22 | 2018-11-09 | 通用电气公司 | Superjunction power semiconductor arrangement with fast switching capability |
| CN109643736A (en) * | 2016-06-30 | 2019-04-16 | 通用电气公司 | Active area for charge balance JBS diode designs |
-
2019
- 2019-12-13 CN CN201911280574.8A patent/CN112993008A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007251023A (en) * | 2006-03-17 | 2007-09-27 | Toyota Motor Corp | Semiconductor device with superjunction structure, and its manufacturing method |
| JP2014017326A (en) * | 2012-07-06 | 2014-01-30 | Rohm Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| CN108369963A (en) * | 2015-12-15 | 2018-08-03 | 通用电气公司 | The edge termination of silicon carbide super junction power device designs |
| CN108780806A (en) * | 2016-03-22 | 2018-11-09 | 通用电气公司 | Superjunction power semiconductor arrangement with fast switching capability |
| CN109643736A (en) * | 2016-06-30 | 2019-04-16 | 通用电气公司 | Active area for charge balance JBS diode designs |
| CN107221561A (en) * | 2017-06-29 | 2017-09-29 | 全球能源互联网研究院 | A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117525155A (en) * | 2024-01-05 | 2024-02-06 | 深圳天狼芯半导体有限公司 | MOSFET integrated with SBD diode and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6471126B2 (en) | Improved Schottky rectifier | |
| JP5739813B2 (en) | Semiconductor device | |
| CN103000665B (en) | Super-junction device and manufacture method | |
| US6710418B1 (en) | Schottky rectifier with insulation-filled trenches and method of forming the same | |
| US20180358478A1 (en) | Trench type junction barrier schottky diode with voltage reducing layer and manufacturing method thereof | |
| US20050242411A1 (en) | [superjunction schottky device and fabrication thereof] | |
| US20150221756A1 (en) | Semiconductor Device and Insulated Gate Bipolar Transistor with Barrier Structure | |
| EP2920816B1 (en) | Method of manufacturing trench-based schottky diode with improved trench protection | |
| US10229969B2 (en) | Power semiconductor device | |
| EP3479414A1 (en) | Active area designs for charge-balanced jbs diodes | |
| JP2019216223A (en) | Semiconductor device | |
| CN103208529B (en) | Semiconductor diode and the method for forming semiconductor diode | |
| US20180358477A1 (en) | Trench type junction barrier schottky diode and manufacturing method thereof | |
| JP5621198B2 (en) | Semiconductor device | |
| CN112993008A (en) | Charge balance device and method of manufacturing the same | |
| CN112993007A (en) | Super junction structure and super junction device | |
| CN112289848A (en) | Low-power-consumption high-performance super junction JBS diode and manufacturing method thereof | |
| CN214012948U (en) | Schottky diode | |
| CN113964186A (en) | Schottky super junction semiconductor device and manufacturing method thereof | |
| CN114284360A (en) | Leakage-free Schottky super-junction semiconductor device and manufacturing method thereof | |
| CN113113463A (en) | Semiconductor device, super junction structure for semiconductor device and manufacturing method thereof | |
| CN106033781A (en) | Schottky barrier diode and preparation method for the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |