CN114284360A - Leakage-free Schottky super-junction semiconductor device and manufacturing method thereof - Google Patents
Leakage-free Schottky super-junction semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a non-leakage Schottky super-junction semiconductor device and a manufacturing method thereof, wherein the non-leakage Schottky super-junction semiconductor device is characterized in that a groove is formed in a first conduction type drift region, a metal layer is deposited at the bottom in the groove, the metal layer and the first conduction type drift region form a columnar metal/first conduction type semiconductor Schottky junction, a groove dielectric layer is deposited in the middle in the groove, the groove dielectric layer is deposited at the height position of a P/N junction of the first conduction type drift region and a second conduction type well region to ensure that the metal layer does not form ohmic contact with the second conduction type well region, a cathode metal layer is deposited on the groove dielectric layer, and the cathode metal layer forms ohmic contact with the second conduction type well region and the first conduction type well region respectively. The non-leakage Schottky super-junction semiconductor device has better on-resistance and breakdown voltage and better device breakdown voltage uniformity, and simultaneously avoids impact ionization of mobile carriers caused by reverse leakage current.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a leakage-free Schottky super junction semiconductor device and a manufacturing method thereof.
Background
In the field of medium-high voltage power semiconductor devices, a Super Junction structure (Super Junction) is widely adopted, and compared with a traditional power MOSFET device, the Super Junction structure can obtain a more excellent compromise relationship between the withstand voltage and the on resistance of the device.
Conventional power switching MOSFET devices such as DMOS (double diffused metal oxide semiconductor) and VMOS (vertical metal oxide semiconductor) have a doping concentration in the n-type drain drift region that is a major factor in determining the on-resistance and reverse breakdown voltage of the device in the "off" state. In the n-type drain drift region, the higher the doping concentration is, the higher the mobile carrier density is, and the lower the on-resistance of the device is. However, the higher doping concentration in the n-type drain drift region also reduces the breakdown electric field of the body/drain junction of conventional switching MOSFET devices. To solve this problem, a new concept of superjunction was proposed in 1990 by placing a plurality of columnar P-type semiconductors in the vertical N-type drift drain region, forming columnar P/N junctions between the top switching MOSFET device and the bottom anode electrode, as shown in fig. 1, and turning off the MOSFET device anode when the SJ MOSFET device is in Zero Current Switching (ZCS) mode, the columnar P/N junctions forming depletion regions on both sides of the P/N junctions. As shown in fig. 2, space charges form a horizontal electric field in the depletion region between the P/N pillars. In the n-type drain drift region, the electric field at the columnar junction is the largest, while the electric field in the central region is smaller, forming a horizontal electric field. On the other hand, at high voltage bias of the anode node in ZCS mode, a vertical electric field is also established from the bottom semiconductor of the anode region to the top semiconductor surface within the vertical n-type drain drift region. In addition to the vertical field applied in the superjunction structure, the horizontal electric field of the n-type drift drain depletion region has two important effects: 1. collecting mobile carriers (impacting ionization sources) horizontally towards the columnar P/N junction to avoid reaching the fragile surface body/drain junction of the switching MOSFET; 2. preventing the strong vertical electric field from penetrating directly from the bottom region to reach the maximum breakdown field of the body/drain junction of the surface of the switching MOSFET device. Thus, the breakdown voltage of the SJ MOSFET device is improved by the space charge generated by the horizontal electric field and the horizontal electric field generated by the dopant concentration of the depleted pillar n-type drain drift region, while the higher dopant concentration of the pillar n-type drain drift region causes the higher mobile carrier density to also reduce the resistance of the MOSFET device.
As shown in fig. 3, a schematic diagram of a switching MOSFET device 300 having a super junction structure is composed of a gate electrode 311,MOSFET device 310 with source 312, channel 313 and drain 314 and P/N diode 320 for a P/N superjunction structure, it can also be appreciated from the schematic that the breakdown voltage of SJ MOSFET device 300 in ZCS mode can be increased by connecting reverse P/N diode 320 in parallel with switching MOSFET device 310 compared to conventional switching MOSFET devices. Furthermore, SJ MOSFET devices are the preferred devices for high frequency switching applications, including zero voltage switching bridges (ZVS), due to their lower on-resistance and low capacitance compared to conventional power MOSFETs. The switching MOSFET device 310 in the switching MOSFET device 300 having the super junction structure is switched in the ZVS mode. In zero voltage or synchronous applications, the body diode of the MOSFET device is not affected by hard-switching commutation, and when the SJ MOSFET device 310 is turned off, the diode current commutates soft with the MOSFET channel, and the diode recovers voltage blocking capability. However, diode recovery cannot be considered reasonable under all conditions of ZVS application when the SJ MOSFET device 310 is turned off, other factors such as transients, low reverse recovery charge (Q)rr) Shorter carrier lifetime and soft recovery characteristics remain important requirements.
The presently known metal/N semiconductor schottky diodes have similar I-V (current-voltage) characteristics as the P/N diodes shown in the figures. As shown in fig. 4, since various metals (platinum, tungsten, molybdenum, chromium), metal silicides, etc., and semiconductors (silicon, silicon carbide, germanium, gallium nitride, etc.) can be selected, the metal/N semiconductor schottky junction can have as good on-resistance and shielding voltage as the P/N superjunction semiconductor. Most importantly, schottky diodes have superior switching performance in ZVS bridge operation to P/N diodes because they are "majority carrier transfer" devices compared to "minority carrier transfer". In the invention, a metal/N semiconductor Schottky diode is applied to a super junction structure of an SJ MOSFET device to replace a conventional P/N diode, so that the Schottky SJ MOSFET device can improve the switching characteristic.
In one aspect of the invention, the schottky superjunction structure can produce a SJ MOSFET device with fewer process steps than the P/N SJ MOSFET devices. The schottky SJ MOSFET has fewer process steps, and can reduce manufacturing cost, thereby yielding product advantages. In the general fabrication of SJ MOSFET devices, multiple semiconductor epitaxial growth and masking steps are required to form the P/N junction. And schottky junctions may be formed by depositing a metallic material into trenches etched into an n-type semiconductor substrate.
However, although schottky diodes have the above advantages over P/N diodes, the reverse leakage current of schottky diodes is much higher than the reverse P/N diode leakage current, as shown by the typical schottky diode and P/N diode I-V characteristics shown in fig. 4. The higher leakage current of schottky diodes can lead to impact ionization of mobile carriers, leading to early breakdown of SSJMOSFET devices. To cut off the reverse leakage current of the schottky diode of the SSJMOSFET device, we introduced a no-leakage schottky diode for the new superjunction structure.
Disclosure of Invention
In order to solve the problems, the technical scheme provided by the invention is as follows:
a non-leakage Schottky super-junction semiconductor device comprises a first conduction type substrate and a first conduction type epitaxial layer adjacent to the first conduction type substrate or the first conduction type epitaxial layer contained in the first conduction type substrate, wherein an anode metal layer is formed on the surface of the bottom of the first conduction type substrate far away from the first conduction type epitaxial layer, a first conduction type drift region is formed on the top of the first conduction type epitaxial layer, a second conduction type well region is formed on the first conduction type drift region, a second conduction type highly-doped well region and a first conduction type highly-doped well region are formed on the second conduction type well region, a groove is formed by the first conduction type drift region and the first conduction type epitaxial layer adjacent to the first conduction type drift region or the first conduction type drift region, and a metal layer is filled at the bottom of the groove, the top surface of the metal layer is filled with groove dielectric layers, grid dielectric layers arranged at intervals are formed at the top of the first conduction type drift region, grid metal is packaged in the grid dielectric layers, cathode metal layers are formed among the grid dielectric layers, at the top of the grid dielectric layers and on the top surface of the groove dielectric layers, the groove dielectric layers are deposited at the height positions of junctions formed by the first conduction type drift region and the second conduction type well region, and the cathode metal layers respectively form ohmic contact with the second conduction type high-doping well region and the first conduction type high-doping well region.
The invention is further arranged that the trench extends through the first conductive type highly doped well region, the second conductive type well region and the first conductive type drift region in sequence to extend into the first conductive type epitaxial layer.
The invention is further configured such that the first conductivity type substrate is a first conductor type highly doped region and the first conductivity type epitaxial layer is a first conductor type lowly doped region.
The invention further provides that the doping concentration of the first conduction type drift region is between the doping concentrations of the first conduction type substrate and the first conduction type epitaxial layer.
The invention is further arranged that an anode electrode is formed on the surface of the anode metal layer far away from the first conductive type substrate, and a cathode electrode is formed on the surface of the cathode metal layer far away from the first conductive type drift region.
A manufacturing method of a leakage-free Schottky super junction semiconductor device comprises the following steps:
providing a substrate, and forming a first conductive type drift region on the surface of the substrate;
performing ion implantation on the surface of the first conductive type drift region by using a mask to form a second conductive type well region;
growing a gate dielectric on the surface of the first conductive type drift region;
depositing a grid electrode film on the grid electrode dielectric medium, and etching the grid electrode film by utilizing a grid electrode mask to form grid electrode metal;
performing ion implantation on the surface of the second conductive type well region to form a second conductive type highly doped well region;
performing ion implantation on the surface of the second conductive type high doping well region to form a first conductive type high doping well region;
forming a gate dielectric layer on the periphery of the gate metal;
opening a groove opening in the first conductive type high-doping well region by using a groove mask, etching the bottom of the groove to the depth of contacting the substrate, annealing and solidifying the groove, cleaning the surface of the groove, depositing metal in the groove and performing metal reverse etching to enable the top of the metal to form a columnar metal/first conductive type semiconductor Schottky junction below the second conductive type well region;
depositing a dielectric on the top of the metal to form a trench dielectric layer, and depositing the trench dielectric layer at the height position of a junction formed by the first conductive type drift region and the second conductive type well region;
and implanting ions into the substrate to form a substrate highly-doped region, depositing drain metal in the substrate highly-doped region, and depositing source metal on the grid dielectric layer and the groove dielectric layer, so that the source metal forms ohmic contact with the second conductive type highly-doped well region and the first conductive type highly-doped well region respectively.
The invention is further configured to clean the trench sidewalls above the top surface of the trench dielectric layer and to remove the trench dielectric layer attached to the trench sidewalls before depositing source metal on the gate dielectric layer and on the trench dielectric layer.
The invention is further arranged to turn the semiconductor and thin the substrate to a thickness of 1-150 μm before implanting ions into the substrate to form a highly doped region of the substrate.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
according to the technical scheme, the leakage-free Schottky super junction semiconductor device is characterized in that a groove is formed in a first conduction type drift region, a metal layer is deposited at the bottom in the groove, the metal layer and the first conduction type drift region form a columnar metal/first conduction type semiconductor Schottky junction, a groove dielectric layer is deposited in the middle in the groove, the groove dielectric layer is deposited at the height position of a P/N junction of the first conduction type drift region and a second conduction type well region, the metal layer is guaranteed not to form ohmic contact with the second conduction type well region, a cathode metal layer is deposited on the groove dielectric layer, the cathode metal layer forms ohmic contact with the second conduction type high-doping well region and the first conduction type high-doping well region respectively, the grid metal is packaged by the dielectric layer, and short circuit of the grid metal, a cathode electrode and the cathode metal layer is prevented.
The metal/N-semiconductor Schottky junction and the P/N super-junction semiconductor have the same good on-resistance and breakdown voltage, and most importantly, as the Schottky diode is a majority carrier transport device, compared with the P/N junction transport device of minority carriers, the switching performance of the Schottky diode for ZVS bridge operation is superior to that of a conventional P/N diode, and the non-leakage Schottky super-junction semiconductor device has better device breakdown voltage uniformity, so that the Schottky SJ MOSFET device can improve the switching characteristic; and the reverse leakage current of the Schottky diode of the SSJMOSFET device is cut off by depositing a trench dielectric layer in the trench, so that impact ionization of mobile carriers caused by the reverse leakage current is avoided.
In another aspect, the manufacturing process steps of the non-leakage Schottky super-junction semiconductor device are fewer, the Schottky junction can be formed by depositing metal materials in the first conduction type drift region and the epitaxial layer etching groove through one mask step, the manufacturing cost can be reduced, and the product competitive advantage is better.
Drawings
Fig. 1 is a cross-sectional view of a prior art SJ MOSFET device.
Fig. 2 is a graph of the horizontal field component of space charge generation in the depleted n-type drift drain region of a prior art SJ MOSFET device.
FIG. 3 is a schematic diagram of an equivalent circuit of a prior art P/N SJ MOSFET device in ZCS mode.
Fig. 4 is a graph showing similar I-V characteristics of a prior art metal/N semiconductor schottky diode and a P/N diode.
Fig. 5 is a cross-sectional view of a non-leakage schottky super junction semiconductor device in embodiment 1 of the present invention.
Fig. 6 is an equivalent circuit schematic diagram of a leakage-free schottky super junction semiconductor device in ZCS mode in embodiment 1 of the present invention.
Fig. 7 is an equivalent circuit schematic diagram of a leakage-free schottky super junction semiconductor device in ZVS mode in embodiment 1 of the present invention.
Fig. 8-17 are schematic process flow diagrams of manufacturing the non-leakage schottky super junction semiconductor device of fig. 5 in embodiment 2 of the present invention.
Detailed Description
For a further understanding of the present invention, reference will now be made in detail to the embodiments illustrated in the drawings.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, integrally connected, or detachably connected; either mechanically or electrically, or internally communicating two elements; they may be directly connected or indirectly connected through an intermediate, and those skilled in the art will understand the specific meanings of the above terms according to specific situations.
Example 1
With reference to fig. 5, the non-leakage schottky super junction semiconductor device according to the present invention includes a first conductivity type substrate 533 and a first conductivity type epitaxial layer 532 adjacent to the first conductivity type substrate 533 or a first conductivity type epitaxial layer 532 contained in the first conductivity type substrate 533, an anode metal layer 570 is formed on a surface of a bottom of the first conductivity type substrate 533 away from the first conductivity type epitaxial layer 532, a first conductivity type drift region 531 is formed on a top of the first conductivity type epitaxial layer 532, a second conductivity type well region 520 is formed on the first conductivity type drift region 520, a second conductivity type highly doped well region 521 and a first conductivity type highly doped well region 510 are formed on the second conductivity type well region 520, a trench 590 is formed on the first conductivity type drift region 531 and the first conductivity type epitaxial layer 532 adjacent thereto or the first conductivity type drift region 531, the bottom of the trench 590 is filled with a metal layer 580, the top surface of the metal layer 580 is filled with a trench dielectric layer 581, the top of the first conductive type drift region 531 forms gate dielectric layers 550 arranged at intervals, the gate dielectric layers 550 are encapsulated with gate metals 540, cathode metal layers 560 are formed between the gate dielectric layers 550, on the top of the gate dielectric layers 550 and on the top surface of the trench dielectric layer 581, the trench dielectric layers 581 are deposited at the height positions of P/N junctions formed by the first conductive type drift region 531 and the second conductive type well region 520, and the cathode metal layers 560 form ohmic contacts with the second conductive type highly doped well region 521 and the first conductive type highly doped well region 510 respectively.
In this embodiment, the trench 590 extends through the first conductive-type highly doped well region 510, the second conductive-type highly doped well region 521, the second conductive-type well region 520 and the first conductive-type drift region 531 in sequence and extends into the first conductive-type epitaxial layer 532.
In this embodiment, the first conductive type substrate 533 is a first conductive type highly doped region, the first conductive type epitaxial layer 532 is a first conductive type lowly doped region, and the doping concentration of the first conductive type drift region 531 is between the doping concentrations of the first conductive type substrate 533 and the first conductive type epitaxial layer 532.
In this embodiment, an anode electrode 502 is formed on a surface of the anode metal layer 570 away from the first conductive type substrate 533, and a cathode electrode 501 is formed on a surface of the cathode metal layer 560 away from the first conductive type drift region 531.
In the present embodiment, the first conductive type drift region 531 forms a pillar schottky junction with the metal layer 580, the metal layer 580.
In the present embodiment, the first conductive type substrate 533 is an N + high doping region, the first conductive type epitaxial layer 532 is a lightly doped N-lightly doped region, the first conductive type drift region 531 is an N-type semiconductor region, the second conductive type well region 520 is a P-type semiconductor region, the second conductive type highly doped well region 521 is a P + high doping region, and the first conductive type highly doped well region 510 is an N + high doping region.
In this embodiment, each MOSFET device has a gate 540, a highly doped N-type source region 510, a P-type body region 520, and an N-type common drain 530. The first conductive-type drift region 531, the first conductive-type epitaxial layer 532, and the first conductive-type substrate 533 constitute the N-type common drain 530.
As shown in fig. 5 and 6, the schematic of the schottky superjunction semiconductor device with cathode node 601 and anode node 602 in ZCS mode is represented by MOSFET device 610 with gate 611, source 612, channel 613 and drain 614 and schottky superjunction structure schottky diode 620, the breakdown voltage of the schottky superjunction semiconductor device in ZCS mode can be enhanced by reverse metal/N-semiconductor schottky diode 620 in parallel with switching MOSFET device 610, and capacitor 630 of metal layer, trench dielectric layer and cathode metal layer is used to cut off reverse leakage current of schottky diode 620. The capacitance of capacitor 630 is inversely proportional to the thickness of trench dielectric layer 581, which is required to satisfy the following requirements for trench dielectric layer 581: the trench dielectric 581 needs to be thinned to a certain thickness to increase the capacitance of the capacitor 630, so that the capacitance of the capacitor 630 is much larger than the capacitance of the capacitor formed by the gate dielectric 550 on the cathode metal 560 side; trench dielectric 581 needs to have a thickness to ensure that capacitor 630 is not broken down. In ZVS or synchronous applications as shown in fig. 7, the body diode (610 in fig. 6) of MOSFET device 710 is not affected by hard commutation, when the MOSFET is turned off, the diode current is soft-switched with the MOSFET channel, the schottky diode recovers voltage blocking capability, the switching transient, low reverse recovery charge (Q) of the schottky junction compared to a P/N superjunction for minority charge transport due to the dynamics of majority charge carrier transport in the schottky junctionrr) Shorter carrier lifetime and soft recovery characteristics are improved.
In the present embodiment, the metal layer 580 deposited in the trench 590 is platinum, tungsten, molybdenum, chromium, metal silicide, or the like; the trench dielectric layer 581 deposited within the trench 590 is silicon oxide or silicon nitride.
In another embodiment, the first conductive-type substrate 533 includes the first conductive-type epitaxial layer 532.
Example 2
With reference to fig. 8-17, the technical scheme of the invention is a manufacturing method of a leakage-free schottky super junction semiconductor device, which comprises the following steps:
providing a substrate 800, and forming a first conductive type drift region 810 on the surface of the substrate 800;
performing ion implantation on the surface of the first conductive type drift region 810 by using a mask to form a second conductive type well region 520;
growing a gate dielectric 820 on the surface of the first conductive-type drift region 810;
depositing a gate film 830 on the gate dielectric 820, and etching the gate film 830 by using a gate mask to form a gate metal 540;
performing ion implantation on the surface of the second conductive type well region 520 to form a second conductive type highly doped well region 521;
performing ion implantation on the surface of the second-conductivity-type highly doped well 521 to form a first-conductivity-type highly doped well 510;
forming a gate dielectric layer 550 on the periphery of the gate metal 540;
opening a trench 590 in the first conductive type highly doped well region 510 by using a trench mask, etching the bottom of the trench 590 to a depth contacting the substrate 800, annealing and curing the trench 590, cleaning the surface of the trench 590, depositing a metal into the trench 590 and performing a metal reverse etching to form a metal layer 580, so that the top of the metal layer 580 forms a columnar metal/first conductive type semiconductor schottky junction with the first conductive type drift region 531 below the second conductive type well region 520;
depositing a dielectric on the top surface of the metal layer 580 to form a trench dielectric layer 581, such that the trench dielectric layer 581 is deposited at the height position of the junction formed by the first conductive type drift region 531 and the second conductive type well region 520;
cleaning the side wall of the trench 590 above the top surface of the trench dielectric layer 581, and removing the dielectric attached to the side wall of the trench 590;
turning the semiconductor and thinning the substrate 800 to a thickness of 1-150 μm;
implanting ions into the substrate 800 to form a substrate highly doped region 533, depositing a drain metal 570 in the substrate highly doped region 533, and depositing a source metal 560 on the gate dielectric layer 550 and the trench dielectric layer 581, such that the source metal 560 forms ohmic contacts with the second conductive type highly doped well 521 and the first conductive type highly doped well 510, respectively.
In this embodiment, the first conductive type drift region 810 is formed on the substrate with a doping concentration of 1014cm-3～1016cm-3The N-type impurity of (1).
The present invention and its embodiments have been described above schematically, without limitation, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. Therefore, if the person skilled in the art receives the teaching, without departing from the spirit of the invention, the person skilled in the art shall not inventively design the similar structural modes and embodiments to the technical solution, but shall fall within the scope of the invention.
Claims (8)
1. A non-leakage Schottky super-junction semiconductor device is characterized by comprising a first conduction type substrate and a first conduction type epitaxial layer adjacent to the first conduction type substrate or a first conduction type epitaxial layer contained in the first conduction type substrate, wherein an anode metal layer is formed on the surface of the bottom of the first conduction type substrate far away from the first conduction type epitaxial layer, a first conduction type drift region is formed on the top of the first conduction type epitaxial layer, a second conduction type well region is formed on the first conduction type drift region, a second conduction type highly-doped well region and a first conduction type highly-doped well region are formed on the second conduction type well region, a groove is formed on the first conduction type drift region and the first conduction type epitaxial layer adjacent to the first conduction type drift region or the first conduction type drift region, and a metal layer is filled at the bottom of the groove, the top surface of the metal layer is filled with groove dielectric layers, grid dielectric layers arranged at intervals are formed at the top of the first conduction type drift region, grid metal is packaged in the grid dielectric layers, cathode metal layers are formed among the grid dielectric layers, at the top of the grid dielectric layers and on the top surface of the groove dielectric layers, the groove dielectric layers are deposited at the height positions of junctions formed by the first conduction type drift region and the second conduction type well region, and the cathode metal layers respectively form ohmic contact with the second conduction type high-doping well region and the first conduction type high-doping well region.
2. The leak-free schottky super junction semiconductor device of claim 1 wherein the trench extends through the first conductivity type highly doped well region, the second conductivity type well region and the first conductivity type drift region in sequence into the first conductivity type epitaxial layer.
3. The leak-free schottky super junction semiconductor device of claim 1, wherein the first conductivity type substrate is a first conductor type highly doped region and the first conductivity type epitaxial layer is a first conductor type lowly doped region.
4. The non-leakage schottky super-junction semiconductor device of claim 3, wherein the doping concentration of the drift region of the first conductivity type is between the doping concentrations of the substrate of the first conductivity type and the epitaxial layer of the first conductivity type.
5. The non-leakage schottky super-junction semiconductor device of claim 1, wherein the surface of the anode metal layer away from the first conductivity type substrate is formed with an anode electrode, and the surface of the cathode metal layer away from the first conductivity type drift region is formed with a cathode electrode.
6. A method for manufacturing a leakage-free Schottky super junction semiconductor device is characterized by comprising the following steps:
providing a substrate, and forming a first conductive type drift region on the surface of the substrate;
performing ion implantation on the surface of the first conductive type drift region by using a mask to form a second conductive type well region;
growing a gate dielectric on the surface of the first conductive type drift region;
depositing a grid electrode film on the grid electrode dielectric medium, and etching the grid electrode film by utilizing a grid electrode mask to form grid electrode metal;
performing ion implantation on the surface of the second conductive type well region to form a second conductive type highly doped well region;
performing ion implantation on the surface of the second conductive type high doping well region to form a first conductive type high doping well region;
forming a gate dielectric layer on the periphery of the gate metal;
opening a groove opening in the first conductive type high-doping well region by using a groove mask, etching the bottom of the groove to the depth of contacting the substrate, annealing and solidifying the groove, cleaning the surface of the groove, depositing metal in the groove and performing metal reverse etching to form a metal layer, and enabling the top of the metal layer to form a columnar metal/first conductive type semiconductor Schottky junction with the first conductive type drift region below the second conductive type well region;
depositing a dielectric medium on the top surface of the metal layer to form a groove dielectric layer, and depositing the groove dielectric layer at the height position of a junction formed by the first conductive type drift region and the second conductive type well region;
and implanting ions into the substrate to form a substrate highly-doped region, depositing drain metal in the substrate highly-doped region, and depositing source metal on the grid dielectric layer and the groove dielectric layer, so that the source metal forms ohmic contact with the second conductive type highly-doped well region and the first conductive type highly-doped well region respectively.
7. The method of claim 6, further comprising cleaning trench sidewalls above a top surface of the trench dielectric layer and removing dielectric attached to the trench sidewalls prior to depositing source metal on the gate dielectric layer and on the trench dielectric layer.
8. The method of claim 6, further comprising turning the semiconductor over and thinning the substrate to a thickness of 1-150 μm before implanting ions into the substrate to form the highly doped region of the substrate.
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