CN115483291A - Integrated circuit chip integrated with TMBS and preparation method thereof - Google Patents
Integrated circuit chip integrated with TMBS and preparation method thereof Download PDFInfo
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- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 title claims 4
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 78
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 68
- 239000004065 semiconductor Substances 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 43
- 230000007704 transition Effects 0.000 claims description 30
- 150000002500 ions Chemical class 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 230000000670 limiting effect Effects 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910000676 Si alloy Inorganic materials 0.000 claims description 5
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 5
- 230000036961 partial effect Effects 0.000 claims description 5
- 230000001413 cellular effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000002441 reversible effect Effects 0.000 description 17
- 238000011084 recovery Methods 0.000 description 16
- 230000002829 reductive effect Effects 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 10
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention relates to the technical field of integrated circuits, in particular to an integrated circuit chip integrated with a TMBS (transverse metal-base-plate) and a preparation method thereof. The invention solves the problems of large occupied area of the MOSFET device, and large conduction loss and switching loss of the device at present.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an integrated circuit chip integrating TMBS and a preparation method thereof.
Background
The use and development of MOSFET (metal oxide semiconductor field effect transistor) devices have been in history for many years, and planar power MOS devices are widely used as power switching tubes in various fields such as switching power supplies, automotive electronics, motor drives, etc. due to their advantages of high switching speed, high input impedance, voltage drive, high frequency, etc. At present, the main research objective of a power MOSFET is to reduce power consumption, and the power consumption of a Semiconductor device includes conduction loss and switching loss, especially, the conduction loss and the switching loss of a planar HV VDMOS (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) are both large, the conduction loss is mainly large due to large epitaxial resistivity, the VDMOS has a parasitic diode connected in parallel with the VDMOS, an anode of the parasitic diode is connected with a source electrode of the VDMOS, a cathode of the parasitic diode is connected with a drain electrode of the VDMOS, the parasitic diode is also used as a free flow, the parasitic diode is the same as a common diode and takes part in conduction by minority carriers, so that when the device is turned off, a reverse recovery time trr is long, and the switching loss of the device is large.
The method for reducing the conduction loss adopts SJ MOSFET to replace VDMOS, but the cost of the epitaxial manufacturing process of the SJ MOSFET is higher;
the traditional method for reducing the switching loss is to control the minority carrier lifetime through electron irradiation or heavy metal doping, reduce the reverse recovery charge Qrr, and further reduce the reverse recovery time trr, but the manufacturing cost of the device is increased, the IDSS leakage of the device is large, and the reliability of the whole device is reduced.
The conduction loss and the switching loss of the planar HV VDMOS are large; the conduction loss is mainly that the conduction resistance RDSON is larger due to larger epitaxial resistivity; the VDMOS is inherently provided with a parasitic diode connected in parallel with the VDMOS, an anode of the parasitic diode is connected with a source electrode of the VDMOS, a cathode of the parasitic diode is connected with a drain electrode of the VDMOS, and the parasitic diode also serves as a freewheeling diode, and the parasitic diode is conductive by minority carriers like a normal diode, so that when the device is turned off in the reverse direction, the reverse recovery time trr is longer, resulting in larger switching loss of the device.
In a word, the conventional MOSFET device is suitable for a common body diode (P-well region-N type epitaxial layer), has the problems of short overall service life and long reverse recovery time of the device, and also has the defects of high manufacturing cost, large occupied area, and large conduction loss and switching loss of the device.
Disclosure of Invention
The invention provides an integrated circuit chip integrated with a TMBS (metal oxide semiconductor field effect transistor) and a preparation method thereof, which solve the problems of large occupied area of an MOSFET (metal oxide semiconductor field effect transistor) device, large conduction loss and large switching loss of the device at present.
In order to realize the purpose of the invention, the technical scheme adopted by the design is as follows: an integrated circuit chip integrated with a TMBS (transverse magnetic resonance) comprises an active area, a terminal area and a transition area, wherein the active area is located in a chip center area, the terminal area surrounds the active area, the transition area is located between the active area and the terminal area and comprises a plurality of groove type Schottky diodes, the groove type Schottky diodes comprise Schottky grooves, groove polycrystalline silicon and an oxide layer surrounding the groove polycrystalline silicon are arranged in the Schottky grooves, the Schottky grooves are arranged in an N-type epitaxial layer, schottky contact layers are arranged on the Schottky grooves, the width of the Schottky contact layers is larger than that of the Schottky grooves, source metal layers are arranged on the Schottky contact layers, an N-type substrate is abutted to the lower portion of the N-type epitaxial layer, and drain metal layers in ohmic contact are arranged below the N-type substrate.
As a preferred embodiment of the present invention, the Schottky contact layer comprises a titanium layer, a titanium nitride layer and a tungsten metal layer adjacent to the titanium nitride layer.
As an optimization scheme of the invention, the terminal area comprises a partial pressure protection area and a cut-off area, the cut-off area is positioned at the outer ring of the terminal area, and the partial pressure protection area is positioned between the transition area and the cut-off area; the partial pressure protection area comprises a field limiting ring which is positioned in the N-type epitaxial layer; a field oxide layer covers the field limiting ring, floating conductive polycrystalline silicon is arranged above the field oxide layer, at least one floating conductive polycrystalline silicon is arranged, floating metal and a grid metal layer are arranged above the floating conductive polycrystalline silicon, and the floating conductive polycrystalline silicon and the floating metal are separated by an insulating medium layer; the stop region comprises a P-type stop well region positioned in the N-type epitaxial layer and an N-type stop source region positioned in the P-type stop well region, a stop ring metal and stop conductive polycrystalline silicon are arranged above the N-type stop source region, and the stop ring metal penetrates through the insulating medium layer and is in ohmic contact with the N-type stop source region and the stop conductive polycrystalline silicon respectively.
As an optimized scheme of the invention, the gate metal layer comprises a first conductive type layer, a second conductive type layer, a third conductive type layer and a fourth conductive type layer which are sequentially arranged from top to bottom, wherein the first conductive type layer, the second conductive type layer, the third conductive type layer and the fourth conductive type layer are all P-type semiconductor layers or N-type semiconductor layers; the P-type semiconductor layer or the N-type semiconductor layer are adjacently arranged to form a PN junction.
As an optimized scheme of the invention, the active area comprises a plurality of cellular units which are arranged in parallel, each cellular unit comprises a P-type well region positioned in the N-type epitaxial layer 2, an N-type source region positioned in the P-type well region, a gate oxide layer covering the N-type epitaxial layer, a gate conductive polycrystalline silicon covering the gate oxide layer, an insulating medium layer covering the gate conductive polycrystalline silicon, and a source metal layer covering the insulating medium layer, wherein the source metal layer penetrates through the insulating medium layer to be in ohmic contact with the P-type well region and the N-type source region respectively.
In order to realize the purpose of the invention, the technical scheme adopted by the design is as follows: a method for preparing an integrated circuit chip of an integrated TMBS is used for manufacturing the integrated circuit chip of the integrated TMBS and comprises the following steps:
1) Providing a semiconductor substrate, wherein the semiconductor substrate comprises an N-type epitaxial layer and an N-type substrate positioned below the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is a first main surface of the semiconductor substrate, and the lower surface of the N-type substrate is a second main surface of the semiconductor substrate;
2) Selectively injecting P-type ions into the first main surface, and pushing a trap to obtain a field limiting ring positioned in the N-type epitaxial layer;
3) Growing a thick oxide layer on the first main surface of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer on the first main surface, wherein the field oxide layer is not covered on the transition region;
4) Depositing a hard mask layer on the first main surface of the semiconductor substrate, etching the hard mask layer to obtain a hard mask pattern, and etching the first main surface under the masking of the hard mask pattern to obtain a Schottky trench in the transition region;
5) Growing an oxide layer and depositing conductive polysilicon on the field oxide layer, the first main surface of the semiconductor substrate and in the Schottky trench, and etching the oxide layer and the conductive polysilicon in turn to obtain gate conductive polysilicon in the active region, a gate oxide layer below the gate conductive polysilicon, floating conductive polysilicon and cut-off conductive polysilicon on the field oxide layer in the terminal region, an oxide layer in the Schottky trench in the transition region and trench polysilicon surrounded by the oxide layer;
6) Injecting P-type ions into the first main surface of the semiconductor substrate, and annealing to obtain a P-type well region positioned in the active region and a P-type cut-off well region positioned in the cut-off region;
7) Selectively injecting N-type ions into the first main surface of the semiconductor substrate to obtain an N-type source region positioned in a P-type well region of the active region and an N-type cut-off source region positioned in a P-type cut-off well region of the cut-off region;
8) Depositing an insulating medium layer on the first main surface, and selectively etching the insulating medium layer and the field oxide layer to obtain a plurality of metal contact holes; the metal contact holes comprise contact holes which are positioned in the active region and used for leading out the N-type active region, contact holes which are positioned in the transition region and used for the Schottky contact layer, contact holes used for leading out the grid conductive polycrystalline silicon and contact holes used for leading out the groove polycrystalline silicon;
9) Sputtering 800A-1000A of a titanium layer in a contact hole of a transition region, and annealing at low temperature for 30s at 720 ℃ in the atmosphere of N2 under the annealing condition, wherein the titanium layer and silicon at the bottom of the contact hole form a titanium-silicon alloy layer, the titanium-silicon alloy layer has a Schottky barrier and is called a Schottky barrier contact layer, the titanium layer and trench polysilicon in a Schottky trench form ohmic contact, the second main surface of a semiconductor is thinned, and then metal is deposited to obtain drain metal positioned on the lower surface of an N-type substrate.
As an optimized scheme of the present invention, a tungsten metal layer is deposited on the titanium layer 800A, a source metal layer is deposited on the tungsten metal layer, and the source metal layer and the tungsten metal layer form an ohmic contact.
The invention has the positive effects that: 1) The TMBS (Trench Mos Barrier Schottky diodes) diode (Schottky Barrier contact layer-N type epitaxial layer) surrounding the active region is arranged in the transition region between the active region and the terminal region of the device to replace the existing common body diode (P-type well region 16-N type epitaxial layer) to serve as a freewheeling diode, the TMBS is a Trench type Schottky diode and has the advantages of high switching frequency, forward voltage reduction and the like, and the Schottky diode is a majority carrier conductive device and does not have the problems of minority carrier service life and reverse recovery;
2) When the device works in a diode freewheeling mode, the source electrode metal is connected with a high potential, the drain electrode metal is connected with a low potential, the TMBS positioned in the transition region has no condition that minority carrier holes flow into the N-type epitaxial layer, and only the holes in the body diode positioned in the active region flow into the N-type epitaxial layer from the P-type body region, so that the hole current in the freewheeling process can be effectively reduced, and the hole charge quantity Qrr (namely reverse recovery charge) stored in the N-type epitaxial layer is reduced;
3) When the device enters the diode reverse recovery process, when the device is reversely biased, the drain metal is connected with a high potential, the source metal is connected with a low potential, and as the number of minority carrier holes stored in the N-type epitaxial layer is reduced, the minority carrier holes in the N-type epitaxial layer are swept out, the reverse recovery current Isd is obviously reduced, the reverse recovery time Trr is further reduced, and therefore, the loss of the device in the switching process is reduced;
4) When the device is reversely biased, the drain metal is connected with a high potential, the source metal is connected with a low potential, and the trench polysilicon in the TMBS trench of the transition region is in ohmic contact with the source metal, so that the trench polysilicon generates transverse depletion on the N-type epitaxy, thereby improving the voltage endurance capability of the transition region (most of the weak points of the traditional VDMOS avalanche breakdown are located in the transition region), further improving the voltage endurance capability of the whole device, and meanwhile, the N-type epitaxy layer with higher doping concentration can be adopted, so that the forward conduction resistance RDSON and the forward conduction voltage drop VFSD of the device are reduced, the conduction resistance RDSON is reduced, the conduction loss is reduced, the forward conduction voltage drop Vsd is reduced, the reverse recovery time Trr is further reduced, and the switching loss is reduced.
Drawings
The invention is described in further detail below with reference to the drawings and the detailed description.
FIG. 1 is a schematic view of the overall structure of the method of the present invention;
FIG. 2 isbase:Sub>A schematic cross-sectional view of A-A' of FIG. 1;
FIG. 3 is a schematic cross-sectional view of B-B' of FIG. 1;
FIG. 4 is a schematic cross-sectional view of C-C' of FIG. 1;
FIG. 5 is a schematic structural diagram of a gate metal layer;
fig. 6 is a graph comparing the reverse recovery current Isd of the conventional structure and the embodiment of the present invention.
Wherein: 1. the structure of the Schottky diode comprises an N-type substrate, 2, an N-type epitaxial layer, 3, a field limiting ring, 4, a field oxide layer, 6, floating conducting polycrystalline silicon, 7, an insulating medium layer, 8, a grid metal layer, 81, a first conducting type layer, 82, a second conducting type layer, 83, a third conducting type layer, 84, a fourth conducting type layer, 9, floating metal, 10, an active electrode metal layer, 11, a drain metal layer, 12, a stop ring metal, 13, stop conducting polycrystalline silicon, 14, a P-type stop well region, 15, an N-type stop source region, 16, a P-type well region, 17, an N-type source region, 18, a grid oxide layer, 19, grid conducting polycrystalline silicon, 20, a Schottky trench, 21, an oxide layer, 22, a Schottky contact layer, 23, trench polycrystalline silicon, 100, an active region, 101, a transition region, 102 and a terminal region.
Detailed Description
As shown in fig. 1-4, the present invention discloses an integrated circuit chip integrated with TMBS, which includes an active region 100 located in a central region of the chip, a termination region 102 surrounding the active region 100, and a transition region 101 located between the active region 100 and the termination region 102, wherein the transition region 101 includes a plurality of trench schottky diodes disposed around the active region 100, each trench schottky diode includes a schottky trench 20, a trench polysilicon 23 and an oxide layer 21 surrounding the trench polysilicon 23 are disposed in the schottky trench 20, the schottky trench 20 is disposed in an N-type epitaxial layer 2, a schottky contact layer 22 is disposed on the schottky trench 20, a width of the schottky contact layer 22 is greater than a width of the schottky trench 20, a source metal layer 10 is disposed on the schottky contact layer 22, the N-type epitaxial layer 2 is adjacent to the N-type substrate 1, and a drain metal layer 11 with ohmic contact is disposed under the N-type substrate 1; the contact of the schottky contact layer 22 with the N-type epitaxial layer 2 is a real schottky contact, and the schottky contact can be formed only if the width of the schottky trench 20 is larger.
The schottky contact layer 22 comprises a titanium layer, a titanium nitride layer, and a tungsten metal layer on the adjacent titanium nitride layer.
The terminal area 102 comprises a voltage division protection area and a cut-off area, the cut-off area is positioned at the outer ring of the terminal area 102, and the voltage division protection area is positioned between the transition area 101 and the cut-off area; the partial pressure protection region comprises a field limiting ring 3, and the field limiting ring 3 is positioned in the N-type epitaxial layer 2; a field oxide layer 4 covers the field limiting ring 3, floating conductive polysilicon 6 is arranged above the field oxide layer 4, at least one floating conductive polysilicon 6 is arranged, floating metal 9 and a grid metal layer 8 are arranged above the floating conductive polysilicon 6, and the floating conductive polysilicon 6 and the floating metal 9 are separated by an insulating medium layer 7; the cut-off region comprises a P-type cut-off well region 14 positioned in the N-type epitaxial layer 2 and an N-type cut-off source region 15 positioned in the P-type cut-off well region 14, a cut-off ring metal 12 and a cut-off conductive polysilicon 13 are arranged above the N-type cut-off source region 15, and the cut-off ring metal 12 penetrates through the insulating medium layer 7 to be in ohmic contact with the N-type cut-off source region 15 and the cut-off conductive polysilicon 13 respectively.
As shown in fig. 5, the gate metal layer 8 includes a first conductive type layer 81, a second conductive type layer 82, a third conductive type layer 83, and a fourth conductive type layer 84, which are sequentially arranged from top to bottom, where the first conductive type layer 81, the second conductive type layer 82, the third conductive type layer 83, and the fourth conductive type layer 84 are all P-type semiconductor layers or N-type semiconductor layers; the P-type semiconductor layer or the N-type semiconductor layer are adjacently arranged to form a PN junction. If the first layer of the first conductivity type layer 81 is N-type, the second layer of the second conductivity type layer 82 is P-type, and conversely, if the first layer of the first conductivity type layer 81 is P-type, the second layer of the second conductivity type layer 82 is N-type, where N-type ions include P ions, as ions, and P-type ions include B ions.
The active region 100 comprises a plurality of cell units which are arranged in parallel, each cell unit comprises a P-type well region 16 located in the N-type epitaxial layer 2, an N-type source region 17 located in the P-type well region 16, a gate oxide layer 18 covering the N-type epitaxial layer 2, a gate conductive polysilicon 19 covering the gate oxide layer 18, an insulating dielectric layer 7 covering the gate conductive polysilicon 19, and a source metal layer 10 covering the insulating dielectric layer 7, wherein the source metal layer 10 penetrates through the insulating dielectric layer 7 to be in ohmic contact with the P-type well region 16 and the N-type source region 17 respectively.
A method for preparing an integrated circuit chip of an integrated TMBS is used for manufacturing the integrated circuit chip of the integrated TMBS and comprises the following steps:
1) Providing a semiconductor substrate, wherein the semiconductor substrate comprises an N-type epitaxial layer 2 and an N-type substrate 1 positioned below the N-type epitaxial layer 2, the upper surface of the N-type epitaxial layer 2 is a first main surface of the semiconductor substrate, and the lower surface of the N-type substrate 1 is a second main surface of the semiconductor substrate;
2) Selectively implanting P-type ions (B ions in this case) into the first main surface, and trapping to obtain a field limiting ring 3 located in the N-type epitaxial layer 2;
3) Growing a thick oxide layer on the first main surface of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer 4 on the first main surface, wherein the field oxide layer 4 is not covered on the transition region 101;
4) Depositing a hard mask layer on a first main surface of a semiconductor substrate, etching the hard mask layer to obtain a hard mask pattern, and etching the first main surface under the masking of the hard mask pattern to obtain a Schottky trench 20 positioned in a transition region 101;
5) Growing an oxide layer and depositing conductive polysilicon on the field oxide layer 4, the first main surface of the semiconductor substrate and in the schottky trench 20, and etching the oxide layer and the conductive polysilicon in turn to obtain gate conductive polysilicon 19 located in the active region 100, a gate oxide layer 18 located below the gate conductive polysilicon 19, floating conductive polysilicon 6 and stop conductive polysilicon 13 located on the field oxide layer 4 of the terminal region 102, an oxide layer 21 located in the schottky trench 20 of the transition region 101, and trench polysilicon 23 surrounded by the oxide layer 21;
6) Implanting P-type ions (here, B ions) into the first main surface of the semiconductor substrate and annealing to obtain P-type well regions 16 located in the active region 100 and P-type cut-off well regions 14 located in the cut-off region 102;
7) Selectively implanting N-type ions into the first main surface of the semiconductor substrate to obtain an N-type source region 17 located in a P-type well region 16 of the active region 100 and an N-type cut-off source region 15 located in a P-type cut-off well region 14 of the cut-off region 102;
8) Depositing an insulating medium layer 7 on the first main surface, and selectively etching the insulating medium layer 7 and the field oxide layer 4 to obtain a plurality of metal contact holes; the metal contact holes comprise a contact hole which is positioned in the active region 100 and used for leading out the N-type source region 17, a contact hole which is positioned in the transition region 101 and used for leading out the Schottky contact layer 22, a contact hole for leading out the grid conductive polysilicon 19 and a contact hole for leading out the groove polysilicon 23;
9) Sputtering a titanium layer 800A-1000A in a contact hole of a transition region 101, and performing low-temperature annealing under the conditions that in the atmosphere of N2, the annealing temperature is 720 ℃ for 30s, the titanium layer and silicon at the bottom of the contact hole form a titanium-silicon alloy layer, the titanium-silicon alloy layer has a Schottky barrier and is called a Schottky barrier contact layer, the titanium layer and the groove polysilicon 23 in the Schottky groove 20 form ohmic contact, the second main surface of the semiconductor is thinned, and then metal is deposited to obtain drain metal 11 positioned on the lower surface of the N-type substrate 1. The drain metal 11 is ALSICU 4um.
Depositing a tungsten metal layer on the titanium layer 800A, depositing a source electrode metal layer 10 on the tungsten metal layer, and forming ohmic contact between the source electrode metal layer 10 and the tungsten metal layer.
The source metal layer 10 forms a schottky contact with the N-type epitaxial layer 2 through a schottky barrier contact layer, and the source metal layer 10 forms an ohmic contact with the trench polysilicon 23 through a schottky contact layer 22.
As shown in fig. 6, in the structure of the embodiment of the present invention, in the reverse recovery process, the reverse recovery peak current is significantly smaller than that of the conventional structure, and the reverse recovery current Isd is recovered to zero current (i.e., the reverse recovery time Trr is reduced) more quickly.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. An integrated circuit chip integrating a TMBS, comprising an active region (100) located in a central region of the chip, a termination region (102) surrounding said active region (100), and a transition region (101) located between the active region (100) and the termination region (102), characterized in that: transition region (101) are including surrounding a plurality of ditch groove type schottky diodes that active area (100) set up, ditch groove type schottky diode includes schottky slot (20), be equipped with ditch groove polycrystalline silicon (23) and surround in schottky slot (20) oxide layer (21) of ditch groove polycrystalline silicon (23), schottky slot (20) set up in N type epitaxial layer (2), are equipped with schottky contact layer (22) on schottky slot (20), the width of schottky contact layer (22) is greater than the width of schottky slot (20) be equipped with source metal layer (10) on schottky contact layer (22), N type epitaxial layer (2) are adjoint N type substrate (1) down, N type substrate (1) have drain metal layer (11) of ohmic contact.
2. The integrated circuit chip of claim 1, wherein: the Schottky contact layer (22) comprises a titanium layer, a titanium nitride layer, and a tungsten metal layer on the adjoining titanium nitride layer.
3. The integrated circuit chip of claim 1, wherein: the terminal area (102) comprises a voltage division protection area and a cut-off area, the cut-off area is positioned at the outer circle of the terminal area (102), and the voltage division protection area is positioned between the transition area (101) and the cut-off area; the partial pressure protection region comprises field limiting rings (3), and the field limiting rings (3) are positioned in the N-type epitaxial layer (2); a field oxide layer (4) covers the field limiting ring (3), floating conductive polysilicon (6) is arranged above the field oxide layer (4), at least one floating conductive polysilicon (6) is arranged, floating metal (9) and a grid metal layer (8) are arranged above the floating conductive polysilicon (6), and the floating conductive polysilicon (6) and the floating metal (9) are separated by an insulating medium layer (7); the cut-off region comprises a P-type cut-off well region (14) located in the N-type epitaxial layer (2) and an N-type cut-off source region (15) located in the P-type cut-off well region (14), a cut-off ring metal (12) and a cut-off conductive polycrystalline silicon (13) are arranged above the N-type cut-off source region (15), and the cut-off ring metal (12) penetrates through an insulating medium layer (7) to be in ohmic contact with the N-type cut-off source region (15) and the cut-off conductive polycrystalline silicon (13) respectively.
4. The integrated circuit chip of claim 3, wherein: the grid metal layer (8) comprises a first conductive type layer (81), a second conductive type layer (82), a third conductive type layer (83) and a fourth conductive type layer (84) which are sequentially arranged from top to bottom, wherein the first conductive type layer (81), the second conductive type layer (82), the third conductive type layer (83) and the fourth conductive type layer (84) are all P-type semiconductor layers or N-type semiconductor layers; the P-type semiconductor layer or the N-type semiconductor layer are adjacently arranged to form a PN junction.
5. The integrated circuit chip of claim 3, wherein: active area (100) include the cellular unit that a plurality of was arranged in parallel each other, the cellular unit is including being located P type well region (16) in N type epitaxial layer 2, being located N type source region (17) in P type well region (16), cover gate oxide (18) on N type epitaxial layer (2), cover grid conductive polysilicon (19) on gate oxide (18), cover insulating medium layer (7) on grid conductive polysilicon (19) cover source electrode metal layer (10) on insulating medium layer (7), source electrode metal layer (10) pass insulating medium layer (7) respectively with P type well region (16), N type source region (17) ohmic contact.
6. A method for manufacturing an integrated circuit chip integrated with TMBS according to claim 1, wherein the method comprises the steps of: the method comprises the following steps:
1) Providing a semiconductor substrate, wherein the semiconductor substrate comprises an N-type epitaxial layer (2) and an N-type substrate (1) positioned below the N-type epitaxial layer (2), the upper surface of the N-type epitaxial layer (2) is a first main surface of the semiconductor substrate, and the lower surface of the N-type substrate (1) is a second main surface of the semiconductor substrate;
2) Selectively injecting P-type ions into the first main surface and pushing a trap to obtain a field limiting ring (3) positioned in the N-type epitaxial layer (2);
3) Growing a thick oxide layer on the first main surface of the semiconductor substrate, and etching the thick oxide layer to obtain a field oxide layer (4) on the first main surface, wherein the field oxide layer (4) is not covered on the transition region (101);
4) Depositing a hard mask layer on the first main surface of the semiconductor substrate, etching the hard mask layer to obtain a hard mask pattern, and etching the first main surface under the masking of the hard mask pattern to obtain a Schottky trench (20) located in the transition region (101);
5) Growing an oxide layer and depositing conductive polysilicon on the field oxide layer (4), the first main surface of the semiconductor substrate and in the Schottky trench (20), and etching the oxide layer and the conductive polysilicon in sequence to obtain gate conductive polysilicon (19) positioned in the active region (100), a gate oxide layer (18) positioned below the gate conductive polysilicon (19), floating conductive polysilicon (6) and cut-off conductive polysilicon (13) positioned on the field oxide layer (4) of the terminal region (102), an oxide layer (21) positioned in the Schottky trench (20) of the transition region (101) and trench polysilicon (23) surrounded by the oxide layer (21);
6) Implanting P-type ions into the first main surface of the semiconductor substrate, and annealing to obtain a P-type well region (16) located in the active region (100) and a P-type cut-off well region (14) located in the cut-off region (102);
7) Selectively implanting N-type ions into the first main surface of the semiconductor substrate to obtain an N-type source region (17) positioned in a P-type well region (16) of the active region (100) and an N-type cut-off source region (15) positioned in a P-type cut-off well region (14) of the cut-off region (102);
8) Depositing an insulating dielectric layer (7) on the first main surface, and selectively etching the insulating dielectric layer (7) and the field oxide layer (4) to obtain a plurality of metal contact holes; the metal contact holes comprise a contact hole which is positioned in the active region (100) and used for leading out the N-type source region (17), a contact hole which is positioned in the transition region (101) and used for leading out the Schottky contact layer (22), a contact hole used for leading out the grid conducting polycrystalline silicon (19) and a contact hole used for leading out the groove polycrystalline silicon (23);
9) Sputtering a titanium layer 800A-1000A in the contact hole of the transition region (101), and annealing at low temperature for 30s at 720 ℃ in the atmosphere of N2, wherein the titanium layer and the silicon at the bottom of the contact hole form a titanium-silicon alloy layer which has a Schottky barrier and is called a Schottky barrier contact layer, the titanium layer forms ohmic contact with the groove polysilicon (23) in the Schottky groove (20), thinning the second main surface of the semiconductor, and depositing metal to obtain the drain metal (11) positioned on the lower surface of the N-type substrate (1).
7. The method of claim 6, wherein the method further comprises the steps of: and depositing a tungsten metal layer on the titanium layer 800A, and depositing a source metal layer (10) on the tungsten metal layer, wherein the source metal layer (10) and the tungsten metal layer form ohmic contact.
8. The method of claim 7, wherein the TMBS integrated circuit chip comprises: the source metal layer (10) forms Schottky contact with the N-type epitaxial layer (2) through a Schottky barrier contact layer, and the source metal layer (10) forms ohmic contact with the trench polysilicon (23) through a Schottky contact layer (22).
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| CN116705859A (en) * | 2023-07-31 | 2023-09-05 | 广东巨风半导体有限公司 | Silicon carbide metal oxide semiconductor field effect transistor structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116705859A (en) * | 2023-07-31 | 2023-09-05 | 广东巨风半导体有限公司 | Silicon carbide metal oxide semiconductor field effect transistor structure and preparation method thereof |
| CN116705859B (en) * | 2023-07-31 | 2024-02-23 | 广东巨风半导体有限公司 | Silicon carbide metal oxide semiconductor field effect transistor structure and preparation method thereof |
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