JP2012156151A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a simple structure in which the breakdown voltage can be enhanced in the whole outer peripheral region by enhancing the breakdown voltage in the corner area of a cell region.SOLUTION: The semiconductor device 1 has a cell region 2 in which a semiconductor element 6 is formed, and an outer peripheral region 3 formed on the outer periphery of the cell region 2. The number of p-type field relaxation regions 24n arranged in the corner area of the cell region 2 from the inside toward the outside of the outer peripheral region 3 is set larger than the number of the p-type field relaxation regions 24n arranged along each side of the cell region 2 from the inside toward the outside of the outer peripheral region 3.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure including a columnar region extending in a thickness direction of a substrate.

  Conventionally, a semiconductor device having a super junction structure is known. Patent Document 1 below discloses a semiconductor device having a super junction structure including a cell region in which a plurality of semiconductor elements are formed and an outer peripheral region for improving a breakdown voltage. In the cell region of this semiconductor device, a plurality of first p-type columnar regions and a plurality of first n-type columnar regions are alternately formed. In the outer peripheral region, a plurality of second p-type columnar regions and a plurality of second n-type columnar regions are alternately formed. Further, in the outer peripheral region, a third p-type columnar region and an n-type high resistance layer are formed on the upper layer of the second p-type columnar region and the second n-type columnar region.

  Here, the depths of the first p-type and first n-type columnar regions of the cell region are deeper than the depths of the second p-type and second n-type columnar regions. Further, the width of the second p-type columnar region is different from the width of the third p-columnar region.

  In the semiconductor device described in Patent Document 1 below, by using the third p-type columnar region, variations in the amount of impurities in each columnar region can be reduced. Thereby, the ratio (charge ratio) between the charge in the p-type columnar region and the charge in the n-type columnar region can be made constant, and the breakdown voltage of the semiconductor device can be improved.

JP 2006-5275 A

  However, in the semiconductor device disclosed in Patent Document 1, the following points have not been considered.

  Since the depth and width of each columnar region of the semiconductor device are different, the structure of the semiconductor device is complicated, and the manufacturing process is complicated accordingly. In particular, if the depth of the columnar region is different, it is difficult to make the amount of impurities in each columnar region equal by appropriately adjusting the ion implantation amount, so that it is difficult to ensure an optimal electric field balance and obtain a stable breakdown voltage. difficult.

  Further, in the corner region of the cell region, the electric field strength becomes the highest and the breakdown voltage is restricted, so that the breakdown voltage of the semiconductor device is deteriorated.

  The present invention has been made to solve the above-described problems. Accordingly, an object of the present invention is to provide a semiconductor device having a simple structure and capable of improving the breakdown voltage of the entire outer peripheral region by improving the breakdown voltage of the corner region of the cell region. Furthermore, the present invention is to provide a semiconductor device capable of improving the breakdown voltage of the entire outer peripheral region by improving the breakdown voltage of the corner region of the cell region while effectively utilizing the dead space.

  In order to solve the above problems, according to a first feature of an embodiment of the present invention, in a semiconductor device, a cell region in which a semiconductor element is formed, an outer peripheral region formed on the outer periphery of the cell region, a cell region, A plurality of first conductivity type regions of the first conductivity type formed in the outer peripheral region and a second conductivity type formed in the first conductivity type region of the cell region and arranged in the first direction and the second direction intersecting therewith. And a plurality of second conductivity type second columnar regions formed in the first conductivity type region of the outer peripheral region and arranged in the first direction and the second direction, and above the second columnar region. A plurality of electric field relaxation regions of the second conductivity type formed, and the distance between the electric field relaxation region and another electric field relaxation region adjacent thereto is different between the inner side and the outer side of the outer peripheral region, and the first direction and the first direction From inside to outside of electric field relaxation region arranged along two directions Relative number arranged towards is that number which are arranged from the inside to the outside of the electric field relaxation region is arranged in the corner region where the first and second directions intersect often.

  According to a second feature of the embodiment, in the semiconductor device according to the first feature, the distance between the electric field relaxation region on the inner side of the outer peripheral region and the other electric field relaxation region adjacent to the outer electric field relaxation region This is smaller than the distance from the electric field relaxation region.

  According to a third feature of the embodiment, in the semiconductor device according to the second feature, the distance between the electric field relaxation region in the outer peripheral region and another adjacent electric field relaxation region is gradually increased from the inside toward the outside. It is to become.

  A fourth feature according to the embodiment is that, in the semiconductor device according to the second feature or the third feature, the width of the electric field relaxation region in the outer peripheral region is gradually reduced from the inside toward the outside. .

  According to a fifth feature of the embodiment, in the semiconductor device according to any one of the second feature to the fourth feature, the depth of the electric field relaxation region in the outer peripheral region is gradually shallower from the inside toward the outside. It is to become.

  According to a sixth feature of the embodiment, in the semiconductor device according to any one of the second feature to the fifth feature, the distance between the first columnar region of the cell region and another first columnar region adjacent to the cell region is an outer periphery. It is equal to the distance between the second columnar region of the region and another adjacent second columnar region.

  According to a seventh feature of the embodiment, in the semiconductor device according to any one of the first feature to the sixth feature, an electric field relaxation region and a corner region arranged along the first direction and the second direction in the outer peripheral region. Two or more electric field relaxation regions are connected to each other and have a stripe shape.

  According to the present invention, it is possible to provide a semiconductor device that has a simple structure and can improve the breakdown voltage of the outer peripheral region by improving the breakdown voltage of the corner region of the cell region. Furthermore, according to the present invention, it is possible to provide a semiconductor device capable of improving the breakdown voltage of the entire outer peripheral region by improving the breakdown voltage of the corner region of the cell region while effectively utilizing the dead space.

FIG. 5 is a cross-sectional view (cross-sectional view taken along the cutting line F1-F1 shown in FIG. 3) of the cell region and the outer peripheral region disposed on the side of the semiconductor device according to Example 1 of the present invention. FIG. 6 is a cross-sectional view (cross-sectional view taken along the F2-F2 cutting line shown in FIG. 3) of the outer peripheral region disposed in the cell region and the corner region of the semiconductor device according to the first embodiment. 3 is a plan view of a cell region and an outer peripheral region of a semiconductor device according to Example 1. FIG. 6 is a first process cross-sectional view illustrating the manufacturing process of the semiconductor device according to Example 1. FIG. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is 4th process sectional drawing. It is 5th process sectional drawing. It is 6th process sectional drawing. 6 is a diagram illustrating a simulation result of a potential distribution of the semiconductor device according to Example 1. FIG. It is a figure which shows the simulation result of the electric potential distribution which concerns on a 1st comparative example. It is a figure which shows the simulation result of the electric potential distribution which concerns on a 2nd comparative example. 6 is a graph showing a relationship between a reverse voltage and a leakage current of the semiconductor device according to Example 1 and the semiconductor devices according to the first comparative example and the second comparative example. 6 is a graph showing the relationship between the reverse voltage and leakage current in the outer peripheral region of the semiconductor device according to Example 1; It is a top view of the cell area | region and outer peripheral area | region of the semiconductor device which concerns on Example 2 of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention specifies the arrangement of each component as follows. It is not what you do. The technical idea of the present invention can be variously modified within the scope of the claims.

Example 1
Embodiment 1 of the present invention describes an example in which the present invention is applied to a semiconductor device including a plurality of semiconductor elements using a field effect transistor (FET) having a super junction structure as a semiconductor element. . Here, the plan view shown in FIG. 3 is obtained by extracting a characteristic configuration for easy understanding of the planar shapes of the p-type base region and the electric field relaxation region, and is not particularly relevant in this description. The configuration is omitted.

[Structure of semiconductor device]
As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment includes a cell region 2 disposed in the center, an outer peripheral region 3 disposed around the cell region 2, and an outer peripheral region 3. And an equipotential ring region 4 disposed on the outermost periphery.

(1) Structure of cell region The cell region 2 is a region where a plurality of semiconductor elements (FETs) 6 having a super junction structure are formed.

  As shown in FIGS. 1 to 3, the cell region 2 includes a substrate 11, an n − type drift region (corresponding to the first conductivity type region according to the claims) 12, and a plurality of p − type columnar regions (claims). 13 corresponding to the first columnar region), a p-type base region 14, an n-type source region 15, a gate electrode 16, a gate insulating film 17, a source electrode 18, and a drain electrode 19. ing. In the following description, the substrate 11, the n − type drift region 12, the p − type columnar region 13, the p type base region 14, and the n type source region 15 may be collectively referred to as the semiconductor substrate 7.

  The substrate 11 is made of an n + type semiconductor in which a semiconductor such as silicon (Si) is doped with phosphorus (P) which is an n type impurity. Here, the n-type is the first conductivity type. The substrate 11 functions as a drain region in the first embodiment.

  The n − type drift region 12 is formed on one main surface (upper surface in FIG. 1 and FIG. 2) 11 a of the substrate 11. N − type drift region 12 has a lower impurity concentration than substrate 11.

  The p − type columnar region 13 is made of a p − type semiconductor in which a semiconductor such as silicon (Si) is doped with boron (B) which is a p type impurity. Here, the p-type is the second conductivity type. The p − type columnar region 13 is formed inside the n − type drift region 12. The p − type columnar region 13 is formed so as to extend in the vertical direction in FIG. 1 and FIG. 2, that is, in the thickness direction of the substrate 11.

  As shown in FIG. 3, the p − -type columnar region 13 has a dot-like planar shape in plan view (as viewed from the vertical direction on the surface of the semiconductor substrate 7). The distances (pitch) D between one p-type columnar region 13 and another one p-type columnar region 13 adjacent thereto are all arranged to be equal. The distance D here is the distance between the centers of adjacent p-type columnar regions 13. The depth, impurity concentration, and width (plane area) of each p − type columnar region 13 are all made equal. In order to realize such a planar structure and a cross-sectional structure, the planar shape of the p-type columnar region 13 according to the first embodiment is set to a hexagonal shape. The distances D between one p-type columnar region 13 and a plurality of (here, six) p-type columnar regions 13 adjacent to the periphery thereof are all equal. The planar shape of the p-type columnar region 13 and the like shown in FIG. 3 is drawn in a hexagonal shape with a sharp apex for convenience, but in an actual product, the diffusion of impurities proceeds isotropically so that the apex angle It becomes a rounded hexagonal shape. In Example 1, such a shape is equivalent to a hexagonal shape.

  In the cell region 2, as shown in FIG. 3, a plurality of p-type columnar regions 13 are regularly arranged in the first direction and in the second direction intersecting with the first direction. The arrangement of the p − type columnar regions 13 is a basic arrangement of the semiconductor elements 6. In the first embodiment, the first direction corresponds to the X direction of the coordinate axis described for convenience, and the second direction is the Y direction orthogonal to the X direction. As described above, since the planar shape of the p-type columnar region 13 in Example 1 is a hexagonal shape, another one adjacent to the one p-type columnar region 13 in the first direction. The p-type columnar region 13 is arranged in a direction inclined 30 degrees upward in FIG. 3 from the first direction, and another one adjacent to the other one p-type columnar region 13 in the first direction. The p-type columnar region 13 is arranged in a direction inclined 30 degrees from the first direction to the lower side in FIG. Although the p-type columnar regions 13 are microscopically arranged in a zigzag manner in the first direction, the p-type columnar regions 13 are large in number, and are macroscopically arranged substantially linearly in the first direction. Take shape.

  Similarly, another p-type columnar region 13 adjacent to one p-type columnar region 13 in the second direction is linearly arranged in the second direction. Although the p-type columnar regions 13 are microscopically arranged in a first direction with a part of the hexagonal apex angle being uneven, the number of arrangements is large, and the second direction is almost macroscopically. And the other side of the cell region 2 is formed.

  The p-type base region 14 is made of a p-type semiconductor. The impurity concentration of the p-type base region 14 is higher than the impurity concentration of the p-type columnar region 13. The p-type base region 14 is formed by being bonded to the upper part of the p-type columnar region 13 (electrically connected without having a pn junction). At least a part of the upper surface of the p-type base region 14 is exposed to one main surface 7 a of the semiconductor substrate 7. As shown in FIG. 3, the p-type base region 14 is formed in a dot shape in plan view. The distances (pitch) between one p-type base region 14 and another adjacent p-type base region 14 are all equal. The depth, impurity concentration, and width of each p-type base region 14 are all made equal. In order to realize such a planar structure and a cross-sectional structure, the p-type base region 14 according to the first embodiment is set to a hexagonal shape similarly to the planar shape of the p-type columnar region 13, and the p-type columnar region is formed. It is composed of a similar shape centered on 13 and slightly larger than that.

  The n-type source region 15 is formed in an island shape inside each p-type base region 14. At least a part of the upper surface of the n-type source region 15 is exposed on one main surface 7 a of the semiconductor substrate 7.

  The gate electrode 16 is made of polycrystalline silicon in the first embodiment. The gate electrode 16 is formed in a mesh shape in plan view. The end of the gate electrode 16 is connected to a gate terminal (not shown).

  The gate electrode 16 is disposed so as to straddle between the n-type source regions 15 of the adjacent p-type base regions 14 with the n − -type drift region 12 interposed therebetween. With such an arrangement, a channel is formed in the surface portion of the p-type base region 14 in a region facing the gate electrode 16 according to the voltage supplied to the gate electrode 16.

  The gate insulating film 17 is formed between the semiconductor substrate 7 and the gate electrode 16 and electrically insulates the semiconductor substrate 7 and the gate electrode 16. The gate insulating film 17 is made of, for example, a silicon oxide film.

  The source electrode 18 injects electrons into the n-type source region 15. The source electrode 18 is electrically connected to the p-type base region 14 and the n-type source region 15 by ohmic contact.

  The drain electrode 19 is electrically connected to the other main surface 11 b facing the main surface 11 a of the substrate 11 by ohmic contact.

  Here, although the entire layout of the cell region 2 is not particularly illustrated, the semiconductor elements 6 are arranged in a matrix in the first direction and the second direction in a plan view, and the cell region 2 is macroscopically rectangular. It has a planar shape.

(2) Structure of outer peripheral region The outer peripheral region 3 is formed so as to surround the outer periphery of the cell region 2. The outer peripheral region 3 has a function of improving the breakdown voltage. As shown in FIGS. 1 and 3, along each side of the outer peripheral region 3 arranged along the first direction (X direction) and the second direction (Y direction), that is, the cell region 2 having a square shape. The arranged outer peripheral region 3 includes a substrate 11, an n − type drift region 12, a plurality of p − type columnar withstand voltage improvement regions 23 n (n = 1, 2,...), And a p type electric field relaxation region 24 n (n = 1, 2,...) And an insulating film 27. The p-type columnar breakdown voltage improving region 23n corresponds to the second columnar region according to the claims. In addition, in the component of the outer periphery area | region 3, the same code | symbol is attached | subjected to the component which has a function equivalent to the component of the cell area 2, or the same component, and the description of the overlapping component is abbreviate | omitted.

  The p-type columnar breakdown voltage improving region (hereinafter simply referred to as “p-type columnar region”) 23 n in the outer peripheral region 3 is the same component as the p-type columnar region 13 in the cell region 2. That is, the distance D between one p-type columnar region 23n and another p-type columnar region 23n adjacent in the first direction or the second direction, and the distance between one p-type columnar region 23n and the outer peripheral region 3 The distance D between the other adjacent p-type columnar regions 23n + 1 arranged from the inner side (cell region 2 side) to the outer side (outermost peripheral side) is the same as the distance D between the p-type columnar regions 13. . The p-type columnar regions 23n are all arranged to have the same distance D. The depth, impurity concentration, and width of each p-type columnar region 23n are configured to be equal to those of the p-type columnar region 13.

  By adopting such a structure, the ratio of the charge in the n − type drift region 12 in the outer peripheral region 3 and the charge in the p − type columnar region 23 n (hereinafter simply referred to as “charge ratio”) is the cell region 2. It becomes equal to the charge ratio between the n − type drift region 12 and the p − type columnar region 13.

  The p-type electric field relaxation region 24n is made of a p-type semiconductor. The impurity concentration of the p-type field relaxation region 24 n is set to be equal to the impurity concentration of the p-type base region 14 of the cell region 2. The p-type electric field relaxation region 24n is formed to be coupled to the upper portion of the p-type columnar region 23n (electrically connected without having a pn junction). The upper surface of the p-type electric field relaxation region 24n exists on the one main surface 7a side of the semiconductor substrate 7, and is in direct contact with the insulating film 27 or indirectly through a natural oxide film. Similar to the planar shape of the p-type base region 14 of the cell region 2, the p-type electric field relaxation region 24n has a dot-shaped planar shape in plan view as shown in FIG. In Example 1, the planar shapes of the p − type columnar region 23 n and the p type electric field relaxation region 24 n in the outer peripheral region 3 are the planes of the p − type columnar region 13 and the p type base region 14 in the cell region 2, respectively. Like the shape, it is set to a hexagonal shape.

  From the distance D between one p-type field relaxation region 24n and another p-type field relaxation region 24n adjacent in the first direction or the second direction, and from the inside of one p-type field relaxation region 24n and the outer peripheral region 3 All the distances D to one other adjacent p-type field relaxation region 24n + 1 arranged outside are equal. Here, the distance D is the distance between the centers of adjacent p-type electric field relaxation regions 24n in plan view.

  As shown in FIG. 1, the width Wn (n = 1, 2,...) Of the p-type field relaxation region 24n is formed so as to gradually decrease from the inner side to the outer side of the outer peripheral region 3. That is, the width Wn can be expressed as the following formula (1).

W1>W2>W3> W4 (1)
Note that the width Wn referred to here is one end of the p-type electric field relaxation region 24n (pn junction surface with the n− type drift region 12) in the direction from the inner side to the outer side of the outer peripheral region 3 and the other end (n -Pn junction plane with the drift region 12). For example, the width Wn is set so that the dimension decreases every 10% so that “width W1 × 0.9 = width W2” and “width W2 × 0.9 = width W3”. Thereby, the interval Sn (n = 1, 2,...) Between one p-type field relaxation region 24n inside the outer peripheral region 3 and another one p-type field relaxation region 24n + 1 adjacent to the outside is from the inside to the outside. Gradually grows as you approach. That is, the interval Sn can be expressed as the following formula (2).

S1 <S2 <S3 (2)
The depth of the p-type electric field relaxation region 24n is formed so as to gradually become shallower from the inside toward the outside. The p-type electric field relaxation regions 24n are formed so that the impurity concentrations are all substantially equal.

  The insulating film 27 is made of, for example, a silicon oxide film. The insulating film 27 is formed so as to cover the main surface 7 a of the semiconductor substrate 7 in the outer peripheral region 3.

  The equipotential ring region 4 is configured so as to surround the outer periphery of the outer peripheral region 3 and is disposed in the outermost peripheral region of the semiconductor substrate 7. As shown in FIG. 1, the equipotential ring region 4 has a ring electrode 31 surrounding the outer peripheral region 3. The ring electrode 31 is connected to the n − type drift region 12. Thereby, the equipotential ring region 4 has a function of suppressing the extension of the depletion layer to the side surface of the semiconductor substrate 7 and a function of stabilizing the charge charged on the surface of the insulating film 27.

(3) Operation of Cell Region and Peripheral Region (Area Excluding Corner Region) of Semiconductor Device The operation of the semiconductor device 1 shown in FIGS. 1 and 3 is as follows.

  First, the operation when the semiconductor element (FET) 6 is turned on is as follows. A voltage is applied between the drain electrode 19 and the source electrode 18 such that the potential of the drain electrode 19 is higher than the potential of the source electrode 18. In this state, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 16, carriers (in this case, electrons are electrons) are accumulated in the p-type base region 14 in a region facing the gate electrode 16. As a result, a channel is formed near the upper surface of the p-type base region 14. Carriers (electrons) injected from the source electrode 18 flow to the drain electrode 19 through the n-type source region 15, the channel of the p-type base region 14, the n − -type drift region 12, and the substrate 11. Note that current flows from the drain electrode 19 to the source electrode 18.

Next, the operation when the semiconductor element 6 is in the off state is as follows. In the off state, a depletion layer spreads not only between the p-type columnar regions 13 of the cell region 2 but also between the p-type columnar regions 23n of the outer peripheral region 3. Thereby, the outer periphery area | region 3 functions in the outer periphery of the cell area | region 2, and can suppress electric field concentration. Further, in the outer peripheral region 3, the width Wn of the p-type electric field relaxation region 24 n is configured to become smaller as it approaches the outer side from the inner side of the outer peripheral region 3. For this reason, the depletion layer spreads further to the outer side of the outermost p-type columnar region 23 n (p-type columnar region 23 ₄ shown in FIG. 1) of the outer peripheral region 3, and is depleted as it approaches the outer side of the outer peripheral region 3. The layer thickness gradually decreases. Thereby, an electric field can be relieved also on the outer side of the outer periphery area | region 3, and an electric field concentration can be suppressed. Accordingly, since the leakage current can be suppressed outside the outer peripheral region 3, the breakdown voltage of the semiconductor device 1 can be improved.

(4) Structure of the outer peripheral region of the corner region of the cell region The outer peripheral region 3 surrounding the outer periphery in the corner region of the cell region 2 is basically the structure of the outer peripheral region 3 arranged along each side of the cell region 2. A similar structure is provided, but a structure that further improves the breakdown voltage is provided. As shown in FIGS. 2 and 3, the outer periphery region 3 disposed in the corner region where the first direction (X direction) and the second direction (Y direction) intersect, that is, the corner of the cell region 2 having a square shape. The outer peripheral region 3 disposed in the region is the same as the outer peripheral region 3 except for the substrate 11, the n − type drift region 12, and a plurality of p − type columnar regions 23 n (n = 1, 2,...). A p-type electric field relaxation region 24n (n = 1, 2,...) And an insulating film 27.

  In the corner region, the number of p-type columnar regions 23n and p-type electric field relaxation regions 24n arranged from the inner side toward the outer side of the outer peripheral region 3 is from the inner side to the outer side of the outer peripheral region 3 in the region other than the corner region. The number of the p-type columnar regions 23n and the p-type electric field relaxation regions 24n arranged in the direction is set to be large.

In the first embodiment, in the region other than the corner region, the second column of the p-type columnar region 23 ₂ and the p-type electric field relaxation region 24 ₂ and the third column of the p-type from the inner side toward the outer side of the outer peripheral region 3. the pillar region 23 ₃ and the p-type electric field relaxation region 24 ₃ are arranged one each pair. On the other hand, in the corner region, the p-type columnar region 23 _{2 (1)} and the p-type electric field relaxation region 24 _{2 (1)} are arranged in the second row from the inner side to the outer side of the outer peripheral region 3. A p-type columnar region 23 _{2 (2)} and a p-type electric field relaxation region 24 _{2 (2)} having the same structure and size as the second column are arranged in the column, and the p-type columnar region 23 ₃ is arranged in the fourth column. ₍₁₎ and the p-type electric field relaxation region 24 _{3 (1)} are arranged, and the p-type columnar region 233 ₍₂₎ and the p-type electric field relaxation region 24 having the same structure and the same size as the fourth row are arranged in the fifth row. _{3 (2)} is provided. That is, in the region other than the corner region, the column region corresponding to the p-type columnar region 23n and the p-type electric field relaxation region 24n arranged in the second and third columns of the outer peripheral region 3 is divided into two columns in the corner region. A p-type columnar region 23n and a p-type electric field relaxation region 24n which are increased by two rows from the fifth row to the fifth row are provided. The p-type columnar region 23n and the p-type electric field relaxation region 24n in the second row and the third row have the structure and the manufacturing method of the semiconductor device 1 without newly setting or adjusting the depth, impurity concentration, width, and the like. In order to be able to realize simply, it is comprised by the same structure and the same size. The p-type columnar region 23n and the p-type electric field relaxation region 24n in the fourth and fifth rows are configured for the same purpose. In the corner region, the width dimensions W1 to W6 of the first to sixth columns, particularly the p-type field relaxation regions 24n, may be gradually decreased from the inner side to the outer side of the outer peripheral region 3.

  In the corner region, the cross-sectional structure and the planar structure of the p-type columnar region 23n in the outer peripheral region 3 are the same as the cross-sectional structure and the planar structure of the p-type columnar region 23n in the outer peripheral region 3 other than the corner region. That is, the distance D between one p-type columnar region 23n and one other p-type columnar region 23n adjacent in the first direction or the second direction is the same distance. Further, the depth, impurity concentration, and width of each p − type columnar region 23n are the same.

  By adopting such a structure, even in the corner region, the charge ratio between the charge in the n − type drift region 12 in the outer peripheral region 3 and the charge in the p − type columnar region 23 n is equal to the n − type drift in the cell region 2. It becomes equal to the charge ratio between the region 12 and the p-type columnar region 13.

  In the corner region, the impurity concentration of the p-type field relaxation region 24 n in the outer peripheral region 3 is set to be equal to the impurity concentration of the p-type base region 14 in the cell region 2. In Example 1, the planar shapes of the p-type columnar region 23n and the p-type electric field relaxation region 24n in the outer peripheral region 3 of the corner region are the p-type columnar region 13 and the p-type base region 14 in the cell region 2, respectively. The hexagonal shape is set similarly to the respective planar shapes.

  From the distance D between one p-type field relaxation region 24n and another p-type field relaxation region 24n adjacent in the first direction or the second direction, and from the inside of one p-type field relaxation region 24n and the outer peripheral region 3 All the distances D to one other adjacent p-type field relaxation region 24n + 1 arranged outside are equal.

  As shown in FIG. 2, the width Wn (n = 1, 2,...) Of the p-type field relaxation region 24n is the same width dimension in the second and third rows, the fourth row and the fifth row, respectively. As a whole, the outer peripheral region 3 is formed so as to gradually decrease from the inner side toward the outer side. That is, the width Wn can be expressed as the following formula (3).

W1> W2 = W3> W4 = W5> W6 (3)
Further, as a result, the interval Sn (n = 1, 2,...) Between one p-type electric field relaxation region 24n inside the outer peripheral region 3 and one other p-type electric field relaxation region 24n + 1 adjacent to the outer side is from the inside. Gradually grows as you approach the outside. That is, the interval Sn can be expressed as the following formula (4).

S1 <S2 <S3 <S4 <S5 (4)
The depth of the p-type electric field relaxation region 24n is the same as that of the width Wn, but the second row, the third row, the fourth row, and the fifth row have the same width dimension. Therefore, it is formed so as to become gradually shallower. The p-type electric field relaxation regions 24n are formed so that the impurity concentrations are all substantially equal.

  Here, in the corner region, the p-type columnar region 23n and the p-type electric field relaxation region 24n in the third and fifth columns (or the second and fourth columns) increased to the outer peripheral region 3 are formed on the semiconductor substrate 7. It is formed in a dead space (empty area where no element is provided). Accordingly, the breakdown voltage of the corner region of the outer peripheral region 3 can be improved without increasing the chip area of the semiconductor device 1.

  Each of the insulating film 27 and equipotential ring region 4 has the same structure as each of the insulating film 27 and equipotential ring region 4 in regions other than the corner region.

(5) Operation of Cell Region and Peripheral Region (Corner Region) of Semiconductor Device In the operation of the semiconductor device 1 shown in FIGS. 1 and 3, the operation when the semiconductor element 6 is turned on is the same as that described in (3 This is the same as the operation of turning on the semiconductor element 6 described in the section).

The operation when the semiconductor element 6 is in the off state is as follows. In the off state, a depletion layer spreads not only between the p-type columnar regions 13 of the cell region 2 but also between the p-type columnar regions 23n of the outer peripheral region 3 in the corner region and other regions. Thereby, the outer periphery area | region 3 functions in the outer periphery of the cell area | region 2, and can suppress electric field concentration. In particular, in the corner region, the number of arrangements of the p-type electric field relaxation regions 24n in the outer peripheral region 3 is increased, so that electric field concentration in this region can be suppressed. Further, the entire outer peripheral region 3 is configured such that the width Wn of the p-type electric field relaxation region 24n decreases as it approaches the outer side from the inner side of the outer peripheral region 3. Therefore, the depletion layer extends to the outer side of the outermost p-type columnar region 23n (p-type columnar region 23 ₄ shown in FIGS. 1 and 2) of the outer peripheral region 3 and approaches the outer side of the outer peripheral region 3. Along with this, the thickness of the depletion layer gradually decreases. Thereby, an electric field can be relieved also on the outer side of the outer periphery area | region 3, and an electric field concentration can be suppressed. Accordingly, since the leakage current can be suppressed outside the outer peripheral region 3, the breakdown voltage of the semiconductor device 1 can be improved.

[Method for Manufacturing Semiconductor Device]
The manufacturing method of the semiconductor device 1 according to the first embodiment described above is as follows. First, as shown in FIG. 4, a first n − type drift region layer 35 a is formed on the main surface 11 a of the substrate 11 using an epitaxial growth method.

  Next, as shown in FIG. 5, a resist film 36 in which openings 36a having a desired pattern are formed is formed on the upper surface of the n − -type drift region layer 35a. Here, the opening 36 a of the resist film 36 is disposed corresponding to a region where the p − type columnar region 13 of the cell region 2 and the p − type columnar region 23 n of the outer peripheral region 3 are formed. All the openings 36a are formed in the same shape. Further, the distance (pitch) between one opening 36a and another adjacent opening 36a, here, the distances D are all equal. Using this resist film 36, p-type impurities are introduced into n − type drift region layer 35a through opening 36a, and p type impurity region 37a is formed in n − type drift region layer 35a. An ion implantation method is used to introduce the p-type impurity. Here, the p-type impurity amount (ion implantation amount) introduced using the ion implantation method is set uniformly on the surface of the n − -type drift region layer 35a. Thereby, the amount of p-type impurity introduced to form all the p-type impurity regions 37a is made uniform. Thereafter, the resist film 36 is removed.

  Next, as shown in FIG. 6, a second n-type drift region layer 35b is formed on the upper surface of the first n-type drift region layer 35a using an epitaxial growth method. Thereafter, a resist film 38 having an opening 38a having a desired pattern is formed on the upper surface of the n − -type drift region layer 35b. Using this resist film 38, p-type impurities are introduced into n − -type drift region layer 35b through opening 38a, and p-type impurity region 37b is formed. An ion implantation method is used to introduce the p-type impurity as described above. Thereafter, the resist film 38 is removed.

  Next, as shown in FIG. 7, the same process is repeated a desired number of times, for example, four times. Thereby, n − type drift region layer 35c to n − type drift region layer 35f are similarly formed using the epitaxial growth method, and p type impurity region 37c to p type impurity region 37f are formed in each drift layer. .

  Next, the uppermost n − -type drift region layer 35g is formed using an epitaxial growth method. Note that no p-type impurity region is formed in the uppermost n − -type drift region layer 35g. When the uppermost n − type drift region layer 35g is formed, the n − type drift region 12 is completed.

  Next, heat treatment is performed, and as shown in FIG. 8, p-type impurities in p-type impurity regions 37 a to 37 f formed in the respective drift layers are diffused, and p − is diffused into n − -type drift region 12 in cell region 2. The − type columnar region 13 is formed, and the p − type columnar region 23 n is formed in the n − type drift region 12 in the outer peripheral region 3. Here, since all the p-type impurity regions 37a to 37f are formed under the same conditions, each of the p − -type columnar regions 13 and 23n has the same depth and the same width in both the cell region 2 and the outer peripheral region 3. (Plane area), formed with the same p-type impurity amount. The distance D between the p-type columnar region 13 of the cell region 2 and another p-type columnar region 13 adjacent thereto is equal to the p-type columnar region 23n of the outer peripheral region 3 and other p-type columnar regions adjacent thereto. The distance D is the same as the distance D to the region 23n.

  Next, a resist film 39 having an opening 39a having a desired pattern is formed on the surface of the n − -type drift region 12 (see FIG. 9). Here, the distance (pitch) between one opening 39a and another opening 39a adjacent thereto is the same regardless of the cell region 2 and the outer peripheral region 3. On the other hand, the width of the opening 39 a formed in the outer peripheral region 3 is formed so as to decrease as it approaches the outer side from the inner side of the outer peripheral region 3. Thereby, the space | interval between the opening parts 39a formed in the outer peripheral area | region 3 becomes large as it approaches an outer side. The widths of the openings 39a formed in the cell region 2 are all equal.

  A p-type impurity is introduced into the surface portion of the n − -type drift region 12 using the resist film 39. An ion implantation method is used to introduce the p-type impurity. Thereafter, the introduced p-type impurity is diffused to form a p-type base region 14 in the cell region 2 and a p-type electric field relaxation region 24n in the outer peripheral region 3 as shown in FIG. When this step is completed, the semiconductor substrate 7 is almost completed.

  Here, the shapes of the p-type base region 14 and the p-type electric field relaxation region 24n are formed based on the shape of the opening 39a of the resist film 39, that is, the width of the opening 39a. Specifically, in the cell region 2, all the p-type base regions 14 are formed with the same width dimension. Further, the distances D between one p-type base region 14 and one other p-type base region 14 adjacent thereto are all equal.

  On the other hand, in the outer peripheral region 3, the width Wn of the p-type electric field relaxation region 24 n is formed so as to decrease from the inner side to the outer side of the outer peripheral region 3. As a result, the distances D between one p-type field relaxation region 24n and one other p-type field relaxation region 24n adjacent thereto are all equal, but one p-type field relaxation region 24n and the other one adjacent thereto. The distance Sn between the two p-type electric field relaxation regions 24n + 1 increases as the distance from the inner side to the outer side of the outer peripheral region 3 increases.

  Then, each structure of the upper layer of the semiconductor substrate 7 and the drain electrode 19 is formed using known processes such as a vapor deposition method, a photolithography method, an etching method, and a lift-off method. Thereby, the semiconductor device 1 according to the first embodiment shown in FIGS. 1 to 3 is completed.

[Features of semiconductor devices]
In the semiconductor device 1 according to the first embodiment, the following effects are obtained. First, the semiconductor device 1 according to the first embodiment is configured such that the width Wn of the p-type electric field relaxation region 24n in the outer peripheral region 3 decreases as it approaches the outer side from the inner side of the outer peripheral region 3. When a reverse voltage is applied to the semiconductor device 1, a depletion layer generated in the peripheral region 3 disposed along each side of the cell area 2 of the outermost peripheral region 3 p-type pillar region 23 ₄ The thickness of the depletion layer spreads to the outside and gradually decreases as it approaches from the inside to the outside of the outer peripheral region 3. Therefore, in the semiconductor device 1, since the electric field can be relaxed and the electric field concentration can be suppressed, the leakage current can be suppressed in the cell region 2 and the outer peripheral region 3 even when a reverse voltage is applied. As a result, the breakdown voltage of the semiconductor device 1 can be improved.

Furthermore, in the semiconductor device 1 according to the first embodiment, the number of p-type electric field relaxation regions 24n arranged in the corner region of the cell region 2 from the inner side to the outer side of the outer peripheral region 3 is equal to each side of the cell region 2. The number of p-type electric field relaxation regions 24n arranged from the inner side to the outer side of the outer peripheral region 3 is set to be larger than that of the outer peripheral region 3. Thus, particularly in the corner regions of the electric field concentration tends to occur cell area 2, it is possible to increase further more the spread of the depletion layer to the outside of the outermost p- type columnar region 23 ₄ of the peripheral region 3, and the depletion The thickness of the layer gradually decreases as it approaches from the inner side to the outer side of the outer peripheral region 3. Therefore, in the semiconductor device 1, the electric field concentration can be suppressed by relaxing the electric field in the corner region of the cell region 2, so that the cell region 2 and the outer peripheral region 3 are all applied even when a reverse voltage is applied. Leakage current can be suppressed. As a result, the breakdown voltage of the semiconductor device 1 can be further improved. In addition, since the number of arrangements of the p-type field relaxation regions 24n in the corner region is increased by utilizing dead space, it is not necessary to expand the area of the semiconductor substrate 7, and the degree of integration of the semiconductor device 1 is improved. be able to.

  In the semiconductor device 1 according to the first embodiment, since the breakdown voltage can be improved by reducing the width Wn of the p-type field relaxation region 24n from the inside toward the outside, the p-type field relaxation region can be improved. All the distances D between 24n and other electric field relaxation regions 24n + 1 adjacent thereto can be set to be the same. Accordingly, the distance D between the p-type columnar region 13 of the cell region 2 and another p-type columnar region 13 adjacent thereto, and the p-type columnar region 23n of the outer peripheral region 3 and other p adjacent thereto. The distance D to the mold columnar region 23n can be set to be the same. Thus, the depth and width (plane area) of all the p-type columnar regions 13 and 23n regardless of whether or not the cell region 2 and the outer peripheral region 3 are corner regions of the outer peripheral region 3. Can be equal. Furthermore, the p-type columnar regions 13 and 23n can be formed in the same process with the same ion implantation amount, and the p-type impurity amounts of all the p-type columnar regions 13 and 23n can be easily set to be the same. it can. As a result, the charge ratio between the n − type drift region 12 and the p − type columnar region 13 in the cell region 2 is equal to the charge ratio between the n − type drift region 12 and the p − type columnar region 23 n in the outer peripheral region 3. Thus, the breakdown voltage of the semiconductor device 1 can be improved. That is, in the semiconductor device 1, the breakdown voltage can be improved while simplifying the structure and the manufacturing process.

  In the semiconductor device 1 according to the first embodiment, each of the p-type electric field relaxation regions of the outer peripheral region 3 disposed on each side of the cell region 2 and the outer peripheral region 3 disposed in the corner region of the cell region 2. As 24n approaches from the inside to the outside, it is formed shallower gradually. Thereby, since the thickness of a depletion layer becomes smaller moderately, an electric field relaxation function can be improved further. As a result, the breakdown voltage of the semiconductor device 1 can be further improved.

[Verification by potential distribution simulation]
Next, the verification results of the simulation of the potential distribution carried out in order to verify the effect of the semiconductor device 1 according to Example 1 described above are as follows.

  A potential distribution simulation is performed on the semiconductor device 1 according to the first embodiment and the semiconductor device according to the first comparative example and the semiconductor device according to the second comparative example for comparison with the semiconductor device 1 according to the first embodiment. It was.

  In the semiconductor device 1 according to the first embodiment, the number of the p-type columnar regions 23n and the p-type electric field relaxation regions 24n in the outer peripheral region 3 is increased as described above. The withstand voltage of the semiconductor device 1 according to the first embodiment is 800V.

  In the semiconductor device according to the first comparative example, all the p-type field relaxation regions 24n are configured to have substantially the same size as the p-type field relaxation region 24n having the largest size of the semiconductor device 1 according to the first embodiment. In the semiconductor device according to the first comparative example, the number of arrangement of the p-type columnar region 23n and the p-type field relaxation region 24n in the outer peripheral region is the p-type columnar region in the outer peripheral region 3 of the semiconductor device 1 according to the first embodiment. 23n and the number of arrangement of the p-type electric field relaxation region 24n are the same.

  In the semiconductor device according to the second comparative example, all the p-type field relaxation regions 24n are configured to have substantially the same size as the smallest p-type field relaxation region 24n of the semiconductor device 1 according to the first embodiment. Here, the width of the p − type columnar region 23n and the width of the electric field relaxation region 24n are substantially the same. Note that the number of arrangement of the p-type columnar regions 23n and the p-type field relaxation regions 24n in the outer peripheral region of the semiconductor device according to the second comparative example is the p-type columnar region in the outer peripheral region 3 of the semiconductor device 1 according to the first embodiment. 23n and the number of arrangement of the p-type electric field relaxation region 24n are the same.

  10 is a simulation result of potential distribution of the semiconductor device 1 according to the first embodiment, FIG. 11 is a simulation result of potential distribution of the semiconductor device according to the first comparative example, and FIG. 12 is a potential of the semiconductor device according to the second comparative example. Distribution simulation results are shown respectively. 10 to 12, a wavy line indicates an equipotential line, a solid line denoted by reference numeral 23n indicates a p-type columnar region 23n of the outer peripheral region 3, and a solid line denoted by reference numeral 24n indicates an n-type electric field relaxation region 24n. ing. FIG. 13 is a graph showing the relationship between the reverse voltage and the leakage current in the semiconductor device 1 according to Example 1, the semiconductor device according to the first comparative example, and the semiconductor device according to the second comparative example.

  As shown in FIG. 10, in the semiconductor device 1 according to the first embodiment, equipotential lines extend to the outer side of the outermost p − type columnar region 23 n and the electric field relaxation region 24 n of the outer peripheral region 3. In the semiconductor device 1 according to the first embodiment, the interval between the outermost equipotential lines in the outer peripheral region 3 is wider than the equipotential lines at the same location of the semiconductor device according to the first comparative example, and the electric field concentration is reduced Has been. In the semiconductor device 1 according to the first embodiment, the thickness of the outermost depletion layer in the outer peripheral region 3 is gradually reduced. As a result, as shown in FIG. 13, the semiconductor device 1 according to Example 1 has a higher breakdown voltage than the semiconductor devices according to the first comparative example and the second comparative example, and the breakdown voltage can be improved. it can.

  On the other hand, as shown in FIG. 11, in the semiconductor device according to the first comparative example, equipotential lines extend to the outside of the outermost p-type columnar region 23n and the electric field relaxation region 24n of the outer peripheral region. However, on the outermost side of the outer peripheral region, the equipotential lines are small and electric field concentration occurs. As a result, in the semiconductor device according to the first comparative example, the leakage current easily flows in the outermost region of the outer peripheral region, and the breakdown voltage is lower than that of the semiconductor device 1 according to the first embodiment as shown in FIG. Become.

  As shown in FIG. 12, in the semiconductor device according to the second comparative example, the equipotential lines do not extend to the outermost p − type columnar region 23n and the electric field relaxation region 24n of the outer peripheral region. Thereby, in the semiconductor device according to the second comparative example, a leak current easily flows in the vicinity of the cell region, and the breakdown voltage is lower than that of the semiconductor device 1 according to the first embodiment as shown in FIG.

  Thus, in the semiconductor device 1 according to Example 1, the breakdown voltage can be improved as compared with the semiconductor devices according to the first comparative example and the second comparative example.

[Results of measuring the pressure resistance of the outer peripheral area]
Next, the breakdown voltage measurement results performed to verify the effects of the semiconductor device 1 according to Example 1 are as follows.

  FIG. 14 is a graph illustrating the relationship between the reverse voltage and the leakage current of the semiconductor device 1 according to the first embodiment. In FIG. 14, the horizontal axis represents the drain-source voltage (VDS), and the vertical axis represents the leakage current (ID). Document (A) is a breakdown voltage measurement result of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 according to the first embodiment shows the number of arrangements of the p-type field relaxation regions 24n in the outer peripheral region 3 in the corner region of the cell region 2. There are many. Document (B) is a breakdown voltage measurement result of the semiconductor device according to the comparative example. In the semiconductor device 1 according to the comparative example, the arrangement of the p-type electric field relaxation region 24n in the outer peripheral region 3 in the corner region of the cell region 2 and the other regions. The number is the same.

  As shown in FIG. 14, in the semiconductor device 1 (document (A)) according to the first embodiment, the number of arrangements of the p-type electric field relaxation regions 24n in the outer peripheral region 3 is increased in the corner region. The breakdown voltage can be relaxed, and the breakdown voltage can be improved as compared with the breakdown voltage of the semiconductor device (document (B)) according to the comparative example.

(Example 2)
Example 2 of the present invention describes an example in which the shape of the p-type electric field relaxation region 24n in the outer peripheral region 3 is changed in the semiconductor device 1 according to Example 1 described above.

  As shown in FIG. 15, the basic structure of the semiconductor device 1 according to the second embodiment is the same as that of the semiconductor device 1 according to the first embodiment described above, but the plane of the p-type field relaxation region 24 n in the outer peripheral region 3. The shape is a stripe shape. In the outer peripheral region 3, the planar shape of the p − type columnar region 23 n is not shown, but is configured in the same shape as the p − type columnar region 23 n of the semiconductor device 1 according to the first embodiment.

  The p-type electric field relaxation region 24n arranged along each side of the cell region 2 and arranged in the n-th column from the inner side to the outer side of the outer peripheral region 3; Each of the p-type field relaxation regions 24n arranged in the n-th column from the inside to the outside is integrally connected, and the planar shape of the p-type field relaxation region 24n in the n-th column is an elongated stripe shape. Have. The n-th p-type field relaxation region 24 n is formed in a ring shape surrounding the cell region 2.

Here, it is not necessary that all the p-type electric field relaxation regions 24n are formed in a ring shape surrounding the periphery of the cell region 2. For example, as shown in FIG. 15, each of a plurality of p-type electric field relaxation regions 242 ₍₂₎ disposed in the corner region of the cell region 2 and arranged in the third column from the inner side to the outer side of the outer peripheral region 3. Are connected integrally in the same manner, and the planar shape of the p-type field relaxation region 242 _{(2) in} the third row has a stripe shape extending elongated. The p-type electric field relaxation region 24 _{2 (2) in the} third column is disposed only in the corner region, and is formed separately from the p-type electric field relaxation region 24 _{2 (1)} connected in the ring shape. Note that the stripe-shaped p-type field relaxation region 24 _{2 (2)} shown in FIG. 15 may be connected to the ring-shaped p-type field relaxation region 24 _{2 (1)} .

  The p-type field relaxation regions 24n in the first to sixth columns having the stripe shape are basically in a floating state.

  In the semiconductor device 1 according to the second embodiment configured as described above, the same effect as that obtained by the semiconductor device 1 according to the first embodiment can be obtained.

(Other examples)
As mentioned above, although this invention was demonstrated in detail using Example 1 and Example 2, this invention is not limited to the said Example described in this specification. The technical scope of the present invention is determined by the description of the claims and the scope equivalent to the description of the claims. Hereinafter, a modified example in which a part of the above embodiment is changed will be described.

  For example, the shape, numerical value, material, and the like of each configuration of the first embodiment or the second embodiment described above can be changed as appropriate.

  In the first embodiment or the second embodiment described above, an example in which four p-type columnar regions 23n and p-type electric field relaxation regions 24n in the outer peripheral region 3 are arranged outside the corner region and six in the corner region has been described. However, the arrangement number of the p-type electric field relaxation regions 24n can be changed as appropriate.

  In the first embodiment or the second embodiment described above, the width of the p-type field relaxation region 24n is gradually reduced from the inside toward the outside, but the method of changing the width can be changed as appropriate. For example, the width of the innermost p-type field relaxation region 24n is set different from the width of the outermost p-type field relaxation region 24n, and the region where the width of the p-type field relaxation region 24n is equal is the innermost and the most. You may arrange | position between outer sides. In other words, the distance between the innermost p-type electric field relaxation region 24n and the outermost p-type electric field relaxation region 24n may be different, and there may be a region in the middle where the interval between the p-type electric field relaxation regions 24n is equal.

  In the first embodiment or the second embodiment described above, the depth of the p-type electric field relaxation region 24n is gradually decreased as it approaches from the inside to the outside, but the method of changing the depth can be changed as appropriate. is there. For example, all the depths of the p-type electric field relaxation region 24n may be the same. Further, the region where the depth of the p-type electric field relaxation region 24n is equal may be in the middle between the innermost side and the outermost side. Furthermore, the depth of the p-type electric field relaxation region 24n may be set deeper than that of the p-type base region 14.

  In the first embodiment or the second embodiment described above, the n-type drift region layer 12 is described as a stack type structure in which the p-type columnar regions 13 and 23n are formed by stacking a plurality of times. After forming a trench, the present invention can be applied to a trench structure in which a p-type columnar region embedded in the trench is formed. Also in this case, the same effect as that obtained by the semiconductor device 1 according to the first embodiment or the second embodiment described above can be obtained.

  Moreover, in Example 1 or Example 2 mentioned above, p-type and n-type are examples, and this conductivity type can be reversed.

  The present invention is widely applicable to semiconductor devices that have a simple structure and can improve the breakdown voltage of the outer peripheral region by improving the breakdown voltage of the corner region of the cell region.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Cell region 3 ... Outer peripheral region 4 ... Equipotential ring region 6 ... Semiconductor element 7 ... Semiconductor substrate 7a, 11a, 11b ... Main surface 11 ... Substrate 12 ... n-type drift region 13 ... p-type columnar shape Region 14 ... p-type base region 15 ... n-type source region 16 ... gate electrode 17 ... gate insulating film 18 ... source electrode 19 ... drain electrode 23n ... p-type columnar region 24n ... p-type electric field relaxation region 27 ... insulating film 31 ... Ring electrodes 35a-35g ... n-type drift region layers 36, 38, 39 ... resist films 36a, 38a, 39a ... openings 37a-37f ... p-type impurity region D ... distance Sn ... interval Wn ... width

Claims (7)

A cell region in which a semiconductor element is formed;
An outer peripheral region formed on the outer periphery of the cell region;
A first conductivity type region of a first conductivity type formed in the cell region and the outer peripheral region;
A plurality of first columnar regions of a second conductivity type formed in the first conductivity type region of the cell region and arranged in a first direction and a second direction intersecting with the first direction;
A plurality of second columnar regions of a second conductivity type formed in the first conductivity type region of the outer peripheral region and arranged in the first direction and the second direction;
A plurality of electric field relaxation regions of a second conductivity type formed on the second columnar region,
An interval between the electric field relaxation region and the other electric field relaxation region adjacent to the electric field relaxation region is different between the inner side and the outer side of the outer peripheral region, and the electric field relaxation region arranged along the first direction and the second direction. Arranged from the inside to the outside of the electric field relaxation region arranged in a corner region where the first direction and the second direction intersect with respect to the number arranged from the inside to the outside. A semiconductor device characterized by a large number.   In the outer peripheral region, an interval between the inner electric field relaxation region and another adjacent electric field relaxation region is smaller than an interval between the outer electric field relaxation region and another adjacent electric field relaxation region. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 2, wherein in the outer peripheral region, an interval between the electric field relaxation region and another electric field relaxation region adjacent to the electric field relaxation region is gradually increased from the inner side toward the outer side. .   4. The semiconductor device according to claim 2, wherein, in the outer peripheral region, the width of the electric field relaxation region gradually decreases from the inner side toward the outer side. 5.   5. The semiconductor device according to claim 2, wherein, in the outer peripheral region, the depth of the electric field relaxation region gradually becomes shallower from the inside toward the outside. 6.   The distance between the first columnar region adjacent to the first columnar region of the cell region is equal to the distance between the second columnar region adjacent to the second columnar region of the outer peripheral region. 6. The semiconductor device according to claim 2, wherein the semiconductor device is characterized in that:   In the outer peripheral region, two or more electric field relaxation regions arranged in the first direction and the second direction and electric field relaxation regions arranged in the corner region are connected and have a stripe shape. The semiconductor device according to claim 1.