CN103050513B - 半导体层叠结构和形成该半导体层叠结构的方法 - Google Patents

半导体层叠结构和形成该半导体层叠结构的方法 Download PDF

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CN103050513B
CN103050513B CN201110314174.1A CN201110314174A CN103050513B CN 103050513 B CN103050513 B CN 103050513B CN 201110314174 A CN201110314174 A CN 201110314174A CN 103050513 B CN103050513 B CN 103050513B
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semiconductor stacked
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梁擎擎
钟汇才
朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体结构,包括:衬底,位于所述衬底上的导体层和围绕所述导体层的电介质层;覆盖所述导体层和所述电介质层的绝缘层;形成在所述绝缘层上的栅极导体层,以及围绕所述栅极导体层的电介质层;覆盖所述栅极导体层和所述围绕栅极导体层的电介质层的绝缘层;填充有半导体材料的通道垂直穿过所述栅极导体层且该通道的底部停止在所述导体层上,在所述通道的顶部设置有用作漏/源极的导体插塞;用作源/漏极的导体插塞与所述导体层电接触,用作栅极的导体插塞与所述栅极导体层电接触。

Description

半导体层叠结构和形成该半导体层叠结构的方法
技术领域
本发明涉及一种半导体结构。更具体而言,本发明涉及一种包括场效应晶体管的半导体结构。本发明还涉及这种半导体结构及其层叠结构的制造方法。
背景技术
在当前的半导体集成电路中,垂直型场效应晶体管(垂直型FET)是一种新的集成解决方案。垂直型FET是其中的源极-漏极电流在垂直于衬底表面的通道内流动的器件,若衬底表面是水平的,则垂直型FET通常是垂直的通道,通道的顶部和底部部分是源/漏极和漏/源极。垂直型FET的一个主要优点是,不通过光刻来限定沟道长度,而是通过例如外延或层积等即使在纳米尺寸也能够提供良好的厚度控制的方法来限定。另一个优点是,垂直型FET工艺天然地适应非对称器件设计。
然而,对于垂直型FET器件而言,一个关键的问题在于如何降低寄生电阻,以及在同一结构中获得具有不同栅极长度且相互之间具有更好隔离度的垂直型FET。
因此,需要能够降低垂直型FET半导体器件的寄生电阻、在同一半导体结构中提供具有不同栅极长度且相互之间具有更好隔离度的垂直型FET器件的解决方案。
发明内容
本发明的其中一个目的是提供一种改进的半导体结构及其形成方法。
根据本发明的一个方面,提供了一种半导体结构,包括:衬底,位于所述衬底上的导体层和围绕所述导体层的电介质层;覆盖所述导体层和所述电介质层的绝缘层;形成在所述绝缘层上的栅极导体层,以及围绕所述栅极导体层的电介质层;覆盖所述栅极导体层和所述围绕栅极导体层的电介质层的绝缘层;填充有半导体材料的通道垂直穿过所述栅极导体层且该通道的底部停止在所述导体层上,在所述通道的顶部设置有用作漏/源极的导体插塞;用作源/漏极的导体插塞与所述导体层电接触,用作栅极的导体插塞与所述栅极导体层电接触。
根据本发明的另一个方面,提供了一种形成半导体结构的方法,包括:a.在衬底上形成导体层和围绕所述导体层的电介质层;b.形成覆盖所述导体层和所述电介质层的绝缘层,并在所述绝缘层上形成栅极导体层以及围绕所述栅极导体层的电介质层;c.形成覆盖所述栅极导体层和所述围绕栅极导体层的电介质层的绝缘层;d.蚀刻一垂直穿过所述栅极导体层的具有侧壁的通道,并使该通道的底部停止在所述导体层上;e.在该通道内沉积半导体材料;f.在所述通道的顶部设置用作漏/源极的导体插塞,设置用作源/漏极的导体插塞,以与所述导体层电接触,设置用作栅极的导体插塞,以与所述栅极导体层电接触。
根据本发明的另一个方面,提供了一种半导体层叠结构,其具有至少两层层叠的根据本发明第一方面所述的半导体结构,其中相邻的两层所述半导体结构中,下层半导体结构中的通道顶部所设置的导体插塞与上层半导体结构的导体层电接触,其余各导体插塞均在相互不同的位置向上延伸至所述半导体层叠结构的顶部。
根据本发明的另一个方面,提供了一种半导体层叠结构的形成方法,其包括执行根据本发明的一个方面所述的形成半导体结构的各步骤后,在已形成的半导体结构的顶部形成一层衬底层,并在该衬底层上再次执行所述的形成半导体结构的各步骤,以层叠多层半导体结构,在相邻的两层半导体结构中,使下层半导体结构中的通道顶部所设置的导体插塞与上层半导体结构的导体层电接触,并使其余各导体插塞均在相互不同的位置向上延伸至所述半导体层叠结构的顶部。
附图说明
本发明的这些和其它目的、特征和优点将会从结合附图对于本发明示例性实施例的以下详细描述中变得更为清楚明了。在附图中:
图1示出了根据本发明的示例性实施例的半导体结构的俯视图;
图2示出了根据图1的半导体结构中,依据AA’方向的横截面示意图;
图3示出了根据本发明的示例性实施例形成半导体结构的方法的第一步骤的俯视图;
图4示出了根据图3的半导体结构中,依据AA’方向的横截面示意图;
图5示出了根据本发明的示例性实施例形成半导体结构的方法的第二步骤的俯视图;
图6示出了根据图5的半导体结构中,依据AA’方向的横截面示意图;
图7示出了根据本发明的示例性实施例形成半导体结构的方法的第三步骤的俯视图;
图8示出了根据图7的半导体结构中,依据AA’方向的横截面示意图;
图9示出了根据本发明的示例性实施例形成半导体结构的方法的第四步骤的俯视图;
图10示出了根据图9的半导体结构中,依据AA’方向的横截面示意图;
图11示出了根据本发明的示例性实施例形成半导体结构的方法的第五步骤的俯视图;
图12示出了根据图11的半导体结构中,依据AA’方向的横截面示意图;
图13示出了根据本发明的示例性实施例的半导体层叠结构的横截面示意图。
具体实施方式
以下将结合附图详细描述本发明的示例性实施例。附图是示意性的,并未按比例绘制,且只是为了说明本发明的实施例而并不意图限制本发明的保护范围。在附图中,相同的附图标记表示相同或相似的部件。为了使本发明的技术方案更加清楚,本领域熟知的工艺步骤及器件结构在此省略。
首先,参照图1和图2详细描述根据本发明的示例性实施例的半导体结构。
图1示出了根据本发明示例性实施例的半导体结构的俯视图;图2示出了根据图1的半导体结构中,依据AA’方向的横截面示意图。在附图中所示的根据本发明示例性实施例的半导体结构具有左右对称性(然而形成自左向右依序排列的若干重复结构也是可能的),因此在以下描述中将着重介绍单侧的结构。
如图2所示,根据本发明示例性实施例的半导体结构包括衬底111,位于所述衬底111上的导体层121和围绕所述导体层121的电介质层122,优选的,所述导体层121可以是金属层(未示出),也可以包括金属层和形成在金属层之上的金属硅化物层131,以形成更加良好的电接触,覆盖所述导体层121和所述电介质层122的绝缘层211,形成在所述绝缘层211上的栅极导体层221,以及围绕所述栅极导体层221的电介质层222,覆盖所述栅极导体层221和所述围绕栅极导体层221的电介质层222的绝缘层311;一用作源/漏极的导体插塞611与导体层121电接触,一用作栅极的导体插塞612与栅极导体层221电接触,一填充有半导体材料511的通道401垂直穿过栅极导体层221且该通道的底部停止在导体层121上,在所述通道的顶部设置有一用作漏/源极的导体插塞613。作为实例,依水平方向延伸的衬底111可以由绝缘材料形成。例如,衬底111可以包括二氧化硅、氮化硅,或者二氧化硅和氮化硅的组合。衬底层111也可以由多层材料叠加形成。在一个实例中,各导体插塞611、612和613之间形成有可根据各导体插塞的高度不同而调整厚度的绝缘层621。
如图2所示,两个效应晶体管可以通过形成在二者之间的绝缘层211、311、621和电介质层122、222彼此隔开,各绝缘层和电介质层在水平方向上的延伸有效地保证了两个场效应晶体管之间的隔离度。用于形成导体层121和栅极导体层221的材料优选为金属,可以但不限于从以下材料构成的组中选取:钨、锗、镍、钛或钴等。围绕所述导体层121的电介质层122和围绕所述栅极导体层221的电介质层222所使用的材料为绝缘材料。绝缘层211、311、621所使用的材料可以是二氧化硅或其他常见的绝缘材料。导体插塞611、612和613所使用的材料优选为适于沉积工艺的金属,例如钨、锗、镍、钛或钴等。在一个实例中,使用高介电常数材料(例如HfO2、Si3N4、Al2O3、TiO2、ZnO或CeO2等),通过外延工艺制作通道401的侧壁402,然后在通道401内沉积半导体材料511,更好的防止了栅极导体层221和通道401内所填充的半导体材料511之间发生漏电。且通过蚀刻、外延和沉积工艺在半导体结构内部先形成栅极,因此在栅极方向上(即栅极导体层221的厚度方向上),区别于以往的使用光刻栅极的方式,能够更好地控制通道401的边缘粗糙度。作为实例,通道401内所填充的半导体材料511为P型多晶硅或N型多晶硅,因此图示的两个场效应晶体管可以(均)为N型场效应晶体管或者(均)为P型场效应晶体管。作为实例,通道401的顶部也可以形成有金属硅化物层以与源/漏极材料形成良好的电接触。
以上详述了如图1、图2所示的半导体结构,利用蚀刻、沉积和外延工艺以及它们的组合,能够得到如图1、图2所示的场效应晶体管。事实上,根据制作的需要,采用相同的工艺步骤,能够在水平方向上选取更大的衬底层,并实现更多数量的效应晶体管。
为缩小器件尺寸并能够得到不同的栅极长度,提出了一种利用大马士革工艺(DamasceneProcess)形成的,以上述半导体结构为基本结构的半导体层叠结构。
在图13所示的示例性实施例中,具有至少两层层叠的半导体结构,下层半导体结构中的通道401顶部所设置的导体插塞613与上层半导体结构的导体层121’电接触,其余各导体插塞均在相互不同的位置向上延伸至半导体层叠结构的顶部。在图13所示的半导体层叠结构中,为得到单个栅极长度的垂直型场效应管,可以使用导体插塞611’、612’、613’分别作为FET器件的源、栅、漏极(其中源极和漏极可以互换,使用通道401’作为FET器件的电流通道),也可使用导体插塞611、612、611’分别作为FET器件的源、栅、漏极(其中源极和漏极可以互换,使用通道401作为FET器件的电流通道,导体插塞611、612和611’、612’分别通过垂直于纸面的方向上的不同位置向半导体层叠结构的顶部延伸以形成4个单独的触点);为得到两个栅极长度的垂直型场效应管,可以使用导体插塞611、(612和612’)、613’分别作为FET器件的源、栅、漏极(其中源极和漏极可以互换,使用通道401、401’共同作为FET器件的电流通道,导体插塞611、612和611’、612’分别通过垂直于纸面的方向上的不同位置向半导体层叠结构的顶部延伸以形成4个单独的触点,且导体插塞612和612’等电位连接)。
为得到两个栅极长度的垂直型场效应管,在图13的基础上也可以做相应的变形,例如在其它结构保持不变的情况下,取消导体插塞612’,并使导体插塞612直接向上延伸至半导体层叠结构的顶部(即:与下层栅极导体层221和上层栅极导体层221’均电接触),以作为栅极。同样,为得到并联结构的两个垂直型场效应管,可以使用如图13右侧所示的结构,将上下层两个垂直型场效应管的两个源/漏/栅极均等电位连接,以实现并联工作。依据上述原理,可以通过上述连接方式的组合,而得到多种不同栅极长度的场效应管。
下面参照图3至图12详细描述利用大马士革工艺(DamasceneProcess)形成根据本发明的示例性实施例的半导体结构和半导体层叠结构的方法。
图3和图4示出了根据本发明的示例性实施例形成半导体器件的方法的第一步骤。在衬底111上形成导体层121和围绕所述导体层121的电介质层122,所述导体层121还可以包括金属硅化物层131。在该步骤中,可以首先沉积导体层121并进行图案化蚀刻,在蚀刻部位填充电介质以形成围绕所述导体层121的电介质层122,然后进行化学机械抛光;也可以首先沉积电介质层122并进行图案化蚀刻,在蚀刻部位填充导体以形成被电介质层122围绕的导体层121,然后进行化学机械抛光。
图5和图6示出了根据本发明的示例性实施例形成半导体器件的方法的第二步骤。形成覆盖所述导体层121和所述电介质层122的绝缘层211,并在所述绝缘层211上形成栅极导体层221以及围绕所述栅极导体层221的电介质层222。
图7和图8示出了根据本发明的示例性实施例形成半导体器件的方法的第三步骤。形成覆盖栅极导体层221和围绕栅极导体层221的电介质层222的绝缘层311。
图9和图10示出了根据本发明的示例性实施例形成半导体器件的方法的第四步骤。蚀刻垂直穿过栅极导体层221的具有侧壁402的通道401,并使该通道401的底部停止在所述导体层121上。
图11和图12示出了根据本发明的示例性实施例形成半导体器件的方法的第五步骤。在已形成的通道401内沉积半导体材料511。
图1和图2示出了根据本发明的示例性实施例形成半导体器件的方法的第六步骤。在通道401的顶部设置用作漏/源极的导体插塞613,设置用作源/漏极的导体插塞611,以与导体层121电接触,设置用作栅极的导体插塞612,以与栅极导体层221电接触。在各导体插塞611、612和613之间形成可根据各导体插塞的高度不同而调整厚度的绝缘层621。
可选地,在第四步骤中使用高介电常数材料形成所述侧壁(高介电常数材料可以为例如HfO2、Si3N4、Al2O3、TiO2、ZnO或CeO2等),然后进行第五步骤,并使用激光退火以增加结晶尺寸。
在一个实例中,围绕所述导体层121的电介质层122和围绕所述栅极导体层221的电介质层222所使用的材料优选具有较高介电常数的材料(例如HfO2、Si3N4、Al2O3、TiO2、ZnO或CeO2等),且可以在通道401的顶部也形成有金属硅化物层以与源/漏极材料形成良好的电接触。
为缩小器件尺寸(相应的,增加器件中的元件密度),并能够得到不同的栅极长度,提出了一种利用大马士革工艺(DamasceneProcess)形成的,以上述半导体结构为基本结构的半导体层叠结构。由于层叠结构是基于根据本发明示例性实施例的半导体结构以多层层叠而形成的,以下将概要性地描述该半导体层叠结构的形成方法。
在一个实例中,执行了形成根据本发明示例性实施例的半导体结构的各步骤后,在已形成的半导体结构顶部形成一第二衬底层,并在该第二衬底层上再次执行形成根据本发明示例性实施例的半导体结构的各步骤,并可依以上步骤继续层叠以获得多层半导体结构,在相邻的两层半导体结构中,使下层半导体结构中的通道顶部所设置的导体插塞与上层半导体结构的导体层电接触,由此能够获得如图13所示的双层或多层半导体层叠结构,实现了垂直型场效应晶体管的三维堆叠,可以有效缩小半导体器件尺寸(相应的,增加器件中的元件密度),并能够得到具有不同栅极长度的垂直型场效应晶体管。
需要注意的是,尽管在图13中仅示出了双层的半导体层叠结构,但本发明不限于此。本领域技术人员可以根据需要,来选择需要堆叠的层数,并选取合适的导体插塞以得到具有不同栅极长度的垂直型场效应晶体管。
尽管已经参照附图详细地描述了本发明的示例性实施例,但是这样的描述应当被认为是说明性或示例性的,而不是限制性的;本发明并不限于所公开的实施例。上面以及权利要求中描述的不同实施例也可以加以组合。本领域技术人员在实施要求保护的本发明时,根据对于附图、说明书以及权利要求的研究,能够理解并实施所公开的实施例的其他变型,这些变型也落入本发明的保护范围内。
在权利要求中,词语“包括”并不排除其他部件或步骤的存在并且“一”或“一个”并不排除复数。在相互不同的从属权利要求中陈述了若干技术手段的事实并不意味着这些技术手段的组合不能有利地加以利用。

Claims (24)

1.一种半导体层叠结构,其具有至少两层层叠的半导体结构,
每个半导体结构包括:
衬底,位于所述衬底上的导体层和围绕所述导体层的电介质层;
覆盖所述导体层和所述电介质层的第一绝缘层;
形成在所述第一绝缘层上的栅极导体层,以及围绕所述栅极导体层的电介质层;
覆盖所述栅极导体层和所述围绕栅极导体层的电介质层的第二绝缘层;
填充有半导体材料的通道垂直穿过所述栅极导体层且该通道的底部停止在所述导体层上,在所述通道的顶部设置有用作漏/源极的第一导体插塞;
用作源/漏极的第二导体插塞与所述导体层电接触,用作栅极的第三导体插塞与所述栅极导体层电接触;
其中相邻的两层所述半导体结构中,下层半导体结构中的通道顶部所设置的用作漏/源极的第一导体插塞与上层半导体结构的导体层电接触,其余各导体插塞均在相互不同的位置向上延伸至所述半导体层叠结构的顶部。
2.根据权利要求1所述的半导体层叠结构,其中所述导体层为金属层,或包括金属层和形成在金属层之上的金属硅化物层。
3.根据权利要求2所述的半导体层叠结构,其中所述金属层为钨、锗、镍、钛或钴。
4.根据权利要求1所述的半导体层叠结构,其中围绕所述导体层的电介质层所使用的材料为高介电常数材料。
5.根据权利要求1所述的半导体层叠结构,其中所述第一绝缘层和第二绝缘层所使用的材料为SiO2
6.根据权利要求1所述的半导体层叠结构,其中所述栅极导体层所使用的材料为钨、锗、镍、钛或钴。
7.根据权利要求1所述的半导体层叠结构,其中所述第一导体插塞、第二导体插塞和第三导体插塞所使用的材料为钨、锗、镍、钛或钴。
8.根据权利要求1所述的半导体层叠结构,其中所述通道的侧壁为高介电常数材料。
9.根据权利要求8所述的半导体层叠结构,其中所述高介电常数材料为HfO2、Si3N4、Al2O3、TiO2、ZnO或CeO2
10.根据权利要求1所述的半导体层叠结构,其中所述通道内所填充的半导体材料为P型多晶硅或N型多晶硅。
11.根据权利要求1所述的半导体层叠结构,其中所述通道的顶部形成有金属硅化物层。
12.一种形成半导体层叠结构的方法,其包括:
执行以下各步骤:
a.在第一衬底上形成导体层和围绕所述导体层的电介质层;
b.形成覆盖所述导体层和所述电介质层的第一绝缘层,并在所述第一绝缘层上形成栅极导体层以及围绕所述栅极导体层的电介质层;
c.形成覆盖所述栅极导体层和所述围绕栅极导体层的电介质层的第二绝缘层;
d.蚀刻一垂直穿过所述栅极导体层的具有侧壁的通道,并使该通道的底部停止在所述导体层上;
e.在该通道内沉积半导体材料;
f.在所述通道的顶部设置用作漏/源极的第一导体插塞,设置用作源/漏极的第二导体插塞,以与所述导体层电接触,设置用作栅极的第三导体插塞,以与所述栅极导体层电接触;以及
在执行步骤a-f后,在已形成的半导体结构的顶部形成第二衬底层,并在该第二衬底层上再次执行步骤a-f,以层叠多层半导体结构,在相邻的两层半导体结构中,使下层半导体结构中的通道顶部所设置的用作漏/源极的第一导体插塞与上层半导体结构的导体层电接触,并使其余各导体插塞均在相互不同的位置向上延伸至所述半导体层叠结构的顶部。
13.根据权利要求12所述的形成半导体层叠结构的方法,其中在a步骤中,首先沉积导体层并进行图案化蚀刻,在蚀刻部位填充电介质以形成围绕所述导体层的电介质层,然后进行化学机械抛光。
14.根据权利要求12所述的形成半导体层叠结构的方法,其中在a步骤中,首先沉积电介质层并进行图案化蚀刻,在蚀刻部位填充导体以形成被电介质层围绕的导体层,然后进行化学机械抛光。
15.根据权利要求12所述的形成半导体层叠结构的方法,其中在d步骤中使用高介电常数材料形成所述侧壁,然后进行e步骤,并使用激光退火以增加结晶尺寸。
16.根据权利要求15所述的形成半导体层叠结构的方法,其中所述高介电常数材料为HfO2、Si3N4、Al2O3、TiO2、ZnO或CeO2
17.根据权利要求12所述的形成半导体层叠结构的方法,其中所述导体层为金属层,或包括金属层和形成在金属层之上的金属硅化物层。
18.根据权利要求17所述的形成半导体层叠结构的方法,其中所述金属层为钨、锗、镍、钛或钴。
19.根据权利要求12所述的形成半导体层叠结构的方法,其中围绕所述导体层的电介质层所使用的材料为高介电常数材料。
20.根据权利要求12所述的形成半导体层叠结构的方法,其中所述第一绝缘层和第二绝缘层所使用的材料为SiO2
21.根据权利要求12所述的形成半导体层叠结构的方法,其中所述栅极导体层为钨、锗、镍、钛或钴。
22.根据权利要求12所述的形成半导体层叠结构的方法,其中所述第一导体插塞、第二导体插塞和第三导体插塞所使用的材料为钨、锗、镍、钛或钴。
23.根据权利要求12所述的形成半导体层叠结构的方法,其中所述通道内所填充的半导体材料为P型多晶硅或N型多晶硅。
24.根据权利要求12所述的形成半导体层叠结构的方法,其中所述通道的顶部形成有金属硅化物层。
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US5324673A (en) * 1992-11-19 1994-06-28 Motorola, Inc. Method of formation of vertical transistor
US5599724A (en) * 1992-05-21 1997-02-04 Kabushiki Kaisha Toshiba FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same

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US5599724A (en) * 1992-05-21 1997-02-04 Kabushiki Kaisha Toshiba FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same
US5324673A (en) * 1992-11-19 1994-06-28 Motorola, Inc. Method of formation of vertical transistor

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