CN103050414A - 三维集成高密度厚薄膜多芯片组件的集成方法 - Google Patents
三维集成高密度厚薄膜多芯片组件的集成方法 Download PDFInfo
- Publication number
- CN103050414A CN103050414A CN2012104928320A CN201210492832A CN103050414A CN 103050414 A CN103050414 A CN 103050414A CN 2012104928320 A CN2012104928320 A CN 2012104928320A CN 201210492832 A CN201210492832 A CN 201210492832A CN 103050414 A CN103050414 A CN 103050414A
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- ceramic substrate
- film
- integrated
- chip
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210492832.0A CN103050414B (zh) | 2012-11-28 | 2012-11-28 | 三维集成高密度厚薄膜多芯片组件的集成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210492832.0A CN103050414B (zh) | 2012-11-28 | 2012-11-28 | 三维集成高密度厚薄膜多芯片组件的集成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103050414A true CN103050414A (zh) | 2013-04-17 |
CN103050414B CN103050414B (zh) | 2016-06-29 |
Family
ID=48063013
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201210492832.0A Active CN103050414B (zh) | 2012-11-28 | 2012-11-28 | 三维集成高密度厚薄膜多芯片组件的集成方法 |
Country Status (1)
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CN (1) | CN103050414B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107658230A (zh) * | 2017-08-30 | 2018-02-02 | 广东风华高新科技股份有限公司 | 一种生瓷片及ltcc基板表面粗糙度的调控方法 |
CN108629235A (zh) * | 2017-03-21 | 2018-10-09 | 南昌欧菲生物识别技术有限公司 | 指纹识别传感器的制备方法 |
CN114364125A (zh) * | 2021-12-31 | 2022-04-15 | 中国电子科技集团公司第十四研究所 | 一种双面布置器件的厚膜混合集成电路及其生产方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5295045A (en) * | 1990-11-14 | 1994-03-15 | Hitachi, Ltd. | Plastic-molded-type semiconductor device and producing method therefor |
US20020110942A1 (en) * | 2001-01-03 | 2002-08-15 | Rf Solutions, Inc. | System and method for prototyping and fabricating complex microwave circuits |
CN101673693A (zh) * | 2009-09-22 | 2010-03-17 | 贵州振华风光半导体有限公司 | 高可靠厚膜混合集成电路键合系统及其制造方法 |
US20110080713A1 (en) * | 2009-10-06 | 2011-04-07 | Shinko Electric Industries Co., Ltd. | Interposer mounted wiring board and electronic component device |
-
2012
- 2012-11-28 CN CN201210492832.0A patent/CN103050414B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5295045A (en) * | 1990-11-14 | 1994-03-15 | Hitachi, Ltd. | Plastic-molded-type semiconductor device and producing method therefor |
US20020110942A1 (en) * | 2001-01-03 | 2002-08-15 | Rf Solutions, Inc. | System and method for prototyping and fabricating complex microwave circuits |
CN101673693A (zh) * | 2009-09-22 | 2010-03-17 | 贵州振华风光半导体有限公司 | 高可靠厚膜混合集成电路键合系统及其制造方法 |
US20110080713A1 (en) * | 2009-10-06 | 2011-04-07 | Shinko Electric Industries Co., Ltd. | Interposer mounted wiring board and electronic component device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108629235A (zh) * | 2017-03-21 | 2018-10-09 | 南昌欧菲生物识别技术有限公司 | 指纹识别传感器的制备方法 |
CN107658230A (zh) * | 2017-08-30 | 2018-02-02 | 广东风华高新科技股份有限公司 | 一种生瓷片及ltcc基板表面粗糙度的调控方法 |
CN114364125A (zh) * | 2021-12-31 | 2022-04-15 | 中国电子科技集团公司第十四研究所 | 一种双面布置器件的厚膜混合集成电路及其生产方法 |
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CN103050414B (zh) | 2016-06-29 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CB03 | Change of inventor or designer information | ||
CB03 | Change of inventor or designer information |
Inventor after: Yang Chenggang Inventor after: Su Guidong Inventor after: Hu Rui Inventor before: Yang Chenggang Inventor before: Su Guidong |
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CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: 550018 Guizhou Province, Guiyang city new North Avenue No. 238 Patentee after: Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd. Address before: 550018 Guizhou Province, Guiyang city new North Avenue No. 238 Patentee before: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR Co.,Ltd. |