CN102969357A - Transverse ultra-junction high-voltage power semiconductor device - Google Patents

Transverse ultra-junction high-voltage power semiconductor device Download PDF

Info

Publication number
CN102969357A
CN102969357A CN2012105163805A CN201210516380A CN102969357A CN 102969357 A CN102969357 A CN 102969357A CN 2012105163805 A CN2012105163805 A CN 2012105163805A CN 201210516380 A CN201210516380 A CN 201210516380A CN 102969357 A CN102969357 A CN 102969357A
Authority
CN
China
Prior art keywords
type
super
drain electrode
junction
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012105163805A
Other languages
Chinese (zh)
Other versions
CN102969357B (en
Inventor
乔明
李燕妃
章文通
吴文杰
许琬
蔡林希
陈涛
胡利志
黄健文
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201210516380.5A priority Critical patent/CN102969357B/en
Publication of CN102969357A publication Critical patent/CN102969357A/en
Application granted granted Critical
Publication of CN102969357B publication Critical patent/CN102969357B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention discloses a transverse ultra-junction high-voltage power semiconductor device, and belongs to the technical field of power semiconductor devices. The transverse ultra-junction high-voltage power semiconductor device comprises a longitudinal ultra-junction cellular structure, a terminal structure and a drain lead-out structure, wherein the terminal structure is positioned at the outer side or the periphery of the entire cellular structure, and the drain lead-out structure is positioned at the outer side or the periphery of the terminal structure. The conduction resistance is reduced when puncture voltage is increased by the longitudinal ultra-junction cellular structure. Compared with the conventional transverse ultra-junction device, according to the transverse ultra-junction high-voltage power semiconductor device, a domain area is reduced by the longitudinal ultra-junction cellular structure, and the conduction resistance is further reduced. A single cell or a plurality of cells is/are integrated; a plurality of parallel cells can share a same terminal, and a drain electrode is transversely led out through the drain lead-out structure, so that the drain electrode, a grid electrode and a source electrode are formed on the surface; and not only is the device integrated with the common circuit easily, but also the domain area is greatly reduced, and the process cost is further reduced. Finally, the transverse ultra-junction high-voltage device which is led out on the surface of the drain electrode and has low conduction resistance can be integrated on various substrate materials, and is high in integration level.

Description

A kind of laterally super knot high-voltage power semiconductor device
Technical field
The invention belongs to the power semiconductor technical field, relate to a kind of laterally super knot high-voltage power semiconductor device.
Background technology
Along with developing rapidly of information technology, power MOSFET device is fast with its switching speed, be widely used without advantages such as second breakdown, negative temperature coefficient and good thermal stabilities.In the power MOS (Metal Oxide Semiconductor) device design, puncture voltage BV(Breakdown Voltage) and conduction resistance R On, spRelation very severe, fundamental relation is arranged: R On, sp∝ BV 2.5In order to solve this contradiction, a kind of Super of being called Junction(or claim Multi-RESURF or 3D RESURF) structure broken conventional power MOS device theoretical limit, keeping the advantageous while of MOS, extremely low conduction loss: R is arranged again On, sp∝ BV 1.23
Vladimir Rumennik is once in its US Patent No. 6,207,994, B1(denomination of invention: HIGH-VOLTAGETRANSISTOR WITH MULTI-LAYER CONDUCTION REGION), reported and planted the horizontal high-voltage MOSFET device with multilayer conductive district.As shown in Figure 1, the 16th, low-doped P type substrate, the 15th, P-well district, the 13rd, P +Source contact area, the 14th, N +Source contact area, the 17th, N-well district, the 19th, N +Drain contact region, 60 is first p type buried layers, 65 is second p type buried layers; P +Source contact area 13 and N +Source contact area 14 is surrounded by P-well district 15, is the second p type buried layer 65 below the P-well district 15; N +Drain contact region 19 is positioned at the upper surface in drain electrode N-well district 17, introduce many first p type buried layers 60 that vertically distribute in the drain electrode N-well district 17, so that N-well district 17 is divided into a plurality of JFET conduction regions 41, wherein, the first p type buried layer 60 can inject by energetic ion to be realized; Be field oxide 40 above the N-well district 17, an oxygen thickness is 500 nanometers ~ 1500 nanometers; Be polygate electrodes 12 above the gate oxide 36, polygate electrodes extends to N-type well region 17, forms grid polycrystalline field plate; P + Source contact area 13 and N +Be source metal 10 above the source contact area 14, the source metal extension covers polygate electrodes 12, forms the source metal field plate, and drain electrode adopts polycrystalline field plate 45 to modulate drain electrode N +The fringe field of contact zone 19 improves device electric breakdown strength.The first p type buried layer 60 in the N-well district 17 and conduction region 41 consist of horizontal super-junction structure, and during device withstand voltage, the first p type buried layer 60 and conduction region 41 exhaust mutually, and device electric breakdown strength is improved in substrate 16 assisted depletion N-well districts 17.Simultaneously, the source metal field plate of introducing, grid polycrystalline field plate and drain electrode polycrystalline field plate optimised devices surface field further improve the puncture voltage of device.Although laterally super-junction structure has been alleviated the relation of puncture voltage and conducting resistance, but tradition laterally P bar and the N bar of super knot high-voltage power MOS device " is laterally placed " along device, therefore realize that high puncture voltage requires it to be used to bear withstand voltage N-well district 17 and the first p type buried layer 60 has long size, this so that the element layout area greatly increase, increase the device conducting resistance, thereby increased manufacturing cost, limited the application of horizontal high voltage power device.
Summary of the invention
For solving existing problem in the above-mentioned prior art, the present invention proposes a kind of laterally super knot high-voltage power semiconductor device, this device comprises structure cell, terminal structure and drain electrode deriving structure, wherein, cellular adopts vertical super-junction structure, on the one hand, break the traditional silicon limit, when improving puncture voltage, reduced conducting resistance; On the other hand, compare laterally super junction device of tradition, the present invention vertically places P bar and N bar along device, has reduced chip area, further reduces conducting resistance; Again on the one hand, the present invention can adopt single or multiple cellulars integrated, a plurality of cellulars in parallel can share same terminal, and by the drain electrode deriving structure drain electrode is laterally drawn, make drain electrode, grid and source electrode all on the surface, not only be easy to custom circuit integratedly, and greatly reduce chip area, further reduce process costs; At last, the super-junction laterally high tension apparatus with low conduction resistance that draw on drain electrode of the present invention surface can be integrated on the various backing materials, and integrated level is high.
Technical solution of the present invention is:
A kind of horizontal super knot high-voltage power semiconductor device as shown in Figure 2, comprises and at least one or more than one vertically surpassing ties structure cell 11, terminal structure 12 and drain electrode deriving structure 13; A plurality of vertically super knot structure cells 11 are horizontal or Width is together tightly packed along device, form whole vertically super knot structure cell; Described terminal structure 12 is positioned at the outside or the periphery of whole structure cell, and described drain electrode deriving structure 13 is positioned at the outside or the periphery of described terminal structure 12.
Described vertically super knot structure cell 11 comprises the N that is positioned at substrate base 1 surface + Drain contact region 43 is positioned at N +Drain contact region 43 surfaces and the super-junction structure drift region that is formed by a N-type doping of two P type doping bar 32 therebetween bar 42; Lay respectively at two P type tagmas 31 on two P type doping bar 32 surfaces in the super-junction structure drift region, have in each P type tagma 31 respectively and the P that is positioned at device surface source metal 51 and links to each other + Source contact area 33 and N + Source contact area 41; The surface of N-type doping bar 42 has the grid structure that is made of gate oxide 22 and polygate electrodes 52 in the super-junction structure drift region, wherein two P type doping bars 32 of gate oxide 22 and super-junction structure drift region and N-type doping bar 42 are in contact, and mutually isolate by dielectric layer 23 between polygate electrodes 52 and the source metal.
Described terminal structure 12 comprises and is positioned at N +The terminal doped region 14 on drain contact region 43 surfaces and groove medium 21, wherein terminal doped region 14 and integral body vertically super knot structure cell link to each other but mutually isolate by groove medium 21 with drain electrode deriving structure 13, terminal doped region 14 and groove medium 21 surfaces are the dielectric layers 23 of isolating source metal 52 and drain metal 53.
Described drain electrode deriving structure 13 comprises drain electrode exit 44 and drain metal 53, and wherein said drain electrode exit 44 is realized drain metal 53 and N +The electrical connection of drain contact region 43.
Described vertically super knot structure cell 11, terminal structure 12 and drain electrode deriving structure 13 adopt common substrate base 1, and the N on substrate base 1 surface + Drain contact region 43 forms an integral body.
Laterally super knot high-voltage power semiconductor device provided by the invention comprises structure cell 11, terminal structure 12 and drain electrode deriving structure 13; Vertical super-junction structure that the drift region of primitive cell structure 11 adopts N-type doping bar of two P type doping bars, 32 folders 42 to form is alleviated the contradictory relation between puncture voltage and the conducting resistance; Shown in Figure 2, device can integrated one or more cellulars, form parallel-connection structure between a plurality of cellulars, the cellular of a plurality of parallel connections shares a terminal structure 12, and by drain electrode deriving structure 13, the drain electrode of device is laterally drawn, not only greatly reduce domain, reduce process costs, and can be integrated with custom circuit, applying flexible.
In the laterally super knot high-voltage power semiconductor device provided by the invention, grid structure can adopt planar gate, groove grid or V-arrangement grid structure.Drain electrode exit 44 can adopt N-type heavily-doped semiconductor 45, with vertical super N-type doped semiconductor 46 or the metal 54 of tying N-type doping bar 42 identical doping contents in the structure cell 11, three kinds of modes can be finished simultaneously with structure cell on technique, also can finish separately.The terminal doped region 14 of described terminal structure 12 can adopt identical with P type doping bar 32 in the vertical super knot structure cell 11 or the semiconductor of identical doping content not.Described substrate base 1 can adopt body silicon substrate, Sapphire Substrate or SOI(Silicon On Isolation) substrate.
Operation principle of the present invention can be described below:
Described laterally super knot high-voltage power semiconductor device can adopt the structures such as planar gate, groove grid or V-type grid, and the operation principle of these structures all is similar.
It is vertically withstand voltage and laterally withstand voltage that laterally super knot high-voltage power semiconductor device provided by the invention withstand voltage comprises, wherein vertically withstand voltage vertical super-junction structure by cellular determines, and is laterally withstand voltage then by 12 decisions of device lateral terminal structure.The primitive unit cell drift region is comprised of the N-type doping bar 42 that replaces and P type doping bar 32 fully.When device drain applies high voltage, P type tagma 31 begins to exhaust with the PN junction metallurgical junction face that N-type doping bar 42 consists of, increase depletion region to the expansion of N-type doping bar with drain voltage, peak electric field appears in the PN junction metallurgical junction face that P type tagma 31 and N-type doping bar 42 are consisted of.Simultaneously, the P type doping bar 32 of N-type doping bar 42 and both sides forms vertical super-junction structure, assisted depletion N-type doping bar 42, and the optimised devices longitudinal electric field, it is vertically withstand voltage to improve device.Because N-type doping bar 42 and P type doping bar 32 doping contents are higher, thereby so that its forward conduction constantly conducting resistance greatly reduce, and then improve conducting resistance and withstand voltage between contradictory relation.Device terminal structure 12 comprises terminal doped region 14 and groove dielectric layer 21, and its middle slot dielectric layer 21 is horizontal withstand voltage major parts.The terminal doped region 14 that the present invention adopts is P type doped semiconductor, this be because, drain electrode deriving structure 13, media slot and semi-conducting material consist of MIS(Metal Insulator Semiconductor) electric capacity, when drain electrode adds high pressure, MIS electric capacity makes N type semiconductor surface stored charge, but energy assisted depletion P type semiconductor, thereby the optimizing surface electric field improves the device lateral breakdown voltage.
Need to prove:
(1) laterally super knot high-voltage power semiconductor device provided by the invention, its cellular drift region adopts N-type doping bar 42 and P type doping bar 32 to form vertical super-junction structure, alleviates the contradictory relation of puncture voltage and conducting resistance.
(2) device can integrated single or multiple structure cells, the cellular of a plurality of parallel connections can share same terminal structure 12, and by drain electrode deriving structure 13 drain electrode is laterally drawn, make grid, drain electrode and source electrode all on the surface, not only be easy to custom circuit integratedly, greatly reduce simultaneously chip area.
(3) the super-junction laterally high tension apparatus can be the structures such as planar gate, groove grid or V-type grid.
(4) drain electrode exit 44 can adopt N-type heavily-doped semiconductor 45, with vertical super N-type doped semiconductor 46 or the metal 54 of tying N-type doping bar 42 identical doping contents in the structure cell 11, three kinds of modes can be finished simultaneously with structure cell on technique, also can finish separately.
(5) the terminal doped region 14 of described terminal structure 12 can adopt identical with P type doping bar 32 in the vertical super knot structure cell 11 or the semiconductor of identical doping content not.
(6) described substrate base 1 can adopt body silicon substrate, Sapphire Substrate or SOI(Silicon On Isolation) substrate.
The present invention has following beneficial effect:
Laterally super knot high-voltage power semiconductor device provided by the invention comprises vertically super knot structure cell 11, terminal structure 12 and drain electrode deriving structure 13, wherein, cellular adopts vertical super-junction structure, the power MOS (Metal Oxide Semiconductor) device theoretical limit breaks traditions, keeping the advantageous while of MOS, extremely low conduction resistance R is arranged again On, sp∝ BV 1.23With high withstand voltage.When the tradition transverse power MOS device is realized high puncture voltage, require it to be used to bear withstand voltage N-type well region 17 and have long size, this has increased process costs so that the conducting resistance of device and area increase greatly, has limited the application of horizontal high voltage power device.Adopt the present invention, the cellular of a plurality of parallel connections can share same terminal structure 12, greatly reduces the element layout area, reduces process costs.These cellulars in parallel are extremely laterally drawn element leakage by drain electrode deriving structure 13, make drain electrode, grid and source electrode all on the surface, not only are easy to custom circuit integratedly, have reduced especially chip area, reduce process costs.The exit 44 that wherein drains can adopt N-type heavily-doped semiconductor 45, with vertical super knot structure cell 11 in N-type doped semiconductor 46 or the metal 54 of N-type doping bar 42 identical doping contents, three kinds of modes can be finished simultaneously with structure cell on technique, also can finish separately, technique is simple, do not need to increase extra mask plate, further reduce process costs.Terminal structure 12 comprises terminal doped region 14 and groove dielectric layer 21, and wherein terminal doped region 14 is P type semiconductor, and it is laterally withstand voltage to adopt groove dielectric layer 21 to bear, and can further reduce chip area.Device can adopt the structures such as planar gate, groove grid or V-type grid, and its bottom is N +The drain electrode contact can be integrated on the various backing materials, such as body silicon substrate, SOI substrate or Sapphire Substrate etc.
In sum, the present invention is by adopting vertically super knot structure cell 11, terminal structure 12 and drain electrode deriving structure 13, and vertically super junction device becomes transversal device.The plurality of advantages such as it is low that this device has conducting resistance, and integrated level is high, chip area is little have reduced technology difficulty and cost.Therefore, adopt the present invention can obtain the semiconductor power device of various function admirables, have the characteristics of high speed, high integration, low conduction loss.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is laterally super knot power MOSFET device section of structure of tradition, introduces a plurality of the first p type buried layers 60 in the N-well district 17, consists of horizontal super-junction structure with the N-well district.
Fig. 2 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, the integrated a plurality of vertically super knot cellulars of device, each vertically surpasses the vertical super knot drift region structure that the knot cellular adopts N-type doping bar of two P type doping bars, 32 folders 42 to consist of.
Fig. 3 is laterally super knot high-voltage power semiconductor device structure profiles of groove grid provided by the invention, the integrated a plurality of vertically super knot cellulars of device, each vertically surpasses the vertical super knot drift region structure that the knot cellular adopts N-type doping bar of two P type doping bars, 32 folders 42 to consist of.
Fig. 4 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, and integrated one of device vertically surpasses knot structure cell 11, and its drain electrode exit 44 adopts N-type heavily-doped semiconductor 45.
Fig. 5 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, the integrated vertical super knot structure cell 11 of device, the N-type doped semiconductor 46 of N-type doping bar 42 identical doping contents in its drain electrode exit 44 employings and the vertical super knot structure cell 11.
Fig. 6 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, and integrated one of device vertically surpasses knot structure cell 11, and its drain electrode exit 44 adopts metal 54.
Fig. 7 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, integrated one of device vertically surpasses knot structure cell 11, its terminal doped region 14 can adopt three kinds of different doping way, wherein, (a) device architecture profile, dotted line frame part among terminal doped region such as the figure; (b) terminal doped region 14 adopts and vertically surpasses the P type doped semiconductor 35 of tying P type doping bar 32 identical doping contents in the structure cell 11; (c) terminal doped region 14 comprises P type doped semiconductor 35 and top and vertical super P type doped semiconductor 34 of tying P type tagma 31 identical doping contents in the structure cell 11 of P type doping bar 32 identical doping contents in below and the vertical super knot structure cell 11.(d) terminal doped region 14 comprises P type doped semiconductor 35, the centre of P type doping bar 32 identical doping contents in below and the vertical super knot structure cell 11 and vertically surpasses the P type doped semiconductor 34 of P type tagma 31 identical doping contents in the knot structure cell 11 and the P type heavily doped region 36 of top.
Fig. 8 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, and integrated one of device vertically surpasses knot structure cell 11, and its backing material is body silicon substrate 10.
Fig. 9 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, and integrated one of device vertically surpasses knot structure cell 11, and its backing material is the SOI substrate, and oxygen buried layer 20 is positioned on the body silicon substrate 10.
Figure 10 is a kind of groove grid super-junction laterally high-voltage device structure profile provided by the invention, and drain electrode exit 44 is laterally drawn the bottom drain electrode, simultaneously device is integrated on the P type body silicon substrate.(a) be device architecture profile figure; Potential profile when (b) being this device breakdown.
Embodiment
The present invention is by adopting vertically super knot structure cell 11 and lateral terminal structure 12 optimised devices conducting resistance and puncture voltages, vertically the drain electrode of super junction device is laterally drawn by drain electrode deriving structure 13, not only can be integrated with custom circuit, and greatly reduce the circuit layout area.Adopt the power device that the present invention can various function admirables, the characteristics of have high speed, high integration, hanging down conduction loss.
A kind of horizontal super knot high-voltage power semiconductor device as shown in Figure 2, comprises and at least one or more than one vertically surpassing ties structure cell 11, terminal structure 12 and drain electrode deriving structure 13; A plurality of vertically super knot structure cells 11 are horizontal or Width is together tightly packed along device, form whole vertically super knot structure cell; Described terminal structure 12 is positioned at the outside or the periphery of whole structure cell, and described drain electrode deriving structure 13 is positioned at the outside or the periphery of described terminal structure 12.
Described vertically super knot structure cell 11 comprises the N that is positioned at substrate base 1 surface + Drain contact region 43 is positioned at N +Drain contact region 43 surfaces and the super-junction structure drift region that is formed by a N-type doping of two P type doping bar 32 therebetween bar 42; Lay respectively at two P type tagmas 31 on two P type doping bar 32 surfaces in the super-junction structure drift region, have in each P type tagma 31 respectively and the P that is positioned at device surface source metal 51 and links to each other + Source contact area 33 and N + Source contact area 41; The surface of N-type doping bar 42 has the grid structure that is made of gate oxide 22 and polygate electrodes 52 in the super-junction structure drift region, wherein two P type doping bars 32 of gate oxide 22 and super-junction structure drift region and N-type doping bar 42 are in contact, and mutually isolate by dielectric layer 23 between polygate electrodes 52 and the source metal.
Described terminal structure 12 comprises and is positioned at N +The terminal doped region 14 on drain contact region 43 surfaces and groove medium 21, wherein terminal doped region 14 and integral body vertically super knot structure cell link to each other but mutually isolate by groove medium 21 with drain electrode deriving structure 13, terminal doped region 14 and groove medium 21 surfaces are the dielectric layers 23 of isolating source metal 52 and drain metal 53.
Described drain electrode deriving structure 13 comprises drain electrode exit 44 and drain metal 53, and wherein said drain electrode exit 44 is realized drain metal 53 and N +The electrical connection of drain contact region 43.Drain electrode deriving structure vertically super junction device becomes transversal device, drain electrode exit 44 can adopt N-type heavily-doped semiconductor 45, with vertical super N-type doped semiconductor 46 or the metal 54 of tying N-type doping bar 42 identical doping contents in the structure cell 11, three kinds of modes can be finished simultaneously with structure cell on technique, also can finish separately, technique is simple, does not need to increase extra mask plate.
The laterally super knot high-voltage power semiconductor device that technique scheme provides, can adopt the structures such as planar gate, groove grid or V-type grid, the opposite planar grid, it is less that the cellular of selection groove gate device can be done, because the raceway groove of groove grid is vertical, channel length is determined by P type tagma 31 junction depths, and the channel length of planar gate is by the length decision in P type tagma 31.
Fig. 3 is laterally super knot high-voltage power semiconductor device structure profiles of groove grid provided by the invention, the vertically super knot drift region structure that the integrated a plurality of cellulars of device, cellular 11 adopt N-type doping bar of two P type doping bars, 32 folders 42 to consist of; Polygate electrodes 52 peripheries are groove gate oxides 24, are source metal 51 above the groove gate oxide 24, mutually isolate by dielectric layer 23 between source metal 51, the polysilicon gate 52; Terminal structure 12 comprises terminal doped region 14 and groove dielectric layer 21; Drain electrode deriving structure 13 comprises drain electrode exit 44 and drain metal 53.Except the grid structure is different, other of device consist of all can adopt the technique realization identical with Fig. 2.
Fig. 4 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, the integrated structure cell 11 of device, terminal structure 12 and drain electrode deriving structure 13, the drain electrode deriving structure comprises drain electrode exit 44 and drain metal 53, its drain electrode exit 44 adopts N-type heavily-doped semiconductor 45, and N-type heavily-doped semiconductor 45 can adopt same N +Drain contact region 43 and N +The concentration that source contact area 41 is identical also can adopt different concentration.
Fig. 5 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, the integrated structure cell 11 of device, terminal structure 12 and drain electrode deriving structure 13, the drain electrode deriving structure comprises drain electrode exit 44 and drain metal 53, its drain electrode exit 44 adopts and vertically surpasses the N-type doped semiconductor 46 of tying N-type doping bar 42 identical doping contents in the structure cell 11, can form simultaneously with the N-type bar 42 that mixes, also can form separately.
Fig. 6 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, integrated one of device vertically surpasses knot structure cell 11, terminal structure 12 and drain electrode deriving structure 13, the drain electrode deriving structure comprises drain electrode exit 44 and drain metal 53, its drain electrode exit 44 adopts metal 54, metal 54 can form simultaneously with drain metal 53, also can form separately.
Fig. 7 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, integrated one of device vertically surpasses knot structure cell 11, terminal structure 12 and drain electrode deriving structure 13, terminal structure 12 comprises terminal doped region 14 and groove dielectric layer 21, and its terminal doped region 14 can adopt three kinds of different modes.(a) be the section of structure of device; (b) be terminal doped region 14 and vertical super P type doped semiconductor 35 of tying P type doping bar 32 identical doping contents in the structure cell 11.
Further, the horizontal super high-voltage power semiconductor device terminal doped region 14 of tying comprises below and vertical P type doped semiconductor 35 and top and vertical super P type doped semiconductor 34 of tying P type tagma 31 identical doping contents in the structure cell 11 that surpasses P type doping bar 32 identical doping contents in the knot structure cell 11, shown in Fig. 7 (c).
Further, laterally super knot high-voltage power semiconductor device terminal doped region 14 comprise P type doping bar 32 identical doping contents in below and the vertical super knot structure cell 11 P type doped semiconductor 35, middle with vertically surpass the P type doped semiconductor 34 of tying P type tagma 31 identical doping contents in the structure cell 11 and the P type heavily doped region 36 of top, shown in Fig. 7 (d).
Fig. 8 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, and device comprises vertically super knot structure cell 11, terminal structure 12 and a drain electrode deriving structure 13, and with on its integrated upper body silicon substrate 10.
Fig. 9 is laterally super knot high-voltage power semiconductor device structure profile of planar gate provided by the invention, device comprises vertically super knot structure cell 11, terminal structure 12 and a drain electrode deriving structure 13, and be integrated on the SOI substrate, wherein, oxygen buried layer 20 is positioned on the body silicon substrate 10.
In order to make technical problem to be solved by this invention, technical scheme and beneficial effect clearer, take Figure 10 as embodiment, the present invention is described in further detail.
Figure 10 (a) is laterally super knot high-voltage power semiconductor device of a kind of groove grid provided by the invention, and the P type doping bar 32 of N-type doping bar 42 and both sides exhausts mutually, forms vertically super knot drift region structure.This device adopts slot grid structure, and device channel determines by the junction depth in P type tagma 31, therefore vertically super-junction structure can do very little, the degree of depth of super knot is according to the difference of device withstand voltage and difference.The super-junction structure silicon limit that breaks traditions obtains less conduction resistance longitudinally, and the relation of conduction resistance and withstand voltage BV is substantially satisfied: R On, sp∝ BV 1.23Compare with the horizontal super-junction structure of routine, vertically the primitive unit cell area of super junction device is less, therefore can reduce the chip area of device, saves manufacturing cost.The lateral terminal structure of described device is made of groove dielectric layer 21 and terminal doped region 14, and the concentration of terminal doped region 14 is identical with P type doping bar 32 concentration.Terminal doped region 14 can be finished together with the technique of structure cell, also can finish separately.The present invention adopts N-type heavily-doped semiconductor 45 with the drain electrode (N of vertical super-junction structure +Drain contact region 43) by laterally drawing, forms laterally super junction device.During device withstand voltage, drain electrode adds positive voltage, so that N-type heavily-doped semiconductor 45, groove medium 21, drain metal 53 and terminal doped region 14 consist of MIS capacitance structure, MIS electric capacity assisted depletion P type terminal doped region, further optimised devices surface field, it is laterally withstand voltage to improve device.Because the device bottom is N + Drain contact region 43, highly doped so that device can be integrated on the various backing materials, this structure is integrated in device on the P type substrate 10.Potential profile when Figure 10 (b) has provided this device breakdown, wherein P type substrate 10 doping content 6E14cm -3, thickness is 30 microns, 0.4 micron of P type doping bar 32 width, concentration 1.6E16cm -3, the concentration of N-type doping bar 42 is 1E16cm -3, width is 1.2 microns, 1 micron of groove medium 21 width, 7 microns of groove depths, 0.5 micron of the width of terminal doped region 14, vertically super knot drift region structure length is 5 microns, the drain electrode exit adopts N-type heavily-doped semiconductor 45, same N +The concentration of drain contact region 43 is identical.Simulation architecture shows that equipotential lines is evenly distributed during device breakdown, the withstand voltage 120V that reaches.
Laterally super knot high-voltage power semiconductor device cellular provided by the invention adopts vertical super-junction structure not only to alleviate withstand voltage BV and conduction resistance R N, spRelation, greatly reduce simultaneously the element layout area, reduce process costs; Terminal structure comprises terminal doped region 14 and groove medium 21, and employing groove dielectric layer is withstand voltage can further to reduce chip area.Device can adopt the structures such as planar gate, groove grid or V-type grid.Device by drain electrode deriving structure 13 vertically super junction device drain electrode laterally draw, make drain electrode, grid and source electrode all on the surface, not only be easy to custom circuit integratedly, and further reduce chip area, the reduction process costs.

Claims (7)

1. a horizontal super knot high-voltage power semiconductor device comprises and at least one or more than one vertically surpassing ties structure cell (11), terminal structure (12) and drain electrode deriving structure (13); A plurality of vertically super knot structure cells (11) are horizontal or Width is together tightly packed along device, form whole vertically super knot structure cell; Described terminal structure (12) is positioned at the outside or the periphery of whole structure cell, and described drain electrode deriving structure (13) is positioned at the outside or the periphery of described terminal structure (12);
Described vertically super knot structure cell (11) comprises the N that is positioned at substrate base (1) surface +Drain contact region (43) is positioned at N +Drain contact region (43) surface and the super-junction structure drift region that is formed by two P type doping bars (32) therebetween N-type doping bar (42); Lay respectively at two P type tagmas (31) on the surface of two P type doping bars (32) in the super-junction structure drift region, have in each P type tagma (31) respectively and the P that is positioned at device surface source metal (51) and links to each other +Source contact area (33) and N +Source contact area (41); The surface of N-type doping bar (42) has the grid structure that is made of gate oxide (22) and polygate electrodes (52) in the super-junction structure drift region, wherein gate oxide (22) is in contact with two P type doping bars (32) and the N-type doping bar (42) of super-junction structure drift region, mutually isolates by dielectric layer (23) between polygate electrodes (52) and the source metal;
Described terminal structure (12) comprises and is positioned at N +Terminal doped region (14) and the groove medium (21) on drain contact region (43) surface, wherein terminal doped region (14) and integral body vertically super knot structure cell link to each other but with drain electrode deriving structure (13) by mutually isolation of groove medium (21), terminal doped region (14) and groove medium (21) surface are the dielectric layers (23) of isolating source metal (52) and drain metal (53);
Described drain electrode deriving structure (13) comprises drain electrode exit (44) and drain metal (53), and wherein said drain electrode exit (44) is realized drain metal (53) and N +The electrical connection of drain contact region (43);
Described vertically super knot structure cell (11), terminal structure (12) and drain electrode deriving structure (13) adopt common substrate base (1), and the N on substrate base (1) surface +Drain contact region (43) forms an integral body.
2. laterally super knot high-voltage power semiconductor device according to claim 1 is characterized in that described grid structure is planar gate, groove grid or V-type grid.
3. according to claim 1 laterally surpassing tied the high-voltage power semiconductor device, it is characterized in that, described drain electrode exit 44 can adopt N-type heavily-doped semiconductor (45), with vertical super knot structure cell 11 in N-type doped semiconductor (46) or the metal (54) of the identical doping content of N-type doping bar (42), three kinds of modes can be finished simultaneously with structure cell on technique, also can finish separately.
4. the laterally super high-voltage power semiconductor device of tying according to claim 1 is characterized in that described terminal doped region (14) adopts the P type doped semiconductor (35) with the middle identical doping content of P type doping bar (32) of vertical super knot structure cell (11).
5. according to claim 1 laterally surpassing tied the high-voltage power semiconductor device, it is characterized in that described terminal doped region (14) comprises below and vertical super P type doped semiconductor (34) of tying P type doped semiconductor (35) and the top of the identical doping content of P type doping bar (32) in the structure cell (11) and vertically surpassing the identical doping content in the middle P type tagma (31) of knot structure cell (11).
6. according to claim 1 laterally surpassing tied the high-voltage power semiconductor device, it is characterized in that described terminal doped region (14) comprises below and the P type doped semiconductor (35) of the middle identical doping content of P type doping bar (32) of vertical super knot structure cell (11), middle and the P type doped semiconductor (34) of the identical doping content in the middle P type tagma (31) of vertical super knot structure cell (11) and the P type heavily doped region (36) of top.
7. laterally super knot high-voltage power semiconductor device according to claim 1 is characterized in that described substrate is body silicon substrate, SOI substrate or Sapphire Substrate.
CN201210516380.5A 2012-12-06 2012-12-06 A kind of horizontal ultra-junction high-voltage power semiconductor device Expired - Fee Related CN102969357B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210516380.5A CN102969357B (en) 2012-12-06 2012-12-06 A kind of horizontal ultra-junction high-voltage power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210516380.5A CN102969357B (en) 2012-12-06 2012-12-06 A kind of horizontal ultra-junction high-voltage power semiconductor device

Publications (2)

Publication Number Publication Date
CN102969357A true CN102969357A (en) 2013-03-13
CN102969357B CN102969357B (en) 2015-08-19

Family

ID=47799376

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210516380.5A Expired - Fee Related CN102969357B (en) 2012-12-06 2012-12-06 A kind of horizontal ultra-junction high-voltage power semiconductor device

Country Status (1)

Country Link
CN (1) CN102969357B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1363332A1 (en) * 2001-02-21 2003-11-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US7427800B2 (en) * 2004-02-02 2008-09-23 Hamza Yilmaz Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
US20080283913A1 (en) * 2007-05-17 2008-11-20 Denso Corporation Semiconductor device
CN201904341U (en) * 2010-12-22 2011-07-20 东南大学 P type hyperconjugation lateral double diffusion metal oxide semiconductor tube
CN102231390A (en) * 2011-06-17 2011-11-02 浙江大学 Vertical double-diffused metal oxide semiconductor power device with super junction structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1363332A1 (en) * 2001-02-21 2003-11-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US7427800B2 (en) * 2004-02-02 2008-09-23 Hamza Yilmaz Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
US20080283913A1 (en) * 2007-05-17 2008-11-20 Denso Corporation Semiconductor device
CN201904341U (en) * 2010-12-22 2011-07-20 东南大学 P type hyperconjugation lateral double diffusion metal oxide semiconductor tube
CN102231390A (en) * 2011-06-17 2011-11-02 浙江大学 Vertical double-diffused metal oxide semiconductor power device with super junction structure

Also Published As

Publication number Publication date
CN102969357B (en) 2015-08-19

Similar Documents

Publication Publication Date Title
CN101689562B (en) Semiconductor device
CN103165678B (en) Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device
CN102148251B (en) Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit
CN104465719B (en) Semiconductor device
CN103050540B (en) Use the lateral power of the low conduction resistance of high-dielectric constant groove structure
CN102779836B (en) Longitudinal power device for low-ratio on-resistance employing groove structure with high dielectric constant
CN102969358B (en) A kind of horizontal high voltage power semiconductor device
CN103268887B (en) Field effect transistor, edge structure and related manufacturing method
CN105070760B (en) A kind of power MOS (Metal Oxide Semiconductor) device
CN106024858A (en) HK SOI LDMOSdevice having three-grating structure
CN102420251A (en) VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure
CN102412297A (en) Silicon-based power device structure based on substrate bias technology
CN108122975A (en) Superjunction devices
CN103022134B (en) A kind of horizontal high voltage power device of SOI of Ultra-low Specific conducting resistance
CN107564965B (en) Transverse double-diffusion MOS device
CN106531802A (en) Low on-resistance novel high-voltage SJ power device
CN107275388B (en) Transverse high-voltage device
CN102130176B (en) SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer
CN101777584B (en) P-channel laterally double diffused metal oxide semiconductor device
CN108110057A (en) Super-junction metal oxide field effect transistor
CN107359194B (en) Device for eliminating high electric field
CN107425052A (en) A kind of lateral high-voltage device
CN107359195B (en) High-voltage-resistance transverse super junction device
CN103035714A (en) Cellular structure of super junction metal oxide semiconductor field effect transistor (MOSFET)
CN104617139B (en) LDMOS device and manufacture method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150819

Termination date: 20151206

EXPY Termination of patent right or utility model