CN102959739A - Group III nitride semiconductor device and method for producing same - Google Patents

Group III nitride semiconductor device and method for producing same Download PDF

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CN102959739A
CN102959739A CN2011800317092A CN201180031709A CN102959739A CN 102959739 A CN102959739 A CN 102959739A CN 2011800317092 A CN2011800317092 A CN 2011800317092A CN 201180031709 A CN201180031709 A CN 201180031709A CN 102959739 A CN102959739 A CN 102959739A
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nitride semiconductor
iii nitride
mask layer
layer
nano
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CN102959739B (en
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北野司
难波江宏一
小池正好
寺前文晴
近藤俊行
铃木敦志
前田智彦
森绿
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EL Seed Corp
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Abstract

To provide a group III compound semiconductor device and a method for producing the same with which it is possible to precisely reduce the dislocation density in a semiconductor layer. [Solution] A group III nitride semiconductor device (1) is produced by forming a mask layer (40) on a substrate (20) and then selectively growing, through a pattern (44) of the mask layer (40), nanocolumns (50) formed from group III nitride semiconductors such that a group III nitride semiconductor layer (10) is grown on the mask layer (40).

Description

III nitride semiconductor devices and manufacture method thereof
Technical field
The present invention relates to III nitride semiconductor devices and manufacture method thereof.
Background technology
At present, known have a LED element (for example with reference to patent documentation 1) that is formed with the semiconductor layer of GaN system at the SiC substrate.In this LED element, use the fluorescence SiC substrate that has a SiC layer that is doped with B and N and be doped with the 2nd SiC layer of Al and N, emit black light from the multiple quantum trap active layer.Black light is absorbed by a SiC layer and the 2nd SiC layer, is transformed into red visible light by a SiC layer from green, is transformed into red visible light by the 2nd SiC layer from blueness.It is high and near the white light of sunlight that its result can emit color rendering from fluorescence SiC substrate.
But in this LED element, because the grid of SiC substrate and GaN based semiconductor layer does not mate and the thermal expansion rate variance, the dislocation density of GaN based semiconductor layer is high.Its result exists and is difficult to realize the thick-film of GaN based semiconductor layer and the problem of low resistance.
Be to reduce the dislocation density of the semiconductor layer on the substrate, motion have by MOCVD on the substrate via resilient coating film forming GaN film after, utilize metal and dielectric nanometer mask etching GaN film, form the method (for example with reference to patent documentation 2) of nano-pillar.According to the method, after forming nano-pillar, utilize the transverse direction growth that GaN based semiconductor layer is grown up at resilient coating and nano-pillar.
Patent documentation 1:(Japan) No. 4153455 communique of special permission
Patent documentation 2:(Japan) JP 2010-518615 communique
But in the method that patent documentation 2 is put down in writing, still dislocation density is high to be formed at U-GaN film on the substrate, and it is carried out etching and the dislocation density of the nano-pillar self that forms is also high.Consequently dislocation is to the GaN based semiconductor layer transmission that is formed on the nano-pillar, and the reduction effect of the dislocation density of GaN based semiconductor layer is also insufficient.
Summary of the invention
The present invention foundes in view of described situation, and its purpose is, III nitride semiconductor devices and the manufacture method thereof of the reduction of the dislocation density that can realize reliably semiconductor layer is provided.
For realizing described purpose, the invention provides a kind of III nitride semiconductor devices, possess: substrate, it is made of SiC or Si; Mask layer, it is formed on the described substrate, and is formed with the pattern of regulation; Nano-pillar, its described pattern by described mask layer is optionally grown up, and is made of the III group-III nitride semiconductor; The III nitride semiconductor layer, it becomes to look high than described nano-pillar on described mask layer.
According to this III nitride semiconductor devices, by mask layer the nano-pillar selectivity is grown up, therefore, can realize that nano-pillar is from the reduction of the dislocation density of body.Consequently, the dislocation from nano-pillar to the transmission that is formed at the III nitride semiconductor layer on the mask layer reduces tremendously, and the dislocation density of III nitride semiconductor layer also reduces.In addition, when the III nitride semiconductor layer was grown up, the dislocation that produces in this III nitride semiconductor layer had terminal at the interface with nano-pillar, therefore, can not transmit upward.
In described III nitride semiconductor devices, preferably, described mask layer is made of non-crystalline material.
According to this III nitride semiconductor devices, owing to mask layer is made of non-crystalline material, so the securely combination of III nitride semiconductor layer and mask layer.Thus, producing in the situation of excessive stress between III nitride semiconductor layer and the mask layer, allow the dislocation between III nitride semiconductor layer and the mask layer.Its result realizes the reduction of the dislocation density of III nitride semiconductor layer.
In described III nitride semiconductor devices, preferably, between described substrate and described mask layer, possesses the resilient coating that is consisted of by the III group-III nitride semiconductor that contains Al.
According to this III nitride semiconductor devices, because resilient coating contains Al, so situation that GaN is directly grown up at the substrate that is made of SiC or Si, III group-III nitride semiconductor and substrate can intense reactions at each other interface, and the III nitride semiconductor layer is grown up on substrate reliably.
In addition, for realizing described purpose, the invention provides a kind of manufacture method of III nitride semiconductor devices, make described III nitride semiconductor devices, wherein, comprise: the mask layer that forms described mask layer at described substrate forms operation; The nano-pillar growth operation that described pattern by described mask layer is optionally grown up the described nano-pillar that is made of the III group-III nitride semiconductor; Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.
According to the manufacture method of this III nitride semiconductor devices, can form mask layer at substrate, utilize mask layer that nano-pillar is grown up, and, the III nitride semiconductor layer is grown up.Therefore, do not need the operation of as at present, removing mask layer, can realize the reduction of manufacturing cost.
For realizing described purpose, the invention provides a kind of manufacture method of III nitride semiconductor devices, make described III nitride semiconductor devices, wherein, comprise: the resilient coating formation operation that on described substrate, forms described resilient coating by sputtering method; The mask layer that forms described mask layer at the described substrate that is formed with described resilient coating forms operation; Make the nano-pillar growth operation of the described nano-pillar selectivity growth that is consisted of by the III group-III nitride semiconductor by the described pattern of described mask layer; Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.
According to the manufacture method of this III nitride semiconductor devices, can form mask layer at substrate, directly utilize mask layer that nano-pillar is grown up, and can form the III nitride semiconductor layer at mask layer.Therefore, do not need the operation of as at present, removing mask layer, can realize the reduction of manufacturing cost.
In addition, owing to forming resilient coating by sputtering method, so can be embodied as at low temperatures farm labourer's skill, improve the volume production rate.In addition, compare mocvd method etc., can obtain the crystal structure of the few better quality of defective.
According to the present invention, can realize reliably the reduction of the dislocation density of semiconductor layer.
Description of drawings
Fig. 1 is the constructed profile of the LED element of expression an embodiment of the present invention;
Fig. 2 is that expression utilizes the pattern of mask layer to form the top key diagram of LED element of the state of nano-pillar;
Fig. 3 represents the manufacture process of LED element, (a) state of expression substrate, and (b) expression makes the state that resilient coating is grown up, and (c) expression is formed with the state of mask layer, and (d) expression makes the state that nano-pillar is grown up;
Fig. 4 represents the manufacture process of LED element, (a) expression makes the state that the N-shaped layer in the III nitride semiconductor layer is grown up, (b) expression makes the whole state of growing up of III nitride semiconductor layer, (c) the expression etching state of a part of III nitride semiconductor layer;
Fig. 5 is the flow chart of the manufacture process of expression LED element;
Fig. 6 is the expression variation, and expression utilizes the pattern of mask layer to form the top key diagram of LED element of the state of nano-pillar.
Symbol description
The 1LED element
The 10III nitride semiconductor layer
12n type layer
14 multiple quantum trap active layers
16p type clad
18p type contact layer
20 substrates
30 resilient coatings
40 mask layers
42 holes
44 patterns
50 nano-pillar
The 60n lateral electrode
62p type electrode
Embodiment
Fig. 1～Fig. 5 represents one embodiment of the present invention, and Fig. 1 is the constructed profile of LED element.
As shown in Figure 1, the LED element 1 as the III nitride semiconductor devices possesses by Al xGa yIn 1 -x-yN(0≤x≤1,0≤y＜=1, x+y≤1) III nitride semiconductor layer 10 and the coefficient of thermal expansion rate substrate 20 less than III nitride semiconductor layer 10 of expression.In the present embodiment, substrate 20 is made of single crystals 6H type SiC, and the coefficient of thermal expansion coefficient is 4.2 * 10 -6/ ℃.In addition, the coefficient of thermal expansion coefficient as the nitride semiconductor layer of semiconductor light emitting section is 5.6 * 10 -6/ ℃.
Substrate 20 comprises donor impurity and acceptor's property impurity, when encouraging by the light that sends from III nitride semiconductor layer 10, because of alms giver, acceptor, to the luminous light that sends provision wavelengths.For example, in the situation of using block SiC substrate, donor impurity is made as N, when acceptor's property impurity is made as B, is roughly sending the visible light of Yellow-to-orange by the excitation of ultraviolet light.In addition, in the situation of using block SiC substrate, donor impurity is made as N, when acceptor's property impurity is made as Al, is sending roughly blue visible light by the excitation of ultraviolet light.In addition, by when donor impurity is made as N, add simultaneously B and Al as acceptor's property impurity, also can access lily visible light, also can make emission wavelength to the short wavelength side displacement by SiC being made as cellular, can change arbitrarily the emission wavelength of substrate.
Form the resilient coating 30 that is consisted of by the III group-III nitride semiconductor at substrate 20.Resilient coating 30 passes through by Al xGa yIn 1-x-yN(0≤x≤1,0≤y≤1, x+y≤1) material that represents of formula consists of.In the present embodiment, as resilient coating 30 by Al xGa 1-xN(0＜x≤1) formula represents, and uses the resilient coating 30 that contains Al.
Be formed with the mask layer 40 that is consisted of by non-crystalline material at resilient coating 30.Be formed with the pattern 42 that is used to form nano-pillar 50 described later at mask layer 40.In the present embodiment, as mask layer 40, use SiO 2In addition, can certainly use the other materials in addition of SiNx(0＜x) as mask layer 40.In addition, as the material of mask layer 40, also can use Al 2O 3, such material such as W.These materials can be many crystallizations, also can be noncrystalline.
As shown in Figure 2, the pattern 42 of mask layer 40 is the shape that the hole 44 of circle is configured in the intersection point of equilateral triangle grid.The diameter in hole 44 and interval are arbitrarily, for example the diameter in hole 44 can be made as 50～1000nm, and interval each other, adjacent hole 44 is made as 100～1000nm.
On substrate 20, via resilient coating 30 and the pattern 42 by mask layer 40 nano-pillar 50 is grown up.In the present embodiment, use GaN as nano-pillar 50.Nano-pillar 50 is grown up accordingly with pattern 42, compares with the situation of not growing up by mask layer 40, and dislocation density reduces.In the present embodiment, nano-pillar 50 forms cylindric, aspect ratio can be made as more than 1.In addition, as long as nano-pillar 50 forms column, also can be the shape beyond the cylinder.
Form III nitride semiconductor layer 10 at mask layer 40.III nitride semiconductor layer 10 has N-shaped layer 12, multiple quantum trap active layer 14, p-type clad 16, p-type contact layer 18 in order from substrate 20 sides.The part of III nitride semiconductor layer 10 is removed by etching, exposes the part of N-shaped layer 12, in this exposed portions serve n lateral electrode 60 is set.In addition, be formed with p lateral electrode 62 at p-type contact layer 18.
In the present embodiment, N-shaped layer 12 is formed by the n-GaN of the N-shaped dopant that is doped with ormal weight (for example Si).In addition, multiple quantum trap active layer 14 has by In xGa 1-xN(0≤x≤1)/Al yGa 1-yN(0≤y≤1) the multiple quantum trap structure that forms.In addition, p-type clad 16 and p-type contact layer 18 are formed by the p-GaN of the p-type dopant that is doped with ormal weight (for example Mg) respectively.
Form to the epitaxial growth of p-type contact layer 18 by the III group-III nitride semiconductor from N-shaped layer 12.In addition, at least comprise the first conductive layer, active layer and the second conductive layer, when the first conductive layer and the second conductive layer are applied voltage, if by electronics and hole again in conjunction with sending light by active layer, the layer formation of III nitride semiconductor layer 10 is arbitrarily.
N lateral electrode 60 is formed on the N-shaped layer 12, for example is that Ni/Au consists of, and steams by vacuum and crosses method, sputtering method, CVD(Chemical Vapor Deposition) formation such as method.P lateral electrode 62 is formed on the p-type contact layer 18, for example by ITO(Indium Tin Oxide) consist of, steam by vacuum and cross method, sputtering method, CVD(Chemical Vapor Deposition) formation such as method.
Secondly, the manufacture method of LED element 1 is described with reference to Fig. 3～Fig. 5.Fig. 3 and Fig. 4 are the constructed profiles of LED element, and Fig. 5 is the flow chart of the manufacture method of LED element.In addition, illustrate with 1 element unit for describing in the mode corresponding with Fig. 1 among Fig. 3 and Fig. 4, but be actually the state of the wafer before the element divisions, about also be formed with continuously other element.
At first, generate the single crystals 6H type SiC of the bulk that is doped with donor impurity and acceptor's property impurity by sublimed method.Interpolation and impurity element or its compound of foreign gas in the environmental gas controlled to the interpolation of material powder when in addition, the doping content of the impurity of SiC crystallization can be by crystalline growth.Shown in Fig. 3 (a), substrate 20 is grown up by the piece of sublimed method and is made for example crystalline substance of the agllutination about 30mm, and the process periphery is ground and cut, cuts into slices, the operations such as the surface is ground and cut, surface grinding are made.At this, the thickness of substrate 20 is arbitrarily, for example is 250 μ m.
Afterwards, shown in Fig. 3 (b), make resilient coating 30 epitaxial growths (resilient coating forms operation S10(Fig. 5) at substrate 20).In the present embodiment, form resilient coating 30 by sputtering method whole ground on substrate 20.In addition, resilient coating 30 also can pass through the formation such as mocvd method (Metal Organic ChemicalVapor Deposition) method, MBE method (Molecular Beam Epitaxy), HVPE method (HalideVapor Phase Epitaxy).And then resilient coating 30 also can form by laser ablation method.At this, the thickness of resilient coating 30 is arbitrarily, for example is 10～200nm.
Secondly, shown in Fig. 3 (c), form mask layer 40(mask layer at the substrate 20 that is formed with resilient coating 30 and form operation S20(Fig. 5)).In the present embodiment, steam the method for crossing whole ground on resilient coating 30 by vacuum and form mask layer 40.At this, the thickness of mask layer 40 is arbitrarily, for example is 10～200nm.As long as be the thickness of this degree, the light of the mask layer 40 that then penetrates from active layer see through encumber to act on and reduce.In addition, as long as utilize the interference of light effect to take out light, then do not need to consider the above-mentioned effect that encumbers, therefore, as long as set the thickness of mask layer 40 according to the degree ground that can obtain this interference effect.Afterwards, use the nano imprint technology to form pattern 44 at mask layer 40.
Then, shown in Fig. 3 (d), utilize the pattern 42 of mask layer 40 to make nano-pillar 50 epitaxial growths (nano-pillar growth operation S30(Fig. 5)).In the present embodiment, by mocvd method and utilize the pattern 42 of mask layer 40 nano-pillar 50 of on resilient coating 30, optionally growing up.In addition, in the growth of nano-pillar 50, can certainly use MBE method, HVPE method etc.The height of nano-pillar 50 is arbitrarily, for example is 500nm.In the present embodiment, because the nano-pillar 50 of optionally growing up on substrate 20, so compare the situation of whole ground grown semiconductor layer on substrate 20, the dislocation density in the nano-pillar 50 is minimum.
After the formation of nano-pillar 50 finishes, make 10 growth (semiconductor layer growth operation (Fig. 5)) of III nitride semiconductor layer.In the present embodiment, by the MOCVD device nano-pillar 50 is become continuously with III nitride semiconductor layer 10.At this, with regard to the V/III ratio, nano-pillar growth operation one side is less than semiconductor growth operation.For example, can be with V/III than in nano-pillar growth operation, being made as less than 900.When nano-pillar is grown up when V/III when excessive, then the semiconductor of growing up can not be formed column.In addition, with regard to the quantity delivered of gallium, preferred nano-pillar growth operation one side is less than semiconductor layer growth operation.Quantity delivered when gallium in nano-pillar growth operation is too much, and then the shape in mask semiconductor-on-insulator island ground crystalline growth and or nano-pillar integrated with nano-pillar produces deviation.
In the present embodiment, shown in Fig. 4 (a), after the mode with landfill nano-pillar 50 has formed N-shaped layer 12, shown in Fig. 4 (b), from mask layer 40 sides grow up successively multiple quantum trap active layer 14, p-type clad 16, p-type contact layer 18.At this moment, in the III nitride semiconductor layer 10 that mask layer 40 is grown up, because the dislocation that produces in inside forms terminal in the contact portion with the sidewall of nano-pillar 50, so can reduce dislocation density.In addition, because nano-pillar 50 is also low from the dislocation density of body, so minimum from the dislocation of nano-pillar 50 transmission.
In addition, after having formed resilient coating 30 by sputter equipment, utilize the MOCVD device to form continuously nano-pillar 50 and III nitride semiconductor layer 10, thus, and compare in the situation by MOCVD device growth resilient coating 30, can shorten manufacturing process.Thus, can reduce the manufacturing cost of light-emitting component 1.
In addition, not being situated between between nano-pillar growth operation and semiconductor layer growth operation has mask layer to form operation, therefore, can access the good III nitride semiconductor layer 10 of quality.Growth in the nano-pillar 50 that is made of the III group-III nitride semiconductor forms in the situation of amorphous mask layer 40 afterwards, the surface of nano-pillar 50 is because of the composition cracking of mask layer 40, take deteriorated nano-pillar 50 as seed crystal, III nitride semiconductor layer 10 is grown up, thus, can not obtain the good III nitride semiconductor layer 10 of quality.
And, because mask layer 40 is non-crystalline material, so be formed at III nitride semiconductor layer 10 and securely combination of mask layer 40 on the mask layer 40.Thus, producing in the situation of excessive stress between III nitride semiconductor layer 10 and the mask layer 40, allowing the relative dislocation of III nitride semiconductor layer 10 and mask layer 40.Thus, realize the reduction of the dislocation density of III nitride semiconductor layer 10.
In addition, the thickness of each layer of III nitride semiconductor layer 10 is arbitrarily, for example the thickness of routine N-shaped layer 12 can be made as 3 μ m, and the thickness of multiple quantum trap active layer 14 is made as 100nm, the thickness of p-type clad 16 is made as 80nm, the thickness of p-type contact layer 18 is made as 10nm.Like this, the thickness of III nitride semiconductor layer 10 can be made as more than the 3 μ m.After III nitride semiconductor layer 10 is grown up, use photoetching technique to form the mask of photoresists at p-type contact layer 18, be etched to the surface of N-shaped layer 12 from p-type contact layer 18 after, remove mask (etching work procedure S50(Fig. 5)).Thus, shown in Fig. 4 (c), form the step part that is consisted of by a plurality of compound semiconductor layers from N-shaped layer 12 to p-type contact layer 18.
Then, use vacuum to steam the method for crossing and photoetching technique formation n lateral electrode 60 and p lateral electrode 62(electrode forming process S60(Fig. 5)).In the present embodiment, make the material of n lateral electrode 60 different with the material of p lateral electrode 62, but these materials being made as when identical, can form simultaneously n lateral electrode 40 and p lateral electrode 62.In addition, for guaranteeing each electrode 60,62 and ohmic contact and the adhesion of III nitride semiconductor layer 10, can under the environment of the temperature of regulation, regulation, implement the heat treatment of official hour.Afterwards, be divided into a plurality of LED elements 1 by cutting, make thus LED element 1.
The LED element 1 that as above consists of sends ultraviolet light from multiple quantum trap active layer 14 when p lateral electrode 62 and n lateral electrode 60 are applied voltage.Then, ultraviolet light is transformed into visible light by substrate 20 after, radiate to the outside.
According to this LED element 1, because by mask layer 40 nano-pillar 50 of optionally growing up, so can realize the reduction of the dislocation density of nano-pillar 50 self.Its result, from nano-pillar 50 to the tremendous minimizing of dislocation that is formed at III nitride semiconductor layer 10 transmission on the mask layer 40, the dislocation density of III nitride semiconductor layer 10 also reduces.In addition, when the growth of III nitride semiconductor layer 10,10 dislocations that produce are owing to having terminal at the interface with nano-pillar 50, so not upward conveyance in this III nitride semiconductor layer.Therefore, can reduce reliably the dislocation density of III group-III nitride semiconductor 10.
In addition, according to this LED element 1, because resilient coating 30 contains Al, so direct situation of growth GaN on the substrate that is consisted of by SiC or Si for example, III group-III nitride semiconductor and substrate can not react intensely at interface each other, and III nitride semiconductor layer 10 is grown up on substrate 20 reliably.
In addition, according to the manufacture method of this LED element 1, form mask layers 40 at substrate 20, utilize mask layer 40 that nano-pillar 50 is grown up, can be on mask layer 40 direct growth III nitride semiconductor layer 10.Therefore, do not need the operation of as at present, removing mask layer, can realize the reduction of manufacturing cost.
And then owing to forming resilient coating 30 and nano-pillar 50 by sputtering method, the technique of can growing up at low temperatures improves the volume production rate.In addition, compare with mocvd method etc., resilient coating can be made as the good crystal structure of the few quality of defective.
In addition, in the above-described embodiment, represented as semiconductor device LED element 1 to be suitable for example of the present invention, but for example other such device of LD element also can be suitable for the present invention.Such as also going for the electronic devices such as field-effect transistor, bipolar transistor, solar cell etc.
In addition, in the above-described embodiment, represented nano-pillar 50 is disposed at the intersection point of triangular lattice, but the configuration status of nano-pillar can change arbitrarily, for example shown in Figure 6, also can be disposed at the intersection point of square lattice.
And then, in the above-described embodiment, represented to use the substrate of the SiC of 6H type as substrate 20, but can certainly be the 4H type, can also be the 15R type, also can use Si as substrate 20.And then substrate 20 also can not have fluorescent functional, and the illuminant colour of III nitride semiconductor layer 10 also is arbitrarily.
Embodiments of the present invention more than have been described, but the execution mode of above-mentioned record does not limit the scope of request of the present invention.In addition, what should be careful is that all Feature Combinations that illustrate in the execution mode are not limited to for the device that solves the invention problem.
Claims (according to the modification of the 19th of treaty)
1. III nitride semiconductor devices possesses:
Substrate, it is made of SiC;
Mask layer, it is formed on the described substrate, and is formed with the periodic pattern of regulation;
Nano-pillar, its described pattern by described mask layer is optionally grown up, and is made of the III group-III nitride semiconductor;
The III nitride semiconductor layer, it becomes to look high in the mode of burying described nano-pillar underground than described nano-pillar on described mask layer.
2. III nitride semiconductor devices as claimed in claim 1, wherein,
Described mask layer is made of non-crystalline material.
3. III nitride semiconductor devices as claimed in claim 2, wherein,
Between described substrate and described mask layer, possesses the resilient coating that is consisted of by the III group-III nitride semiconductor that contains Al.
4. the manufacture method of an III nitride semiconductor devices is made each described III nitride semiconductor devices in the claim 1～3, wherein, comprises:
The mask layer that forms described mask layer at described substrate forms operation;
The nano-pillar growth operation that described pattern by described mask layer is optionally grown up the described nano-pillar that is made of the III group-III nitride semiconductor;
Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.
5. the manufacture method of an III nitride semiconductor devices is made III nitride semiconductor devices claimed in claim 3, wherein, comprises:
On described substrate, form the resilient coating formation operation of described resilient coating by sputtering method;
The mask layer that forms described mask layer at the described substrate that is formed with described resilient coating forms operation;
Make the nano-pillar growth operation of the described nano-pillar selectivity growth that is consisted of by the III group-III nitride semiconductor by the described pattern of described mask layer;
Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.

Claims (5)

1. III nitride semiconductor devices possesses:
Substrate, it is made of SiC or Si;
Mask layer, it is formed on the described substrate, and is formed with the pattern of regulation;
Nano-pillar, its described pattern by described mask layer is optionally grown up, and is made of the III group-III nitride semiconductor;
The III nitride semiconductor layer, it becomes to look high than described nano-pillar on described mask layer.
2. III nitride semiconductor devices as claimed in claim 1, wherein,
Described mask layer is made of non-crystalline material.
3. III nitride semiconductor devices as claimed in claim 2, wherein,
Between described substrate and described mask layer, possesses the resilient coating that is consisted of by the III group-III nitride semiconductor that contains Al.
4. the manufacture method of an III nitride semiconductor devices is made each described III nitride semiconductor devices in the claim 1～3, wherein, comprises:
The mask layer that forms described mask layer at described substrate forms operation;
The nano-pillar growth operation that described pattern by described mask layer is optionally grown up the described nano-pillar that is made of the III group-III nitride semiconductor;
Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.
5. the manufacture method of an III nitride semiconductor devices is made III nitride semiconductor devices claimed in claim 3, wherein, comprises:
On described substrate, form the resilient coating formation operation of described resilient coating by sputtering method;
The mask layer that forms described mask layer at the described substrate that is formed with described resilient coating forms operation;
Make the nano-pillar growth operation of the described nano-pillar selectivity growth that is consisted of by the III group-III nitride semiconductor by the described pattern of described mask layer;
Make the semiconductor layer growth operation of III nitride semiconductor layer growth at described mask layer.
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