JP5161759B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a compound semiconductor device.

  In recent years, GaN-based semiconductor devices such as GaN (gallium nitride) -based high electron mobility transistors (HEMT) have been expected to be applied as high breakdown voltage / high-speed devices due to the wide band gap of GaN. Yes. So far, in the GaN-based HEMT, the best output characteristics are obtained when a SiC substrate is used as the substrate. This is because the lattice constants of GaN and SiC are close, so there are few defects in the GaN layer grown on the SiC substrate, and because the thermal conductivity of the SiC substrate is high, the thermal radiation characteristics are high.

  In addition, in a GaN-based semiconductor device capable of high-frequency operation, a semi-insulating SiC substrate is particularly used. This is to keep the parasitic capacitance low. However, the price of a semi-insulating SiC substrate is very high compared to a conductive SiC substrate. This may impede the spread of GaN-based semiconductor devices such as GaN-based HEMTs despite their excellent performance.

  Therefore, research for manufacturing GaN-based semiconductor devices at low cost has been conducted. For example, in a conventional manufacturing method, first, a nitride-based semiconductor crystal layer is epitaxially grown on a SiC substrate, and then hydrogen ions are implanted into the semiconductor crystal layer. Next, the surface of the semiconductor crystal layer is bonded to the surface of a support substrate such as a silicon substrate. Then, the semiconductor crystal layer is separated along the portion where hydrogen ions are implanted. In this way, a structure in which the semiconductor crystal layer is located on the support substrate is obtained. Thereafter, if a semiconductor element or the like is formed in the semiconductor crystal layer, a semiconductor device can be obtained.

  However, in this conventional method, hydrogen ions remain in the semiconductor crystal layer on the support substrate, which is a heat dissipation member. For this reason, this hydrogen ion becomes a defect and sufficient performance cannot be obtained.

  In another conventional technique, a nanocolumn region is formed on a substrate such as a GaAs substrate or a Si substrate.

  However, in this prior art, when the HEMT is formed, the substrate is removed by long-time wet etching using a strong acid. For this reason, the compound semiconductor layer constituting the HEMT is damaged during the wet etching.

JP 2007-220899 A JP 2007-305869 A

  The objective of this invention is providing the manufacturing method of the compound semiconductor device which can reduce cost, ensuring performance.

In one embodiment of the production method of a compound semiconductor device on a substrate to form an n-type GaN layer in which an opening portion is provided for communicating with the outside, then, form of compound semiconductor crystal layer on the n-type GaN layer To do. Then, for a given etching solution is irradiated with ultraviolet rays in the n-type GaN layer, by photoelectrochemical etching by dissolving the n-type GaN layer, it separates the compound semiconductor crystal layer from the substrate. The opening communicates with the outside at least in a direction perpendicular to the stacking direction of the n-type GaN layer and the compound semiconductor crystal layer. The compound semiconductor crystal layer includes an electron transit layer and an electron supply layer, and an undoped AlGaN layer located between the electron transit layer and the electron supply layer and the n-type GaN layer. In the photoelectrochemical etching, the non-doped AlGaN layer is used as an etching stopper.

  According to the above method for manufacturing a semiconductor device, even if an expensive substrate that affects the crystallinity of the second compound semiconductor crystal layer is selected, this substrate is not included in the compound semiconductor device, so that it is repeatedly used. can do. Therefore, the consumption of the substrate can be reduced and the cost can be reduced. On the other hand, since the crystallinity of the second compound semiconductor crystal layer is ensured, the performance can be maintained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. 1A to 1R are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to the first embodiment in the order of steps.

  In this embodiment, first, as shown in FIG. 1A, a conductive substrate 1 is used as a crystal growth substrate, and an AlN layer 2 having a thickness of about 10 nm to 50 nm is formed on the substrate 1 by, for example, a metal organic chemical vapor phase. A nucleation layer is formed by a growth (MOCVD: metal organic chemical vapor deposition) method or the like. As the substrate 1, for example, a conductive SiC substrate is used. The thickness of the substrate 1 is about 400 μm, for example. The AlN layer 2 may be formed by a sputtering method. Next, a mask layer 3 having an opening 3 a is formed on the AlN layer 2. For example, a silicon oxide film, a silicon nitride film, or a tungsten film is formed as the mask layer 3. In forming the mask layer 3, for example, a silicon oxide film or the like is formed on the AlN layer 2 by a plasma enhanced chemical vapor deposition (PECVD) method or the like, and is patterned in a line shape. The width of the opening 3a is preferably 100 nm or less, and the width of the remaining part of the mask layer 3 is preferably 500 nm or more. If the width of the opening 3a exceeds 100 nm, the width of the n-GaN layer 4 to be formed later becomes wide, and the time taken to remove the n-GaN layer 4 by photoelectrochemical etching performed later becomes longer. Further, when the width of the remaining portion of the mask layer 3 is less than 500 nm, the potassium hydroxide (KOH) aqueous solution used in the photoelectrochemical etching becomes difficult to contact the n-GaN layer 4, and the n-GaN layer 4 It takes longer time to remove.

Thereafter, as shown in FIG. 1B, an n-type n having a thickness of about 200 nm to 1 μm is formed on the AlN layer 2 exposed from the mask layer 3 by, for example, a molecular beam epitaxy (MBE) method. The GaN layer 4 is formed as a first compound semiconductor crystal layer. At this time, for example, solid Ga and NH ₃ gas are used as raw materials. Note that the growth conditions of the n-GaN layer 4 are such that the vertical growth is dominant. For example, the pressure is about 1 × 10 ⁻⁴ Pa to normal pressure, and the growth temperature is 800 ° C. As a result, the n-GaN layer grows in a columnar shape from the opening 3a, and the n-GaN layer 4 provided with the opening communicating with the outside is obtained.

1C to 1D, a non-doped GaN layer 5 having a thickness of 1 μm or more is formed on the n-GaN layer 4 by hydride vapor phase epitaxy (HVPE). . As the source gas, for example, a mixed gas of GaCl and NH ₃ is used. The growth conditions for the GaN layer 5 are such that lateral growth is dominant. For example, the pressure is normal pressure and the growth temperature is 1000 ° C. As a result, under such conditions, the GaN layer 5 grows in a conical shape at the initial stage of growth, and then grows in the lateral direction, as shown in FIG. 1C, the openings between the n-GaN layers 4 are formed. Disappear. Further, when the GaN layer 5 grows, the surface becomes flat as shown in FIG. 1D.

After the formation of the GaN layer 5, as shown in FIG. 1E, an AlGaN layer 6 having a thickness of 50 nm or less is formed on the GaN layer 5 as an etching stopper layer. Next, on the AlGaN layer 6, for example, a non-doped i-GaN layer 7 (electron transit layer) having a thickness of about 0.2 μm to 2 μm (for example, 1 μm) and a non-dope having a thickness of about 2 nm to 10 nm (for example, 5 nm) I-AlGaN layer 8, n-type n-AlGaN layer 9 (electron supply layer) having a thickness of about 2 nm to 50 nm (eg, 30 nm), and n-type n− having a thickness of about 2 nm to 10 nm (eg, 10 nm). The GaN layer 10 is formed in this order. The n-AlGaN layer 9 is doped with, for example, Si at a concentration of 5 × 10 ¹⁸ cm ⁻³ , and the n-GaN layer 10 is also doped with, for example, Si at a concentration of 5 × 10 ¹⁸ cm ^−3. Has been. The GaN layer 5, AlGaN layer 6, i-GaN layer 7, i-AlGaN layer 8, n-AlGaN layer 9, and n-GaN layer 10 constitute a second compound semiconductor crystal layer.

  Subsequently, as shown in FIG. 1F, a resist pattern 51 in which openings 51s and 51d are provided in a region where a source electrode is to be formed and a region where a drain electrode is to be formed is formed on the n-GaN layer 10. .

  Next, by using the resist pattern 51 as a mask and performing dry etching using a chlorine-based gas on the n-GaN layer 10, openings 10s and 10d are formed in the n-GaN layer 10 as shown in FIG. 1G. Form. In addition, regarding the depth of the openings 10s and 10d, a part of the n-GaN layer 10 may be left, or a part of the n-AlGaN layer 9 may be removed. That is, the depths of the openings 10 s and 10 d do not need to match the thickness of the n-GaN layer 10.

  Thereafter, as shown in FIG. 1H, the source electrode 21s is formed in the opening 10s, and the drain electrode 21d is formed in the opening 10d. In forming the source electrode 21s and the drain electrode 21d, for example, a Ti layer is formed by vapor deposition, and an Al layer is formed thereon by vapor deposition. Then, the resist pattern 51 is removed. That is, in the formation of the source electrode 21s and the drain electrode 21d, for example, vapor deposition and lift-off techniques are used.

  Subsequently, heat treatment is performed in a nitrogen atmosphere at 600 ° C. to establish ohmic contact between the source electrode 21s and the drain electrode 21d.

  Next, as shown in FIG. 1I, a passivation film 31 covering the source electrode 21s and the drain electrode 21d is formed on the n-GaN layer 10 by PECVD. For example, a silicon nitride film is formed as the passivation film 31.

  Subsequently, as shown in FIG. 1J, a resist pattern 52 having an opening 52g in a region where a gate electrode is to be formed is formed on the passivation film 31. Next, as shown in FIG.

  Next, by etching the passivation film 31 using the resist pattern 52 as a mask, an opening 31g is formed in the passivation film 31 as shown in FIG. 1K.

  Thereafter, as shown in FIG. 1L, a gate electrode 21g is formed in the opening 31g. In forming the gate electrode 21g, for example, a Ni layer is formed by a vapor deposition method, and an Au layer is formed thereon by a vapor deposition method.

  Then, as shown in FIG. 1M, the resist pattern 52 is removed. That is, even in the formation of the gate electrode 21g, for example, vapor deposition and lift-off techniques are used. Next, a passivation film 32 covering the gate electrode 21g is formed on the passivation film 31 by PECVD. For example, a silicon nitride film is formed as the passivation film 32.

  Thereafter, as shown in FIG. 1N, a surface protective layer 33 is formed on the passivation film 32. The surface protective layer 33 is made of a material having alkali resistance such as wax. Subsequently, a support substrate 34 is attached on the surface protective layer 33. As the support substrate 34, for example, a substrate having alkali resistance such as a Si substrate or a resin substrate is used.

  Next, as shown in FIG. 1O, the n-GaN layer 4 is dissolved by photoelectrochemical etching. As a result, the GaN layer 5 is separated from the AlN layer 2. In this photoelectrochemical etching, as shown in FIG. 2, a back electrode 41 is formed on the back surface of the substrate 1, and the back electrode 41 is connected to the positive electrode of the DC power supply 43. A Pt electrode 42 is connected to the negative pole of the DC power supply 43. That is, a voltage is applied so that the back electrode 41 is an anode and the Pt electrode 42 is a cathode. Then, the structure before separation is immersed in a potassium hydroxide (KOH) aqueous solution 44 in the tank 45, and ultraviolet rays are irradiated toward the back surface of the substrate 1. Irradiation with ultraviolet rays is performed using, for example, a mercury lamp. When ultraviolet rays are irradiated from the back surface, the ultraviolet rays pass through the substrate 1 and are absorbed by the n-GaN layer 4 to excite electron-hole pairs. Then, the n-GaN layer 4 is etched by the influence of the excited holes. The back electrode 41 is formed in a region that does not hinder the incidence of ultraviolet rays, for example, the end surface of the substrate.

Here, the photoelectrochemical etching in the present embodiment will be described. FIG. 3 is a diagram showing a band structure of the GaN layer. In the present embodiment, as shown in FIG. 3A, the band of the n-GaN layer 4 is curved upward at the interface with the KOH aqueous solution 44. For this reason, holes 47 tend to accumulate at the interface between the n-GaN layer 4 and the KOH aqueous solution 44, and the etching reaction via the holes 47 tends to proceed. That is, the n-GaN layer 4 is etched by the following reaction formula using the holes 47 excited by the absorption of ultraviolet rays.
2GaN + 6h ⁺ → 2Ga ⁺ + N ₂

However, since holes 47 are consumed in this reaction, as the etching progresses, the electrons 46 are excessively present in the n-GaN layer 4. If the electrons 46 are excessively present, the etching reaction of the n-GaN layer 4 is hindered. Therefore, in this embodiment, in order to extract the electrons 46 from the n-GaN layer 4, a voltage is applied between the Pt electrode 42 immersed in the KOH aqueous solution 44 and the back electrode 41 to consume the electrons 46. doing. That is, the electrons 46 are reacted with the KOH aqueous solution 44 at the Pt electrode 42 according to the following reaction formula.
2H ^{+ +} 2e ^- → H ₂

  As a result, the etching reaction of the n-GaN layer 4 proceeds without delay.

  Also, if the p-type p-GaN layer 48 is brought into contact with the KOH aqueous solution 44, the band of the p-GaN layer 48 curves downward at the interface with the KOH aqueous solution 44 as shown in FIG. For this reason, the holes 47 are confined inside the p-GaN layer 48, and etching through the holes 47 is hindered.

  In this embodiment, a non-doped GaN layer 5 showing intermediate properties between the n-GaN layer 4 and the p-GaN layer 48 is provided, which also contacts the KOH aqueous solution 44, but the n-GaN Since the layer 4 is preferentially etched, the GaN layer 5 is hardly etched.

  As shown in FIG. 4, the AlGaN layer 6 has a wider band gap than the GaN layer 5. Therefore, there is a band gap discontinuity at the interface between the AlGaN layer 6 and the GaN layer 5. Due to the presence of such discontinuities, the holes 47 excited in the n-GaN layer 4 are inhibited from diffusing up to the i-GaN layer 7 by the AlGaN layer 6, and the n-GaN layer 4 or the GaN layer 5 Exists only in Accordingly, the AlGaN layer 6 functions as an etching and stopper, and the i-GaN layer 7 and the compound semiconductor layer thereon are prevented from being etched.

  In the present embodiment, such photoelectrochemical etching is performed, and the GaN layer 5 is separated from the AlN layer 2.

  After the separation of the GaN layer 5 and the AlN layer 2, as shown in FIG. 1P, the GaN layer 5 and the AlGaN located below the i-GaN layer 7 by a chemical mechanical polishing (CMP) method or the like. The layer 6 is removed, and the back surface of the i-GaN layer 7 is planarized. If the back surface is planarized, the GaN layer 5 and the AlGaN layer 6 may be left, or only the AlGaN layer 6 may be left.

Next, for example, as shown in FIG. 1Q, the heat dissipation substrate 35 is bonded to the back surface of the i-GaN layer 7 as an insulating heat dissipation member by a wafer direct bonding method. As the heat dissipation substrate 35, an AlN substrate, an amorphous SiC substrate, an amorphous C (diamond like carbon (DLC)) substrate, or the like is used. In this bonding, the back surface of the i-GaN layer 7 is cleaned by acid cleaning, and then the back surface is made hydrophilic by O ₂ plasma treatment or the like. Similarly, hydrophilic treatment is also performed on the surface of the heat dissipation substrate 35. Then, the surfaces subjected to the hydrophilic treatment are overlapped and joined. Thereafter, heat treatment is performed at a temperature within a range in which the HEMT including the gate electrode 21g, the source electrode 21s, and the drain electrode 21d is not destroyed, for example, 400 ° C., thereby improving the bonding strength between the heat dissipation substrate 35 and the i-GaN layer 7. .

  Subsequently, as shown in FIG. 1R, the surface protective layer 33 and the support substrate 34 are removed. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  On the other hand, for the structure of the substrate 1, the AlN layer 2 and the mask layer 3 separated from the GaN layer 5, the surface of the substrate 1 where the AlN layer 2 and the mask layer 3 are present is polished by a CMP method or the like, and the AlN layer 2 Then, the mask layer 3 is removed, and the surface of the substrate 1 is polished and flattened by about 100 nm. It can be said that the state of the substrate 1 after planarization has not changed except that it is slightly thinner than before the formation of the AlN layer 2. Therefore, if the substrate 1 is processed after the formation of the AlN layer 2, a GaN-based HEMT can be repeatedly formed.

  In addition, since the characteristics of the heat dissipation substrate 35 do not affect the crystallinity of the i-GaN layer 7, it is only necessary to ensure insulation and high heat dissipation (thermal conductivity). Accordingly, the performance of the GaN-based HEMT does not deteriorate even when a conductive SiC substrate such as an AlN substrate, an amorphous SiC substrate, or an amorphous C substrate and a semi-insulating SiC substrate are used. As described above, in the first embodiment, even if an expensive substrate 1 as a crystal growth substrate is used, the substrate 1 is not a constituent element of the GaN-based HEMT and is inexpensive as the heat dissipation substrate 35. Since sufficient performance can be obtained even if a product is used, cost can be reduced while obtaining high performance.

  It is also possible to use a diamond substrate as the heat dissipation substrate 35. In this case, the cost may increase, but higher heat dissipation can be obtained as compared with a semi-insulating SiC substrate. A BN substrate can also be used as the heat dissipation substrate 35.

  In the semiconductor device manufactured by such a method, the crystallinity (such as the presence or absence of crystal defects) of the i-GaN layer 7 that is a compound semiconductor crystal layer depends on the atomic arrangement of the substrate 1 and is a heat dissipation member that is a heat dissipation member. This is independent from the atomic arrangement in the substrate 35.

  Note that the pattern of the mask layer 3 does not have to be a line if photoelectrochemical etching is possible and the opening can be closed by the GaN layer 5. For example, a lattice shape or a dot shape may be used. Moreover, the dimension of patterns, such as opening part 3a, is not specifically limited. Also, the growth conditions of the GaN layer 5 are not particularly limited as long as the lateral growth is dominant and the opening can be closed.

  Further, a columnar crystal layer called a nanocolumn or the like may be used as the n-GaN layer 4. In this case, if a self-forming nanocolumn is used, the mask layer 3 is unnecessary.

(Second Embodiment)
Next, a second embodiment will be described. 6A to 6B are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (semiconductor device) according to the second embodiment in the order of steps.

In this embodiment, first, similarly to the first embodiment, processing up to dissolution of the n-GaN layer 4 by photoelectrochemical etching is performed (FIG. 1O). Next, as shown in FIG. 6A, a DLC film 61 is formed on the back surface of the GaN layer 5 as an insulating heat dissipation member by plasma ion implantation and deposition (PBII & D). In forming the DLC film 61, for example, a structure including the support substrate 34, the GaN layer 5 and the like is placed in a chamber, and C ₂ H _{2 is} generated in the chamber by high frequency (pulse voltage: 20 kV, pulse width: 10 μs). Excites the plasma. Subsequently, a negative high voltage pulse (pulse voltage: −20 kV, pulse width: 5 μs) is applied. Such plasma excitation and voltage application are repeated until a DLC film 61 having a predetermined thickness is obtained.

  After the DLC film 61 is formed, the surface protective layer 33 and the support substrate 34 are removed as shown in FIG. 6B. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT.

  The effect similar to 1st Embodiment can be acquired also by such 2nd Embodiment. In addition, since it is not necessary to polish the GaN layer 5 or the like, the number of steps can be reduced as compared with the first embodiment.

  When applying a negative high voltage pulse, it is preferable to adjust the duty ratio of the high voltage pulse so that the process temperature is 200 ° C. or lower. For this purpose, the duty ratio is set to 10% or less, for example.

Further, before the DLC film 61 is formed, it is preferable to clean the back surface of the GaN layer 5 using Ar gas. In addition, it is also preferable to improve adhesion with the DLC film 61 by attaching carbon atoms and hydrogen atoms to the back surface of the GaN layer 5 using CH ₄ gas. Also, nitrogen atoms are ion-implanted into the back surface of the GaN layer 5, and then carbon atoms are ion-implanted into the back surface of the GaN layer 5, thereby preventing adhesion of carbon atoms into the GaN layer 5. It is also preferable to improve it.

  Similarly, in order to improve adhesion, it is also preferable to form an amorphous SiC layer as an intermediate layer on the back surface of the GaN layer 5 by sputtering before forming the DLC film 61.

  Further, if the material of the heat dissipation member is excellent in insulation and heat radiation characteristics, it is not necessary to be DLC. Instead of the DLC film 61, an AlN film or SiC film formed by an aerosol deposition method or the like is used. Also good.

(Third embodiment)
Next, a third embodiment will be described. 7A to 7D are sectional views showing a method of manufacturing a GaN-based HEMT (semiconductor device) according to the third embodiment in the order of steps.

  In this embodiment, first, as shown in FIG. 7A, an AlN layer 2 is formed as a nucleation layer on a substrate 1 in the same manner as in the first embodiment. However, in this embodiment, as the substrate 1, for example, a semi-insulating SiC substrate or a sapphire substrate or a zinc oxide substrate which is an insulating substrate is used. Next, an n-GaN layer 71 having a thickness of about 20 nm to 100 nm (for example, 100 nm) is formed on the AlN layer 2 by the MBE method or the like.

  Thereafter, as shown in FIG. 7B, a tungsten film 72 that covers the entire substrate 1, the AlN layer 2, and the n-GaN layer 71 is formed by a CVD method or the like. The thickness of the tungsten film 72 is about 50 nm to 200 nm (for example, 150 nm).

  Subsequently, as shown in FIG. 7C, a line-shaped opening 72 a is formed in the tungsten film 72 on the n-GaN layer 71. As with the opening 3a, the width of the opening 72a is preferably 100 nm or less, and the width of the remaining portion of the tungsten film 72 is preferably 500 nm or more.

  7C, an opening 72b is formed in the tungsten film 72 on the back surface of the substrate 1. In forming the opening 72b, it is preferable to leave a part of the tungsten film 72 on the back surface of the substrate 1 and to expose a wide area of the substrate 1 so that the substrate 1 is easily irradiated with ultraviolet rays later. Is preferred.

  Next, as illustrated in FIG. 7D, the n-GaN layer 4 is formed on the n-GaN layer 71 exposed from the tungsten film 72 in the same manner as in the first embodiment.

  Thereafter, similarly to the first embodiment, processing after the formation of the GaN layer 5 is performed to complete the GaN-based HEMT.

  However, in this embodiment, the back electrode 41 is formed not on the back surface of the substrate 1 but on the tungsten film 72 during photoelectrochemical etching. This is because an insulating or semi-insulating substrate 1 is used. In this embodiment, since the n-GaN layer 71 is formed above the substrate 1 and below the patterned tungsten film 72, each part of the n-GaN layer 4 is formed during photoelectrochemical etching. A predetermined potential (potential of the back electrode 41) is easily applied uniformly. This is the same as the pattern of the opening 3a, and the pattern of the opening 72a is not particularly limited, and is effective when it has a lattice shape or a dot shape.

  After the photoelectrochemical etching, as shown in FIG. 8A, a structure of the substrate 1, the AlN layer 2, the n-GaN layer 71, and the tungsten film 72 is obtained. For this structure, first, the tungsten film 72 is removed using an acid, and then the surface of the substrate 1 where the AlN layer 2 and the n-GaN layer 71 are present is polished by CMP or the like to obtain the AlN layer 2 and n The GaN layer 71 is removed, and the surface of the substrate 1 is polished and flattened by about 100 nm. It can be said that the state of the substrate 1 after planarization has not changed except that it is slightly thinner than before the formation of the AlN layer 2. Therefore, if the substrate 1 is processed after the formation of the AlN layer 2, a GaN-based HEMT can be repeatedly formed.

  According to the third embodiment as described above, the same effect as that of the first embodiment can be obtained. Further, if a sapphire substrate that is less expensive than a conductive SiC substrate is used, a GaN-based HEMT can be manufactured at a lower cost.

  As in the second embodiment, the DLC film 61 may be formed while leaving the GaN layer 5 left.

  Further, instead of the tungsten film 72, another refractory metal film may be used. The refractory metal is used because it is exposed to a high temperature when the compound semiconductor layer is formed.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 9 is a cross-sectional view showing a method of manufacturing a GaN-based HEMT (semiconductor device) according to the fourth embodiment in the order of steps.

  In the fourth embodiment, as shown in FIG. 9, before the GaN layer 5 is formed on the n-GaN layer 4, the AlGaN layer 16 is formed on the n-GaN layer 4 as an etching stopper layer. . Further, the i-GaN layer 7 is formed directly on the GaN layer 5 without forming the AlGaN layer 6. Other configurations are the same as those of the first embodiment.

  According to the fourth embodiment, since the AlGaN layer 16 that functions as an etching stopper layer exists between the n-GaN layer 4 and the GaN layer 5, Dissolution can be more reliably suppressed.

  In the fourth embodiment, the AlGaN layer 6 may be formed as in the first embodiment. Further, the second embodiment and / or the third embodiment may be combined with the fourth embodiment. That is, the DLC film 61 or the like may be used as the heat radiating member, and conduction may be ensured by the tungsten film 72 while using the insulating or semi-insulating substrate 1.

  Note that the GaN-based HEMT manufactured by these methods can be used, for example, for a high-power amplifier included in a base station for wireless communication. Moreover, it can be used for a DC-DC converter, an AC-AC converter, an AC-DC converter, a high frequency power source, etc. as a power supply application. In power supply applications, it is possible to reduce the size of passive components and reduce the number of elements by increasing the frequency by utilizing the high breakdown voltage, low loss, and high-speed switching characteristics of GaN. It becomes possible. And by these, size reduction, weight reduction, and cost reduction of a power converter device are realizable.

  The material of the nucleation layer is not limited to AlN, and can be appropriately selected depending on the crystal layer formed thereon. For example, when the crystal layer formed thereon is a GaN-based crystal layer, an AlN-based crystal layer can be used as the nucleation layer. Further, the material of the compound semiconductor crystal layer is not limited. For example, a nitride semiconductor such as GaN, AlN, or InN may be used alone, or a mixed crystal of two or more of these may be used.

  Further, the growth conditions of the compound semiconductor crystal layer are not particularly limited. Various epitaxial lateral overgrowth (ELO) techniques have been developed for GaN-based crystal layers. For example, FIELO (facet-initiated ELO) technology based on the HVPE method as described above, and FACELO (facet-controlled ELO) technology based on the metal-organic vapor phase epitaxy (MOVPE) method have been developed. ing.

  Further, the semiconductor element formed on the compound semiconductor crystal layer is not limited to HEMT. For example, an insulated gate bipolar transistor (IGBT) may be formed.

  An etching solution used for photoelectrochemical etching is not limited to a potassium hydroxide aqueous solution (KOH aqueous solution), but it is preferable to use a weak alkaline aqueous solution that causes little damage to the compound semiconductor layer.

It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 1B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1A. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1B. 1C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1C. 2D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1D. 2E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1E. 1F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1F. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1G. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1H. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1I. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1J. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1K. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1L. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1M. 1N is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1N. FIG. 10 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 10. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1P. FIG. 2 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 1Q. It is a figure which shows the detail of photoelectrochemical etching. It is a figure which shows the band structure of a GaN layer. FIG. 6 is a band diagram showing the operation of the AlGaN layer 6. It is sectional drawing which shows the reuse method of the board | substrate 1 in 1st Embodiment. FIG. 5B is a cross-sectional view illustrating a method of reusing the substrate 1 following FIG. 5A. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6A. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7A. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7B. 7C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7C. It is sectional drawing which shows the reuse method of the board | substrate 1 in 3rd Embodiment. FIG. 8B is a cross-sectional view illustrating a method of reusing the substrate 1 following FIG. 8A. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 4th Embodiment.

Explanation of symbols

1: Substrate 2: AlN layer 3: Mask layer 3a: Opening 4: n-GaN layer 5: GaN layer 6: AlGaN layer 7: i-GaN layer 8: i-AlGaN layer 9: n-AlGaN layer 10: n -GaN layer 21d: Drain electrode 21g: Gate electrode 21s: Source electrode 33: Surface protective layer 34: Support substrate 35: Heat dissipation substrate 41: Back electrode 42: Pt electrode 43: DC power supply 44: KOH aqueous solution 45: Tank 61: DLC Film 71: n-GaN layer 72: Tungsten film 72a, 72b: Opening

Claims (5)

Forming an n-type GaN layer provided with an opening communicating with the outside on the substrate;
Forming a compound semiconductor crystal layer into the n-type GaN layer,
In a predetermined etching solution, by irradiating ultraviolet rays to the n-type GaN layer, and the photoelectrochemical etching to dissolve the n-type GaN layer, and the step to separate the active said compound semiconductor crystal layer from the substrate,
I have a,
The opening communicates with the outside at least in a direction perpendicular to the stacking direction of the n-type GaN layer and the compound semiconductor crystal layer,
The compound semiconductor crystal layer has an electron transit layer and an electron supply layer, and the electron transit layer and the non-doped AlGaN layer located between the electron supply layer and the n-type GaN layer,
A method of manufacturing a compound semiconductor device , wherein the non-doped AlGaN layer is used as an etching stopper during the photoelectrochemical etching . As before asked compound semiconductor crystal layer, the production method of a compound semiconductor device according to claim 1, characterized in that a nitride semiconductor crystal layer.   3. The method of manufacturing a compound semiconductor device according to claim 2, wherein the nitride semiconductor crystal layer is made of one or more mixed crystals selected from the group consisting of GaN, AlN, and InN. .   The method of manufacturing a compound semiconductor device according to claim 1, wherein a SiC substrate is used as the substrate. After the step of dissolving the n-type GaN layer, the compounds described in the preceding claim 1 to 4, further comprising the step of providing a backside heat radiation member asked compound semiconductor crystal layer A method for manufacturing a semiconductor device.

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