CN102931175A - Thyristor module - Google Patents

Thyristor module Download PDF

Info

Publication number
CN102931175A
CN102931175A CN2012104581071A CN201210458107A CN102931175A CN 102931175 A CN102931175 A CN 102931175A CN 2012104581071 A CN2012104581071 A CN 2012104581071A CN 201210458107 A CN201210458107 A CN 201210458107A CN 102931175 A CN102931175 A CN 102931175A
Authority
CN
China
Prior art keywords
chip
electrode
district
signal terminal
conductor wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012104581071A
Other languages
Chinese (zh)
Other versions
CN102931175B (en
Inventor
周锦源
柏治国
蒋陆金
臧凯晋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Yang Jie Semiconductor Co., Ltd.
Original Assignee
JIANGSU APT SEMICONDUCTOR CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIANGSU APT SEMICONDUCTOR CO Ltd filed Critical JIANGSU APT SEMICONDUCTOR CO Ltd
Priority to CN201210458107.1A priority Critical patent/CN102931175B/en
Publication of CN102931175A publication Critical patent/CN102931175A/en
Application granted granted Critical
Publication of CN102931175B publication Critical patent/CN102931175B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)

Abstract

The invention discloses a thyristor module, belonging to the field of manufacturing of power semiconductor modules. The thyristor module adopts a new way to connect a chip and a signal end, therefore, the process and the material are simplified, and the product has connecting structure which is high in reliability and consistency, thereby remarkably optimizing the performance of the product. The thyristor module comprises a bottom plate, a housing, a substrate, a chip I, a chip II, an electrode I, an electrode II, an electrode III, a signal terminal Ga, a signal terminal Ka, a signal terminal Kb and a signal terminal Gb; the front surfaces of the two chips are provided with positive electrodes A, and the back surfaces are provided with negative electrodes K and gates G; and a conductive block zone I, a conductive block zone II, a conductive block zone III, a conductive wire zone I, a conductive wire zone II, a conductive wire zone III and a conductive wire zone IV which are mutually insulated are printed on the top surface of the substrate. According to the thyristor module, the consistency of the product is greatly improved, and the reliability is enhanced as well. Therefore, the raw materials and the process steps of the product are greatly simplified, the manufacturing yield is improved, the performance and the consistency are remarkably enhanced, and the reliability is improved.

Description

A kind of thyristor module
Technical field
A kind of thyristor power model and signal terminal inner connecting way thereof belong to power semiconductor modular and make the field.
Background technology
The thyristor power model is the aggregate that several thyristor chips are packaged together according to certain topological functions.General, in a power model, the bottom surface of these thyristor chips is welded on the metal surface of insulated substrate.This insulated substrate also has simultaneously good heat dispersion and realizes relative electric insulation with radiating bottom plate so that chip bottom can realize electrical connection.The upper surface of chip is metallized (being generally ag material), can realize with the mode of welding molybdenum sheet and metal connecting bridge electrical connection.These power components can use silica gel fully to cover in module, so that element is fully insulated and avoids environmental nuisance.
Thyristor chip 4 contains three utmost points, and the general back side is anode A 41, and the front is negative electrode K42 and gate pole G43, and structure is shown in Fig. 8,9.Usually, thyristor module mainly by thyristor chip (Thyristor), cover copper ceramic substrate (DBC), copper soleplate and the formations such as shell, electrode and holding wire.Use according to thyristor module needs, and in the inside of module, the gate pole G43 of chip is connected the signal terminal corresponding with module to connect respectively with negative electrode K42, circuit diagram such as Fig. 7.
Chip 4 and signal end routinely connected mode are: chip surface (negative electrode 42) welding molybdenum sheet, be connected with the DBC Copper Foil with connecting bridge 5 connections at molybdenum sheet, then the regional end that welds higher temperature line 9 of identical DBC Copper Foil; An other end of higher temperature line 9 and signal terminal (terminal one ~ 4 21 ~ 24) link together with flatiron welding or electric current spot welding, thereby realize electrical connection.For guaranteeing that signal end fixes, need to fix signal end with plastic support frame 81, such as Figure 10 in addition.
The major defect of the mode of present this connection has: higher temperature line 9 and DBC plate Copper Foil zone 51(are as shown in figure 10) welding be point and the welding of face, technology difficulty is large.In module package technique, this step is soldering, need to use special frock to fix higher temperature line 9; The welding ends of higher temperature line 9 need to pass through wire stripping, the preliminary treatment such as upper tin; Operating personnel's installation step is loaded down with trivial details; Technological effect is undesirable in addition, even use the soldering under the vacuum reduction environment, doing over again of significant proportion is arranged still, increases man-hour and cost.
Higher temperature line 9 and signal terminal (21 ~ 24) to be connected the potential failure risk high.When using spot welding, usually so that the copper core of higher temperature line 9 by ironed, it is very large that this connection is affected by the clean conditions of material surface, and the risk of rosin joint is often arranged, and be difficult in time being found.
The higher temperature line that connects negative electrode twines the purpose of eliminating inductance to reach mutually with the higher temperature line needs that are connected gate pole.And every product of same model needs to keep chip to the cable run distance consistent (although the length that shows among Figure 10 is inconsistent, in actual product, the length requirement of four higher temperature lines 9 is the same) of signal end.The realization difficulty is large, and inefficacy is many.The fixing higher temperature line 9 of unsettled nothing is pushed down by shell in subsequent operation easily in addition, causes new inefficacy.
Summary of the invention
The present invention is directed to above problem, a kind of thyristor module is provided; It has adopted the connected mode of brand-new chip and signal end, and then can simplify technique and material, so that product has high reliability and high conforming syndeton, thus remarkable optimizing product performance.
Technical scheme of the present invention is: comprise base plate, housing, substrate, chip one, chip two, electrode one, electrode two, electrode three, signal terminal Ga, signal terminal Ka, signal terminal Kb and signal terminal Gb; The front of two described chips is anode A, and the back side is provided with negative electrode K and gate pole G; The end face of described substrate is printed with conducting block district one, conducting block district two, conducting block district three, conductor wire district one, conductor wire district two, conductor wire district three and the conductor wire district four of mutually insulated;
The anode A of described electrode one, chip one be connected the negative electrode K of chip two and connect described conducting block district one;
Described electrode two be connected the negative electrode K of chip one and connect described conducting block district two;
The anode A of described electrode three, chip two connects described conducting block district three;
The gate pole G of described chip one connects described conductor wire district one by aluminium wire, and described conductor wire district connects described signal terminal Ga again and again;
The negative electrode K of described chip one connects described conductor wire district two by connecting bridge, and described conductor wire district two connects described signal terminal Ka again;
The negative electrode K of described chip two connects described conductor wire district three by connecting bridge, and described conductor wire district three connects described signal terminal Kb again;
The gate pole G of described chip two connects described conductor wire district four by aluminium wire, and described conductor wire district four connects described signal terminal Gb again.
Described electrode one comprises sheet noumenon and connecting pin, described connecting pin is double-legged structure, comprise connecting pin one, connecting pin two and the horizontal part that connects, described connecting pin one and connecting pin two are in and describedly horizontally connect the bottom of part and link to each other by the described horizontal part that connects, and the described horizontal top partly that connects connects described body; The bottom surface of described connecting pin one is joint face one, and the bottom surface of described connecting pin two is to form the span syndeton between joint face two, the two described joint faces.
The area sum of described joint face one and joint face two equals described electrode two working face areas, equals the work area of described electrode three.
Each described signal terminal bottom has S shape footing; It is curved that described S type footing is divided into the curved and lower C type of C type, and the curved degree of depth of described upper C type is greater than the curved degree of depth of described lower C type.
The gate pole of chips of the present invention is connected conductor wire district one, four and is realized connecting by the aluminium wire bonding techniques with the DBC Copper Foil; The negative electrode of chip still adopts routine techniques to draw.New DBC layout (being seven conductor wires, the piece zone that substrate top surface is printed in this case) is so that direct cabling between DBC Copper Foil (zone).Signal end can directly be welded between the DBC Copper Foil.Like this, just realized the functional requirement of module.The contrast routine techniques has been cancelled higher temperature line, the structural members such as plastic support frame; Say the pretreating process of having cancelled higher temperature line from technological angle, the welding procedure of higher temperature line one end and the spot-welding technology of the other end, and the winding step of higher temperature line.Know-why of the present invention: 1. the aluminium wire bonding techniques is mainly used on the chip of aluminium surface or gold surface, so that aluminium wire becomes the through-flow carrier of power model.And thyristor chip is silver surface, and is because silver can move, general and inapplicable.But the present invention has overcome this technology prejudice, and in the present invention, the bonding aluminium wire is only born several milliamperes weak current, although silver-colored transport phenomena proves that by a series of reliability certifications and senile experiment enough supporting modules of its life-span are reliable.2.DBC in the layout, the K polar curve is a pair of equidistant parallel Copper Foil (conductor wire district one, conductor wire district two) with the G polar curve, when replacing higher temperature line connection simplification material and technique, its track lengths all is identical with mode for every module, thereby so that homogeneity of product improves greatly, reliability also improves thereupon.Product raw material and processing step that the present invention makes are significantly simplified, and manufacturing yield of products promotes, and performance and consistency significantly improve, and reliability increases.
Description of drawings
Fig. 1 is the in-built structural representation of thyristor of the present invention,
Fig. 2 is the left view of Fig. 1,
Fig. 3 is the vertical view of Fig. 1,
Fig. 4 is the stereogram of electrode one among the present invention,
Fig. 5 is the stereogram one after thyristor of the present invention is removed housing and silicon gel layer,
Fig. 6 is the stereogram two after thyristor of the present invention is removed housing and silicon gel layer,
Fig. 7 is circuit theory diagrams of the present invention,
Fig. 8 is chip back structural representation of the present invention,
Fig. 9 is chip front side structural representation of the present invention,
Figure 10 is in-built structural representation in the background technology of the present invention;
Among the figure:
The 11st, electrode one, 111st, connecting pin one, 1110th, joint face one, 112nd, connecting pin two, 1120th, joint face two, 12nd, electrode two, 13rd, electrode three,
The 21st, signal terminal Ga, the 22nd, signal terminal Ka, the 23rd, signal terminal Kb, the 24th, signal terminal Gb, the 211st, S type structure, the 2111st, upper C type is curved, and the 2112nd, lower C type is curved,
The 3rd, substrate, the 30th, cover the copper conductive layer, the 311st, conducting block district one, 312nd, conducting block district two, 313rd, conducting block district three, 321st, conductor wire district one, 322nd, conductor wire district two, 323rd, conductor wire district three, 324th, conductor wire district four,
The 4th, chip, 4a are chips one, and 4b is chip two, 40th, molybdenum sheet, and the 41st, anode A, the 42nd, negative electrode K, the 43rd, gate pole G,
The 5th, connecting bridge one, 6th, aluminium wire, the 7th, connecting bridge two, 8th, base plate, the 81st, plastic support frame, the 9th, higher temperature line.
Embodiment
The present invention comprises base plate, housing, substrate, chip one, chip two, electrode one, electrode two, electrode three, signal terminal Ga, signal terminal Ka, signal terminal Kb and signal terminal Gb shown in Fig. 1-6; The front of two described chips is anode A, and the back side is provided with negative electrode K and gate pole G; The end face of described substrate is printed with conducting block district one, conducting block district two, conducting block district three, conductor wire district one, conductor wire district two, conductor wire district three and the conductor wire district four of mutually insulated;
The anode A of described electrode one, chip one be connected the negative electrode K of chip two and connect described conducting block district one;
Described electrode two be connected the negative electrode K of chip one and connect described conducting block district two;
The anode A of described electrode three, chip two connects described conducting block district three;
The gate pole G of described chip one connects described conductor wire district one by aluminium wire, and described conductor wire district connects described signal terminal Ga again and again;
The negative electrode K of described chip one connects described conductor wire district two by connecting bridge, and described conductor wire district two connects described signal terminal Ka again;
The negative electrode K of described chip two connects described conductor wire district three by connecting bridge, and described conductor wire district three connects described signal terminal Kb again;
The gate pole G of described chip two connects described conductor wire district four by aluminium wire, and described conductor wire district four connects described signal terminal Gb again.
Described electrode one comprises sheet noumenon and connecting pin, described connecting pin is double-legged structure, comprise connecting pin one, connecting pin two and the horizontal part that connects, described connecting pin one and connecting pin two are in and describedly horizontally connect the bottom of part and link to each other by the described horizontal part that connects, and the described horizontal top partly that connects connects described body; The bottom surface of described connecting pin one is joint face one, and the bottom surface of described connecting pin two is to form the span syndeton between joint face two, the two described joint faces.Two pin are when considering design so that more compact structure and flexible on same conducting surface.If also use single pin, DBC just need to prolong at least length of 4mm so, in other words, adopts double-legged structure, has effectively utilized the space of chip one both sides.
The area sum of described joint face one and joint face two equals described electrode two working face areas, equals the work area of described electrode three.The conductive area of each electrode is consistent like this, so that electrical property has consistency; After the welding because area is consistent, so that the bonding strength of conductive area is consistent on each electrode and the substrate.
Each described signal terminal bottom has S shape footing; It is curved that described S type footing is divided into the curved and lower C type of C type, and the curved degree of depth of described upper C type is greater than the curved degree of depth of described lower C type.

Claims (4)

1. a thyristor module comprises base plate, housing, substrate, chip one, chip two, electrode one, electrode two, electrode three, signal terminal Ga, signal terminal Ka, signal terminal Kb and signal terminal Gb; The front of two described chips is anode A, and the back side is provided with negative electrode K and gate pole G; It is characterized in that the end face of described substrate is printed with conducting block district one, conducting block district two, conducting block district three, conductor wire district one, conductor wire district two, conductor wire district three and the conductor wire district four of mutually insulated;
The anode A of described electrode one, chip one be connected the negative electrode K of chip two and connect described conducting block district one;
Described electrode two be connected the negative electrode K of chip one and connect described conducting block district two;
The anode A of described electrode three, chip two connects described conducting block district three;
The gate pole G of described chip one connects described conductor wire district one by aluminium wire, and described conductor wire district connects described signal terminal Ga again and again;
The negative electrode K of described chip one connects described conductor wire district two by connecting bridge, and described conductor wire district two connects described signal terminal Ka again;
The negative electrode K of described chip two connects described conductor wire district three by connecting bridge, and described conductor wire district three connects described signal terminal Kb again;
The gate pole G of described chip two connects described conductor wire district four by aluminium wire, and described conductor wire district four connects described signal terminal Gb again.
2. a kind of thyristor module according to claim 1, it is characterized in that, described electrode one comprises sheet noumenon and connecting pin, described connecting pin is double-legged structure, comprise connecting pin one, connecting pin two and the horizontal part that connects, described connecting pin one and connecting pin two are in and describedly horizontally connect the bottom of part and link to each other by the described horizontal part that connects, and the described horizontal top partly that connects connects described body; The bottom surface of described connecting pin one is joint face one, and the bottom surface of described connecting pin two is to form the span syndeton between joint face two, the two described joint faces.
3. a kind of thyristor module according to claim 2 is characterized in that, the area sum of described joint face one and joint face two equals described electrode two working face areas, equals the work area of described electrode three.
4. a kind of thyristor module according to claim 1 is characterized in that, each described signal terminal bottom has S shape footing; It is curved that described S type footing is divided into the curved and lower C type of C type, and the curved degree of depth of described upper C type is greater than the curved degree of depth of described lower C type.
CN201210458107.1A 2012-11-14 2012-11-14 Thyristor module Active CN102931175B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210458107.1A CN102931175B (en) 2012-11-14 2012-11-14 Thyristor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210458107.1A CN102931175B (en) 2012-11-14 2012-11-14 Thyristor module

Publications (2)

Publication Number Publication Date
CN102931175A true CN102931175A (en) 2013-02-13
CN102931175B CN102931175B (en) 2015-04-08

Family

ID=47645942

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210458107.1A Active CN102931175B (en) 2012-11-14 2012-11-14 Thyristor module

Country Status (1)

Country Link
CN (1) CN102931175B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172262A (en) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp Manufacture of semiconductor module
US5705848A (en) * 1995-11-24 1998-01-06 Asea Brown Boveri Ag Power semiconductor module having a plurality of submodules
CN102136469A (en) * 2009-11-19 2011-07-27 英飞凌科技股份有限公司 Power semiconductor module and method for operating a power semiconductor module
CN201927602U (en) * 2010-11-11 2011-08-10 嘉兴斯达微电子有限公司 Power module comprising special power terminal
CN202352664U (en) * 2011-11-30 2012-07-25 江苏宏微科技有限公司 Power module controlled by direct current motor excitation
CN202888171U (en) * 2012-11-14 2013-04-17 江苏爱普特半导体有限公司 Thyristor module

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172262A (en) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp Manufacture of semiconductor module
US5705848A (en) * 1995-11-24 1998-01-06 Asea Brown Boveri Ag Power semiconductor module having a plurality of submodules
CN102136469A (en) * 2009-11-19 2011-07-27 英飞凌科技股份有限公司 Power semiconductor module and method for operating a power semiconductor module
CN201927602U (en) * 2010-11-11 2011-08-10 嘉兴斯达微电子有限公司 Power module comprising special power terminal
CN202352664U (en) * 2011-11-30 2012-07-25 江苏宏微科技有限公司 Power module controlled by direct current motor excitation
CN202888171U (en) * 2012-11-14 2013-04-17 江苏爱普特半导体有限公司 Thyristor module

Also Published As

Publication number Publication date
CN102931175B (en) 2015-04-08

Similar Documents

Publication Publication Date Title
CN100539137C (en) Power semiconductor modular and manufacture method thereof as the H-bridge circuit
CN100527411C (en) Semiconductor device
CN101452925B (en) Semiconductor device
CN102244066B (en) Power semiconductor module
CN204046434U (en) Three-phase commutation bridge power model
CN103994359A (en) Modularized LED lamp strip and processing method thereof
CN202888171U (en) Thyristor module
CN205657051U (en) Full siC power semiconductor module of half -bridge structure
CN102842549B (en) The power MOSFET package body of square flat non-pin
CN205336219U (en) Photovoltaic terminal box and diode
CN102931175B (en) Thyristor module
CN106098649A (en) High-power surface mount elements and processing tool, manufacture method
CN111863789B (en) Low inductance power module
CN207149616U (en) Battery welding device and battery modules
CN213691998U (en) Novel power semiconductor module of design
CN211428165U (en) High-heat-dissipation and high-reliability IGBT power module structure
CN209029372U (en) One kind being used for high-power multi-die packages structure
CN204596786U (en) A kind of power model
CN103078477B (en) Connection structure of intelligent power module terminal
CN103779341A (en) High-power half-bridge module
CN108010975B (en) Bypass diode for solar power generation assembly
CN216928548U (en) Copper-clad ceramic plate for IGBT module
CN104916612A (en) Power module and making method thereof
CN218069639U (en) Frame for multi-core group capacitor
CN214544232U (en) Four-side-path five-outlet diode module

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee
CP01 Change in the name or title of a patent holder

Address after: 225008 No. 26 Middle Road, Pioneer Park, Weiyang Economic Development Zone, Jiangsu, Yangzhou

Patentee after: Jiangsu Yang Jie Semiconductor Co., Ltd.

Address before: 225008 No. 26 Middle Road, Pioneer Park, Weiyang Economic Development Zone, Jiangsu, Yangzhou

Patentee before: Jiangsu APT Semiconductor Co., Ltd.