CN102931069A - 栅极的制作方法 - Google Patents

栅极的制作方法 Download PDF

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CN102931069A
CN102931069A CN2012104966089A CN201210496608A CN102931069A CN 102931069 A CN102931069 A CN 102931069A CN 2012104966089 A CN2012104966089 A CN 2012104966089A CN 201210496608 A CN201210496608 A CN 201210496608A CN 102931069 A CN102931069 A CN 102931069A
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周军
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Shanghai Huali Microelectronics Corp
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities

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Abstract

本发明提供了一种栅极的制作方法，包括：提供半导体衬底，所述半导体衬底上形成有多晶硅层、硬掩膜层、抗反射层和光刻胶层；以所述抗刻蚀层和光刻胶层为掩膜，对硬掩膜层进行刻蚀；采用SiCoNi工艺对刻蚀后的硬掩膜层进行消减，直至消减后的硬掩膜层的特征尺寸达到工艺要求；以消减后的硬掩膜层为掩膜，刻蚀所述多晶硅层，形成栅极。本发明能更加精确地控制硬掩膜层削减时的厚度和形貌，最终能够获得更小的CD的栅极并能够改善栅极的形貌。

Description

栅极的制作方法
技术领域
本发明涉及半导体技术领域，尤其涉及栅极的制作方法。
背景技术
在半导体发展工艺中，一个集成电路（integrated circuit，简称IC）往往包括了上百万个电子器件，而随着工艺的发展以及不断提升的应用要求，集成电路向微细化、多层化、平坦化、薄型化发展，而超大规模的集成电路中，仅仅几毫米见方的硅片上集成上万至百万晶体管。
而随着器件尺寸的进一步缩小，其制造工艺要求也经受着重大挑战。其中，在MOS晶体管器件和电路制备中，随着器件尺寸缩小，如何在衬底上形成更小的形状规整的多晶栅不断冲击着现有半导体制备技术。
在常规技术中，人们一直以来都是在刻蚀的过程中对多晶栅的硬掩膜进行削减（trim），使其小到一定特征尺寸(CD,characterized dimension)，然后通过对硬掩膜的刻蚀来得到一定特征尺寸的多晶栅极。但是通过刻蚀过程来削减硬掩膜，其消减的过程不是完全线性的，因此当需要削减的时间较长时，对CD的控制会不精确，而且刻蚀削减所形成的硬掩膜形貌不够保型，对后续多晶硅栅的刻蚀会产生不利的影响。
具体地，请结合图1~图4所示的现有的栅极的制作方法。首先，请参考图1，提供半导体衬底10，所述半导体衬底10上依次形成有多晶硅层11、硬掩膜层12、抗反射层13和光刻胶层14。然后，请参考图2，以所述抗反射层13和光刻胶层14为掩膜，对所述硬掩膜层12进行刻蚀工艺，之后利用含氯的等离子体对所述硬掩膜层12进行削减，目的是使其小到一定特征尺寸(CD,characterized dimension)。接着，请参考图3，去除所述光刻胶层14，然后通过以所述硬掩膜层12为掩膜刻蚀多晶硅层12，形成多晶硅栅极。最后，参考图4，去除所述硬掩膜层12。
如图2所示，在利用含有氯的等离子体对所述硬掩膜层12进行削减时，由于削减的时间太长会无法精确控制削减后的硬掩膜层12的特征尺寸，因此会影响硬掩膜层12的形貌，最终不利于形成多晶硅栅极的形貌。
发明内容
本发明解决的问题是提供了一种栅极的制作方法，能更加精确地控制硬掩膜层削减时的厚度和形貌，最终能够获得更小的CD的栅极并能够改善栅极的形貌。
为了解决上述问题，本发明提供一种栅极的制作方法，包括：
提供半导体衬底，所述半导体衬底上形成有多晶硅层、硬掩膜层、抗反射层和光刻胶层；
以所述抗刻蚀层和光刻胶层为掩膜，对硬掩膜层进行刻蚀；
采用SiCoNi工艺对刻蚀后的硬掩膜层进行消减，直至消减后的硬掩膜层的特征尺寸达到工艺要求；
以消减后的硬掩膜层为掩膜，刻蚀所述多晶硅层，形成栅极。
可选地，所述光刻胶层的厚度为1000-4000埃。
可选地，所述硬掩膜层的材质为氧化硅、氮化硅或两者的结合。
可选地，所述硬掩膜层的厚度范围为200-4000埃。
可选地，所述多晶硅层的厚度范围为400-1500埃。
与现有技术相比，本发明具有以下优点：
本发明采用SiCoNi工艺对硅和氧化硅\氮化硅的刻蚀选择比高，能更加精确地控制硬掩膜层削减时的厚度和形貌，最终能够获得更小的CD的栅极并且能够改善最终形成的栅极的形貌。
附图说明
图1-图4是现有技术的栅极的制作方法剖面结构示意图；
图5是本发明一个实施例的栅极的制作方法流程示意图；
图6-图9是本发明一个实施例的栅极的制作方法剖面结构示意图。
具体实施方式
为了更好地控制硬掩膜层的厚度和形貌，更加精确地控制硬掩膜层的特征尺寸，形成精确特征尺寸和形貌的栅极，本发明提供一种栅极的制作方法，请参考图5所示的本发明一个实施例的栅极的制作方法流程图，所述方法包括：
步骤S1，提供半导体衬底，所述半导体衬底上形成有多晶硅层、硬掩膜层、抗反射层和光刻胶层；
步骤S2，以所述抗刻蚀层和光刻胶层为掩膜，对硬掩膜层进行刻蚀；
步骤S3，采用SiCoNi工艺对刻蚀后的硬掩膜层进行消减，直至消减后的硬掩膜层的特征尺寸达到工艺要求；
步骤S4，以消减后的硬掩膜层为掩膜，刻蚀所述多晶硅层，形成栅极。
下面结合具体的实施例对本发明的技术方案进行说明。为了更好地说明本发明的技术方案，请参考图6-图9所示的本发明一个实施例的栅极的制作方法剖面结构示意图。
首先，请参考图6，提供半导体衬底100，所述半导体衬底100上形成有多晶硅层110、硬掩膜层120、抗反射层130和光刻胶层140。所述半导体衬底100的材质为硅。所述多晶硅层110的厚度范围为400-1500埃，比如所述多晶硅层110的厚度可以为400埃、800埃、1100埃、1500埃。所述抗反射层130的材质为200-1000埃。所述光刻胶层为193纳米光刻胶，其厚度范围为1000-4000埃。所述硬掩膜层120的材质可以为氧化硅、氮化硅或两者的结合。作为一个实施例，所述硬掩膜层120的材质为氧化硅。所述硬掩膜层120的厚度范围为200-4000埃。
然后，请参考图7，以所述抗刻蚀层130和光刻胶层140为掩膜，对硬掩膜层120进行刻蚀。然后，采用SiCoNi工艺对刻蚀后的硬掩膜层120进行消减，直至消减后的硬掩膜层120的特征尺寸达到工艺要求。SiCoNi作为低强度高精度的化学刻蚀方法，其对硅和氧化硅\氮化硅具有较高的刻蚀选择比，因此能够更加精确的控制刻蚀工艺的精度，有利于控制消减后的硬掩膜层120的形状和尺寸。
接着，请参考图8，在SiCoNi工艺之后，去除硬掩膜层120上方残留的抗刻蚀层130和光刻胶层140，然后，以消减后的硬掩膜层120为掩膜，刻蚀所述多晶硅层110，形成栅极。
最后，请参考图9，去除所述硬掩膜层120。
综上，本发明采用SiCoNi工艺对硅和氧化硅\氮化硅的刻蚀选择比高，能更加精确地控制硬掩膜层削减时的厚度和形貌，最终能够获得更小的CD的栅极并且能够改善最终形成的栅极的形貌。
因此，上述较佳实施例仅为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种栅极的制作方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底上形成有多晶硅层、硬掩膜层、抗反射层和光刻胶层；
以所述抗刻蚀层和光刻胶层为掩膜，对硬掩膜层进行刻蚀；
采用SiCoNi工艺对刻蚀后的硬掩膜层进行消减，直至消减后的硬掩膜层的特征尺寸达到工艺要求；
以消减后的硬掩膜层为掩膜，刻蚀所述多晶硅层，形成栅极。
2.如权利要求1所述的栅极的制作方法，其特征在于，所述光刻胶层的厚度为1000-4000埃。
3.如权利要求1所述的栅极的制作方法，其特征在于，所述硬掩膜层的材质为氧化硅、氮化硅或两者的结合。
4.如权利要求1所述的栅极的制作方法，其特征在于，所述硬掩膜层的厚度范围为200-4000埃。
5.如权利要求1所述的栅极的制作方法，其特征在于，所述多晶硅层的厚度范围为400-1500埃。
CN2012104966089A 2012-11-28 2012-11-28 栅极的制作方法 Pending CN102931069A (zh)

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CN112331610A (zh) * 2020-11-12 2021-02-05 上海华虹宏力半导体制造有限公司 半导体结构的制备方法

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CN112331610B (zh) * 2020-11-12 2023-08-25 上海华虹宏力半导体制造有限公司 半导体结构的制备方法

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