CN102916695B - High-speed preposed dual frequency divider circuit and implementing method thereof - Google Patents
High-speed preposed dual frequency divider circuit and implementing method thereof Download PDFInfo
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- CN102916695B CN102916695B CN201210433677.5A CN201210433677A CN102916695B CN 102916695 B CN102916695 B CN 102916695B CN 201210433677 A CN201210433677 A CN 201210433677A CN 102916695 B CN102916695 B CN 102916695B
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Abstract
The invention discloses a high-speed preposed dual frequency divider circuit and an implementing method thereof. The frequency divider circuit comprises a feedback loop, two stages of sampling circuits and an output end. The implementing method for the frequency divider comprises the following steps: taking a high-speed clock as an input signal; sampling a feedback signal through a first-stage sampling circuit; and sampling and outputting a first-stage sampling result through the second-stage sampling circuit, and feeding the result back to the data input end of the sampling circuit. The high-speed preposed dual frequency divider circuit can be implemented only by adopting four N-channel metal oxide semiconductor (NMOS) tubes and three P-channel metal oxide semiconductor (PMOS) tubes; the structure of the circuit is simplified; and the high-speed preposed dual frequency divider circuit has the characteristics of high speed, low power consumption and low vibration.
Description
Technical field
The present invention relates generally to high-speed frequency divider design field, especially refers to the preposition two-divider circuit structure of a kind of high speed.
Background technology
Growing along with wireless communication technique, the frequency of radio frequency chip work improves constantly.Because automatic frequency control system has high stability, superior tracking performance and good anti-interference, in field of wireless communication, be widely used.As an important module of automatic frequency control system, the preposition two-divider of high speed is mainly realized DCO high frequency output clock is carried out to two divided-frequency, adjusts DCO output waveform simultaneously, produces that frequency is lower, the low-frequency clock of waveform symmetry.
Tradition TSPC two-divider circuit refers to Fig. 1.In Fig. 1, two-divider consists of nine metal-oxide-semiconductors, wherein the grid of NMOS pipe M1 meets frequency divider output OUTBAR, drain electrode connects the drain electrode of PMOS pipe M3, source electrode meets power supply ground GND, the grid of PMOS pipe M3 meets input clock signal CK, source electrode connects the drain electrode of PMOS pipe M5, the grid of PMOS pipe M5 meets frequency divider output OUTBAR, source electrode meets power vd D, the grid of NMOS pipe M2 meets input clock signal CK, drain electrode connects the drain electrode of PMOS pipe M7, source electrode meets power supply ground GND, the grid of PMOS pipe M7 connects the drain electrode of PMOS pipe M3, source electrode connects the drain electrode of PMOS pipe M8, the grid of PMOS pipe M8 meets input clock signal CK, source electrode meets power vd D, the grid of NMOS pipe M4 connects the drain electrode of PMOS pipe M8, source electrode meets power supply ground GND, drain electrode connects the source electrode of NMOS pipe M6, the grid of NMOS pipe M6 meets input clock signal CK, drain electrode meets output OUTBAR, the grid of PMOS pipe M9 connects the drain electrode of PMOS pipe M8, source electrode meets power vd D, drain electrode meets output OUTBAR.
There are two defects in traditional TSPC two-divider: the one, easily produce burr, and while considering OUTBAR=1, when CK is while being low, M8 be height by preliminary filling, and makes M7 conducting; When CK becomes when high, M8 and OUTBAR discharge simultaneously, and M8 drops to the downward trend of OUTBAR when enough low and is reversed, and now just can produce a burr.The 2nd, it is generally merely able to be operated in hundreds of MHz to 1GHz, and being difficult to meet working range is that hundreds of MHz is to the DCO requirement of several GHz.
The design defect existing for traditional TSPC two-divider circuit structure, designer proposes to adopt two-stage sample circuit structure to realize the preposition frequency-halving circuit structure of high speed (shown in Fig. 2).In order to improve the operating rate of two-divider and to avoid the generation of burr, circuit is reduced to seven realizations by nine original metal-oxide-semiconductors.Concrete improvement is as follows: omit original PMOS pipe M7 and NMOS pipe M6, the drain electrode of PMOS pipe M8 is connected with the drain electrode of NMOS pipe M2, and the drain electrode that PMOS manages M9 is connected with the drain electrode of NMOS pipe M4; Metal-oxide-semiconductor M3 changes NMOS into by PMOS pipe and manages; The grid of PMOS pipe M8 changed by originally meeting input clock signal CK the drain electrode that meets PMOS pipe M5 into, and the grid of PMOS pipe M9 is changed into and met input clock signal CK by the drain electrode that originally met PMOS pipe M8.
For the frequency-halving circuit after improving, metal-oxide-semiconductor M1, M2, M3, M4 and M5 realize the sampling of input data one-level, be output as input clock signal CK and input data OUTBAR's or non-value x2, metal-oxide-semiconductor M6 and M7 realize x2 are carried out to high level sampling low level output, thereby have avoided the generation of burr.
Summary of the invention
The problem to be solved in the present invention is: the problem existing for prior art, the invention provides the preposition two-divider circuit structure of a kind of high speed, this divider circuit can improve the inner antijamming capability of frequency divider, has the simple characteristic of low-power consumption, low jitter and circuit structure simultaneously; The present invention also will provide a kind of implementation method of described divider circuit.
For realizing above-mentioned technical problem, the solution that the present invention proposes is: the preposition two-divider circuit of a kind of high speed, it is characterized in that: it comprises a NMOS pipe (M1), the 2nd NMOS pipe (M2), the 3rd NMOS pipe (M4), the 4th NMOS pipe (M6), the one PMOS pipe (M3), the 2nd PMOS pipe (M5), the 3rd PMOS pipe (M7), wherein the grid of a NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of a PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of a PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock (CK), source electrode connects power supply (VDD).
As a further improvement on the present invention, the preposition two-divider circuit of described high speed has adopted feedback control loop and two-stage sample circuit to realize.
In described two-stage sample circuit, first order sample circuit is identical with the sampling clock of second level sample circuit, the sampled data of first order sample circuit is two-divider output, the output of first order sample circuit is as the data input of second level sample circuit, and second level sample circuit is output as the output of two-divider.
In described two-stage sample circuit, first order sample circuit adopts NOR-logic and dynamic inverter to realize, and second level sample circuit adopts dynamic inverter to realize.
The implementation method of described frequency divider comprises the steps: first using high-frequency clock as input signal; Then by first order sample circuit, feedback signal is sampled; Finally by second level sample circuit to the output of sampling of first order sampled result, and feed back to the data input pin of first order sample circuit.
The present invention only adopts four NMOS pipe and three PMOS pipes to realize, and has simplified circuit structure, has the characteristic of high speed, low-power consumption, low jitter.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of traditional TSPC two-divider circuit;
Fig. 2 is the schematic diagram of the preposition two-divider circuit of high speed of the present invention;
Fig. 3 is the schematic diagram one of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 4 is the schematic diagram two of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 5 is the schematic diagram three of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 6 is the schematic diagram four of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 7 is the schematic diagram five of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 8 is the output waveform of the desirable frequency division of the preposition two-divider circuit of high speed of the present invention;
Fig. 9 is the output waveform of the actual frequency division of the preposition two-divider circuit of high speed of the present invention;
In figure, Reference numeral is: CK-high frequency clock signal; VDD-power supply; X1, x2-M signal; *-metal-oxide-semiconductor is operated in cut-off region, and coupled node disconnects; M1, M2, M4, M6-NMOS pipe; M3, M5, M7, M8, M9-PMOS pipe; OUTBAR-output.
Embodiment
Below with reference to the drawings and specific embodiments, the present invention is described in further details.
Refer to Fig. 2, Fig. 2 is the schematic diagram of the preposition two-divider circuit of high speed of the present invention.It comprises a NMOS pipe (M1), the 2nd NMOS pipe (M2), the 3rd NMOS pipe (M4), the 4th NMOS pipe (M6), the one PMOS pipe (M3), the 2nd PMOS pipe (M5), the 3rd PMOS pipe (M7), wherein the grid of a NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of a PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of a PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock (CK), source electrode connects power supply (VDD).
Two-divider circuit shown in Fig. 2, when realizing, first represents high-speed clock signal with single-ended format, then as the clock input signal of two-stage sample circuit.Like this, as long as input clock signal is effective, two-stage sample circuit can work, and wherein first order sample circuit adopts NOR-logic and dynamic inverter to realize.Only have when input data OUTBAR and clock signal C K are low level, first order sample circuit output x2 is just high level, otherwise remains low level always.Second level sample circuit adopts dynamic inverter to realize, and at rising edge clock, x2 node is sampled, and trailing edge output, finally realizes the two divided-frequency to input clock signal CK.
The embodiment mono-of two-divider circuit of the present invention refers to Fig. 3, suppose the state high level of x2 node, when OUTBAR is while being low and when clock CK is low level, x1 node is recharged, M5 operating state is along with the level of x1 node raises gradually and become linear zone from saturation region, finally, in cut-off region, in this process, the state of x2 node does not change.Now M1, M2, M4 end, and are equivalent to the state disconnecting.Therefore, this stage is initial condition.
The embodiment bis-of two-divider circuit of the present invention refers to Fig. 4, and specifically, when clock CK is during from low transition to high level, M4 opens also x2 node is discharged, and M1, M5, M7 end, and are equivalent to off-state, and x1 node and OUTBAR state are constant.Therefore, this stage is output hold mode.
The embodiment tri-of two-divider circuit of the present invention refers to Fig. 5, and when clock CK jumps to low level from high level, M7 opens and OUTBAR node is charged, and M2, M3, M5 and M6 end, and are equivalent to off-state, and x1 state remains unchanged.Therefore, this stage is output transitional states.
The embodiment tetra-of two-divider circuit of the present invention refers to Fig. 6, when clock CK is during from low transition to high level, M2 and M1 open and x1 node are discharged, M5 and M4 are in opening, by regulate Assurance of Size now x2 node be low level, M3, M6 and M7 end, and are equivalent to off-state.Therefore, this stage is output hold mode.
The embodiment five of two-divider circuit of the present invention refers to Fig. 7, when clock CK jumps to low level from high level, M4 is in off-state, make M5 start x2 node to charge, in like manner OUTBAR is low level by high level saltus step, and M1 is off-state by opening saltus step, and M3 opens x1 node is charged, M5 is off-state by opening saltus step, and x2 node is for keeping high level.Therefore, this stage is output hold mode.
The circuit of each figure both can adopt NMOS pipe to realize above, also can adopt PMOS pipe or bipolar device (as NPN transistor or PNP transistor) to realize.Circuit shown in each figure is only example above, CK, OUTBAR, x1, x2 is replaced to caused circuit variation simply and also belong to protection scope of the present invention, and protection scope of the present invention should be as the criterion with claims.
Claims (4)
1. a preposition two-divider circuit that is applied to high speed frequency division field, it is characterized in that: it comprises a NMOS pipe (M1), the 2nd NMOS pipe (M2), the 3rd NMOS pipe (M4), the 4th NMOS pipe (M6), the one PMOS pipe (M3), the 2nd PMOS pipe (M5), the 3rd PMOS pipe (M7), wherein the grid of a NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of a PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of a PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock signal (CK), source electrode connects power supply (VDD).
2. a kind of preposition two-divider circuit that is applied to high speed frequency division field according to claim 1, is characterized in that having adopted feedback control loop and two-stage sample circuit to realize.
3. according to a kind of preposition two-divider circuit that is applied to high speed frequency division field described in claim 1 and 2, it is characterized in that in described two-stage sample circuit, first order sample circuit is identical with the sampling clock of second level sample circuit, the sampled data of first order sample circuit is two-divider output, the output of first order sample circuit is as the data input of second level sample circuit, and second level sample circuit is output as the output of two-divider.
4. according to a kind of preposition two-divider circuit that is applied to high speed frequency division field described in claim 1 and 2, it is characterized in that described first order sample circuit adopts NOR-logic and dynamic inverter to realize, second level sample circuit adopts dynamic inverter to realize.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924553A (en) * | 2010-09-15 | 2010-12-22 | 复旦大学 | Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure |
| CN102291132A (en) * | 2011-06-10 | 2011-12-21 | 华东师范大学 | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit |
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| US6989697B2 (en) * | 2004-01-15 | 2006-01-24 | Organicid, Inc. | Non-quasistatic phase lock loop frequency divider circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101924553A (en) * | 2010-09-15 | 2010-12-22 | 复旦大学 | Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure |
| CN102291132A (en) * | 2011-06-10 | 2011-12-21 | 华东师范大学 | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit |
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