CN102916695A - High-speed preposed dual frequency divider circuit and implementing method thereof - Google Patents
High-speed preposed dual frequency divider circuit and implementing method thereof Download PDFInfo
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- CN102916695A CN102916695A CN2012104336775A CN201210433677A CN102916695A CN 102916695 A CN102916695 A CN 102916695A CN 2012104336775 A CN2012104336775 A CN 2012104336775A CN 201210433677 A CN201210433677 A CN 201210433677A CN 102916695 A CN102916695 A CN 102916695A
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Abstract
The invention discloses a high-speed preposed dual frequency divider circuit and an implementing method thereof. The frequency divider circuit comprises a feedback loop, two stages of sampling circuits and an output end. The implementing method for the frequency divider comprises the following steps: taking a high-speed clock as an input signal; sampling a feedback signal through a first-stage sampling circuit; and sampling and outputting a first-stage sampling result through the second-stage sampling circuit, and feeding the result back to the data input end of the sampling circuit. The high-speed preposed dual frequency divider circuit can be implemented only by adopting four N-channel metal oxide semiconductor (NMOS) tubes and three P-channel metal oxide semiconductor (PMOS) tubes; the structure of the circuit is simplified; and the high-speed preposed dual frequency divider circuit has the characteristics of high speed, low power consumption and low vibration.
Description
Technical field
The present invention relates generally to the high-speed frequency divider design field, especially refers to the preposition two-divider circuit structure of a kind of high speed.
Background technology
Growing along with wireless communication technique, the frequency of radio frequency chip work improves constantly.Because automatic frequency control system has high stability, superior tracking performance and good anti-interference, be widely used in field of wireless communication.As an important module of automatic frequency control system, the preposition two-divider of high speed is mainly realized DCO high frequency output clock is carried out two divided-frequency, adjusts simultaneously the DCO output waveform, produces that frequency is lower, the low-frequency clock of waveform symmetry.
Tradition TSPC two-divider circuit sees also Fig. 1.Two-divider is made of nine metal-oxide-semiconductors among Fig. 1, wherein the grid of NMOS pipe M1 meets frequency divider output OUTBAR, drain electrode connects the drain electrode of PMOS pipe M3, source electrode meets power supply ground GND, the grid of PMOS pipe M3 meets input clock signal CK, source electrode connects the drain electrode of PMOS pipe M5, the grid of PMOS pipe M5 meets frequency divider output OUTBAR, and source electrode meets power vd D, and the grid of NMOS pipe M2 meets input clock signal CK, drain electrode connects the drain electrode of PMOS pipe M7, source electrode meets power supply ground GND, and the grid of PMOS pipe M7 connects the drain electrode of PMOS pipe M3, and source electrode connects the drain electrode of PMOS pipe M8, the grid of PMOS pipe M8 meets input clock signal CK, source electrode meets power vd D, and the grid of NMOS pipe M4 connects the drain electrode of PMOS pipe M8, and source electrode meets power supply ground GND, drain electrode connects the source electrode of NMOS pipe M6, the grid of NMOS pipe M6 meets input clock signal CK, and drain electrode meets output OUTBAR, and the grid of PMOS pipe M9 connects the drain electrode of PMOS pipe M8, source electrode meets power vd D, and drain electrode meets output OUTBAR.
There are two defectives in traditional TSPC two-divider: the one, produce easily burr, when considering OUTBAR=1, when CK when low, M8 be height by preliminary filling, and makes the M7 conducting; When CK becomes when high, M8 and OUTBAR discharge simultaneously, and M8 drops to that the downward trend of OUTBAR is reversed when enough low, just can produce a burr this moment.The 2nd, it generally is merely able to be operated in hundreds of MHz to 1GHz, and being difficult to satisfy working range is that hundreds of MHz is to the DCO requirement of several GHz.
For the design defect that traditional TSPC two-divider circuit structure exists, the designer proposes to adopt two-stage sample circuit structure to realize the preposition frequency-halving circuit structure of high speed (shown in Figure 2).For the operating rate that improves two-divider and the generation of avoiding burr, circuit is reduced to seven realizations by nine original metal-oxide-semiconductors.Concrete improvement is as follows: omit original PMOS pipe M7 and NMOS pipe M6, the drain electrode of PMOS pipe M8 links to each other with the drain electrode of NMOS pipe M2, and the drain electrode that PMOS manages M9 links to each other with the drain electrode of NMOS pipe M4; Metal-oxide-semiconductor M3 changes the NMOS pipe into by the PMOS pipe; The grid of PMOS pipe M8 changed the drain electrode that meets PMOS pipe M5 into by originally meeting input clock signal CK, and the grid of PMOS pipe M9 is changed into by the drain electrode that originally met PMOS pipe M8 and meets input clock signal CK.
For the frequency-halving circuit after improving, metal-oxide-semiconductor M1, M2, M3, M4 and M5 realize the sampling of input data one-level, be output as input clock signal CK and input data OUTBAR's or non-value x2, metal-oxide-semiconductor M6 and M7 realize x2 is carried out high level sampling low level output, thereby have avoided the generation of burr.
Summary of the invention
The problem to be solved in the present invention is: for the problem of prior art existence, the invention provides the preposition two-divider circuit structure of a kind of high speed, this divider circuit can improve the inner antijamming capability of frequency divider, has simultaneously the simple characteristic of low-power consumption, low jitter and circuit structure; The present invention also will provide a kind of implementation method of described divider circuit.
For realizing above-mentioned technical problem, the solution that the present invention proposes is: the preposition two-divider circuit of a kind of high speed, it is characterized in that: it comprises NMOS pipe (M1), the 2nd NMOS manages (M2), the 3rd NMOS manages (M4), the 4th NMOS manages (M6), the one PMOS manages (M3), the 2nd PMOS manages (M5), the 3rd PMOS manages (M7), wherein the grid of NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply ground (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply ground (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply ground (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock (CK), and source electrode connects power supply (VDD).
As a further improvement on the present invention, the preposition two-divider circuit of described high speed has adopted feedback control loop and two-stage sample circuit to realize.
In the described two-stage sample circuit, first order sample circuit is identical with the sampling clock of second level sample circuit, the sampled data of first order sample circuit is two-divider output, the output of first order sample circuit is as the data input of second level sample circuit, and second level sample circuit is output as the output of two-divider.
In the described two-stage sample circuit, first order sample circuit adopts NOR-logic and dynamic inverter to realize, second level sample circuit sampling dynamic inverter is realized.
The implementation method of described frequency divider comprises the steps: at first high-frequency clock as input signal; Then by the first order sample circuit feedback signal is sampled; At last by second level sample circuit to the output of sampling of first order sampled result, and feed back to the data input pin of first order sample circuit.
The present invention only adopts four NMOS pipe and three PMOS pipes to realize, has simplified circuit structure, has the characteristic of high speed, low-power consumption, low jitter.
Description of drawings
Fig. 1 is the schematic diagram of traditional TSPC two-divider circuit;
Fig. 2 is the schematic diagram of the preposition two-divider circuit of high speed of the present invention;
Fig. 3 is the schematic diagram one of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 4 is the schematic diagram two of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 5 is the schematic diagram three of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 6 is the schematic diagram four of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 7 is the schematic diagram five of the preposition two-divider circuit embodiments of high speed of the present invention;
Fig. 8 is the output waveform of the desirable frequency division of the preposition two-divider circuit of high speed of the present invention;
Fig. 9 is the output waveform of the actual frequency division of the preposition two-divider circuit of high speed of the present invention;
Reference numeral is among the figure: the CK-high frequency clock signal; The VDD-power supply; X1, x2-M signal; *-metal-oxide-semiconductor is operated in cut-off region, and coupled node disconnects; M1, M2, M4, M6-NMOS pipe; M3, M5, M7, M8, M9-PMOS pipe; The OUTBAR-output.
Embodiment
Below with reference to the drawings and specific embodiments the present invention is described in further details.
See also Fig. 2, Fig. 2 is the schematic diagram of the preposition two-divider circuit of high speed of the present invention.It comprises NMOS pipe (M1), the 2nd NMOS manages (M2), the 3rd NMOS manages (M4), the 4th NMOS manages (M6), the one PMOS manages (M3), the 2nd PMOS manages (M5), the 3rd PMOS manages (M7), wherein the grid of NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply ground (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply ground (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply ground (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock (CK), and source electrode connects power supply (VDD).
Two-divider circuit shown in Figure 2 at first represents high-speed clock signal when realizing with single-ended format, then as the clock input signal of two-stage sample circuit.Like this, as long as input clock signal is effective, the two-stage sample circuit namely can both be worked, and wherein first order sample circuit adopts NOR-logic and dynamic inverter to realize.Only have when input data OUTBAR and clock signal C K are low level, first order sample circuit output x2 just is high level, otherwise remains low level always.Second level sample circuit then adopts dynamic inverter to realize, at rising edge clock the x2 node is sampled, and trailing edge output realizes the two divided-frequency to input clock signal CK at last.
The embodiment one of two-divider circuit of the present invention sees also Fig. 3, suppose the state high level of x2 node, when OUTBAR when low and clock CK when being low level, the x1 node is recharged, the M5 operating state raises gradually along with the level of x1 node and becomes linear zone by the saturation region, be at last cut-off region, in this process, the state of x2 node does not change.M1, M2, M4 end the state that is equivalent to disconnect at this moment.Therefore, this stage is initial condition.
The embodiment two of two-divider circuit of the present invention sees also Fig. 4, and specifically, as clock CK during from low transition to high level, M4 opens and the x2 node is discharged, and M1, M5, M7 end, and are equivalent to off-state, and x1 node and OUTBAR state are constant.Therefore, this stage is the output hold mode.
The embodiment three of two-divider circuit of the present invention sees also Fig. 5, and when clock CK jumped to low level from high level, M7 opened and the OUTBAR node is charged, and M2, M3, M5 and M6 end, and are equivalent to off-state, and the x1 state remains unchanged.Therefore, this stage is the output transitional states.
The embodiment four of two-divider circuit of the present invention sees also Fig. 6, as clock CK during from low transition to high level, M2 and M1 open and the x1 node are discharged, M5 and M4 are in opening, be low level by regulating Assurance of Size x2 node this moment, M3, M6 and M7 end, and are equivalent to off-state.Therefore, this stage is the output hold mode.
The embodiment five of two-divider circuit of the present invention sees also Fig. 7, when clock CK jumps to low level from high level, M4 is in off-state, so that M5 begins the x2 node is charged, in like manner OUTBAR is level by the high level saltus step, and M1 is off-state by the opening saltus step, and M3 opens the x1 node is charged, M5 is off-state by the opening saltus step, and the x2 node is for keeping high level.Therefore, this stage is the output hold mode.
More than the circuit of each figure both can adopt the NMOS pipe to realize, also can adopt PMOS pipe or bipolar device (such as NPN transistor or PNP transistor) to realize.More than the circuit shown in each figure only be example, CK, OUTBAR, x1, x2 are replaced caused circuit variation simply also belong to protection scope of the present invention, protection scope of the present invention should be as the criterion with claims.
Claims (4)
1. the preposition two-divider circuit of high speed and its implementation, it is characterized in that: it comprises NMOS pipe (M1), the 2nd NMOS manages (M2), the 3rd NMOS manages (M4), the 4th NMOS manages (M6), the one PMOS manages (M3), the 2nd PMOS manages (M5), the 3rd PMOS manages (M7), wherein the grid of NMOS pipe (M1) connects output (OUTBAR), drain electrode connects the source electrode of the 2nd NMOS pipe (M2), source electrode connects power supply ground (GND), the grid of the 2nd NMOS pipe (M2) connects input clock signal (CK), drain electrode connects the drain electrode of PMOS pipe (M3), the source electrode of the one PMOS pipe (M3) connects power supply (VDD), grid connects output (OUTBAR), the grid of the 3rd NMOS pipe (M4) connects input clock signal (CK), drain electrode connects the drain electrode of the 2nd PMOS pipe (M5), source electrode connects power supply ground (GND), the 2nd PMOS pipe (M5) grid connects the drain electrode of PMOS pipe (M3), source electrode connects power supply (VDD), the grid of the 4th NMOS pipe (M6) connects the drain electrode of the 3rd NMOS pipe (M4), drain electrode connects output (OUTBAR), source electrode connects power supply ground (GND), the drain electrode of the 3rd PMOS pipe (M7) connects output (OUTBAR), grid connects input clock signal (CK), and source electrode connects power supply (VDD).
2. the preposition two-divider circuit of high speed according to claim 1 is characterized in that having adopted feedback control loop and two-stage sample circuit to realize.
According to claim 1 with the preposition two-divider circuit of 2 described high speeds, it is characterized in that in the described two-stage sample circuit, first order sample circuit is identical with the sampling clock of second level sample circuit, the sampled data of first order sample circuit is two-divider output, the output of first order sample circuit is as the data input of second level sample circuit, and second level sample circuit is output as the output of two-divider.
According to claim 1 with the preposition two-divider circuit of 2 described high speeds, it is characterized in that described first order sample circuit adopts NOR-logic and dynamic inverter to realize, second level sample circuit sampling dynamic inverter is realized.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017084217A1 (en) * | 2015-11-16 | 2017-05-26 | 东南大学 | E-tspc structure-based low-power-consumption 2/3 frequency divider circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050156641A1 (en) * | 2004-01-15 | 2005-07-21 | Klaus Dimmler | Non-quasistatic phase lock loop frequency divider circuit |
| CN101924553A (en) * | 2010-09-15 | 2010-12-22 | 复旦大学 | Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure |
| CN102291132A (en) * | 2011-06-10 | 2011-12-21 | 华东师范大学 | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050156641A1 (en) * | 2004-01-15 | 2005-07-21 | Klaus Dimmler | Non-quasistatic phase lock loop frequency divider circuit |
| CN101924553A (en) * | 2010-09-15 | 2010-12-22 | 复旦大学 | Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure |
| CN102291132A (en) * | 2011-06-10 | 2011-12-21 | 华东师范大学 | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017084217A1 (en) * | 2015-11-16 | 2017-05-26 | 东南大学 | E-tspc structure-based low-power-consumption 2/3 frequency divider circuit |
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