CN102884626A - 半导体装置和使用该半导体装置的半导体继电器 - Google Patents

半导体装置和使用该半导体装置的半导体继电器 Download PDF

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CN102884626A
CN102884626A CN2011800220557A CN201180022055A CN102884626A CN 102884626 A CN102884626 A CN 102884626A CN 2011800220557 A CN2011800220557 A CN 2011800220557A CN 201180022055 A CN201180022055 A CN 201180022055A CN 102884626 A CN102884626 A CN 102884626A
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CN102884626B (zh
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冈田洋
砂田卓也
大森猛司
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Panasonic Intellectual Property Management Co Ltd
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Matsushita Electric Industrial Co Ltd
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Abstract

在第一导电型碳化硅(SiC)基板(1)内至少具备一个晶体管单元。各个晶体管单元具备：第二导电型的阱区域，其形成在上述SiC基板的第一面上；源区，其形成在上述阱区域内，由第一导电型区域构成；栅电极，其隔着上述栅极绝缘膜而形成；源电极，其形成为与上述源区相接触；以及漏电极，其形成在上述SiC基板(1)的第二面侧，其中，上述半导体装置具备第二导电型区域，该第二导电型区域位于与上述晶体管单元中的最外侧单元的外侧相邻的位置，该第二导电型区域围绕上述阱区域、并且相对于上述栅电极和上述源电极中的任一个都绝缘。

Description

半导体装置和使用该半导体装置的半导体继电器
技术领域
本发明涉及一种半导体装置和使用该半导体装置的半导体继电器，特别是涉及一种使用碳化硅(SiC)等的化合物半导体的半导体装置和使用该半导体装置的半导体继电器。
背景技术
已知如下一种光耦合型半导体继电器：具备基于输入信号发光的发光元件和接收来自发光元件的光信号来产生电动势的受光元件，通过该电动势来使输出用的MOSFET导通或者截止。
半导体继电器的导通电阻小，半导体继电器能够控制微小模拟信号且小型，因此能够应用于各种用途。
半导体继电器包括LED等发光元件、光电转换部以及输出元件，其中，该LED等发光元件响应于输入信号而生成光信号，该光电转换部包括接收光信号来产生电动势的光电二极管阵列和对所产生的电动势进行充放电的充放电电路，该输出元件包括与来自充放电电路的电压相对应地导通或截止的MOSFET。
作为该MOSFET，以SiC为材料的SiC-MOSFET耐压性高且导通电阻小，因此备受关注。
作为这种MOSFET，在设置于SiC基板内的有源区内配置多个晶体管单元而成的功率用晶体管成为主流。但是，在大功率下使用时，由于晶体管单元的周围的电场集中而导致击穿(breakdown)，因此难以实现高耐压化。
因此提出了各种方案，提出了一种通过将第一导电型的杂质导入有源区的周缘部的环状区域来形成浮置环(floating ring)的MOSFET(例如日本专利公开2006-344802号公报)。
如图9所示，在该半导体装置中，在SiC基板101上形成有作为场效应晶体管(FET)而发挥功能的有源区111。而且，在该有源区111的周缘部形成有固定为与源电极108相同的电位的内侧环116。另外，与该内侧环116相隔规定间隔地形成有电浮置状态的浮置环112。并且，在SiC半导体基板101的周缘部设置有作为漏区的固定为与该基板101相同的电位的外侧环113。在该日本专利公开2006-344802号公报的半导体装置中，在有源区111、即构成FET的区域的最外周设置有内侧环116，该内侧环116经由接触区域117与源电极108相连接。而且，通过将内侧环116固定为与源区104相同的电位，并将外侧环113固定为与漏极相同的电位，能够实现有源区111的周围区域的电场分布的均匀化和稳定化。
另外，在该内侧环116的外侧形成有浮置环112，从p型阱103、116延伸出的耗尽层130越过浮置环112而向外侧环113延伸，不会产生急剧的弯曲(130A表示不存在浮置环112的情况下的耗尽层)。由此能够有效地缓和电场集中。
发明内容
然而，在日本专利公开2006-344802号公报的半导体装置中，在有源区111、即构成FET的区域的最外周设置有内侧环116，该内侧环116和源区104的电位相同，因此存在当对漏极与源极之间施加高电压时经由该第一导电型的区域而漏电流增大的问题，需要采取对策。
另外，除了外侧环113以外，还需要形成内侧环116和浮置环112，因此导致元件面积增大。
本发明是鉴于上述实际情况而完成的，其目的在于减少施加高电压时的漏电流。
因此，根据本发明的一个方式，提供一种半导体装置，该半导体装置在第一导电型的碳化硅基板即SiC基板内至少具备一个晶体管单元(transistor cell)，各个晶体管单元具备：第二导电型的阱区域(well region)，其形成在SiC基板的第一面上；源区，其形成在该阱区域内，由第一导电型区域构成；栅电极，其隔着上述栅极绝缘膜而形成；源电极，其形成为与上述源区相接触；以及漏电极，其形成在SiC基板的第二面侧，该半导体装置具备第二导电型区域，该第二导电型区域位于与该晶体管单元中的最外侧单元的外侧相邻的位置，该第二导电型区域包围该阱区域并且相对于栅电极和源电极中的任一个都绝缘。
期望该第二导电型区域构成环区域。
期望构成为：该SiC基板在第一导电型的高浓度区域表面形成浓度更低的第一导电型的外延生长层，上述第二导电型区域和与该第二导电型区域最接近的晶体管单元之间的间隔小于阱区域下的外延生长层的厚度。
期望构成为：形成为使上述第二导电型区域和与该第二导电型区域最接近的晶体管单元之间的间隔小于相邻的晶体管单元之间的间隔。
根据本发明的其它方式，提供一种半导体继电器，其具备：发光元件，其根据输入信号来发光；光电二极管阵列，其接收该光来发电；充放电电路，其与光电二极管阵列并联连接；以及输出FET，其将栅极和源极与光电二极管阵列的两端相连接，其中，具备上述SiC FET作为该输出FET。
发明的效果
根据本发明，使与SiC-FET的源电极等电位的晶体管单元周围的第二导电型区域为电浮置状态(floating)，由此不对第二导电型区域与基板之间的pn结施加漏极与源极间的电压。因而，能够减少实质性的pn结面积，从而能够减少pn结的漏电量。另外，只要追加浮置区域即可，因此能够减少占用面积，能够实现元件的小型化。
附图说明
基于与如下的附图一起提供的后述的优选实施方式的说明能够明确本发明的目的和特征。
图1是表示实施方式1的半导体继电器的等效电路图。
图2是表示构成实施方式1的半导体继电器的输出元件的晶体管的单元配置的图，图2的(a)是芯片的上表面说明图，图2的(b)是主要部分的放大截面说明图。
图3是表示SiC-MOSFET的制造工序的图。
图4的(a)是表示实施方式1的将硅二极管进行外部连接的输出元件芯片的连接例的说明图，图4的(b)是图4的(a)的等效电路图。
图5是表示实施方式1的半导体继电器的局部剖切立体图。
图6是表示实施方式1的半导体继电器的截面概要图。
图7是表示在实施方式1的半导体继电器中使用的输出元件的变形例的等效电路图。
图8是表示在实施方式2的半导体继电器中使用的输出元件的等效电路图。
图9是表示现有例的半导体装置的截面图。
具体实施方式
下面，参照附图详细地说明本发明的实施方式。
(实施方式1)
图1是实施方式1的半导体继电器的等效电路图，图2是表示构成该半导体继电器的输出元件的晶体管的单元配置的图，图2的(a)是该晶体管芯片的上表面说明图，图2的(b)是主要部分的放大截面说明图。本实施方式1的半导体继电器使用了化合物半导体装置、即SiC-MOSFET 31a、31b来作为构成其输出元件30的晶体管，在第一导电型、例如n型SiC基板1的第一面上形成多个晶体管单元TC来构成输出元件30。本发明的实施方式1的输出元件的特征在于，具备作为第二导电型区域的p型耐压保持区域3p，该p型耐压保持区域3p位于构成晶体管单元TC中的最外侧单元TC的p型阱区域3s的外侧相邻的位置，该p型耐压保持区域3p包围该p型阱区域3和3s、并且相对于栅电极7和源电极5中的任一个都绝缘。如图2的(a)所示，该p型耐压保持区域3p以包围晶体管单元TC的方式形成为环状。
即，如图2的(a)和图2的(b)所示，本发明的实施方式1的输出元件30是在构成晶体管单元TC的p型阱区域3中的最外层的p型阱区域3s的外侧形成相同深度的p型耐压保持区域3p而构成的。而且，形成为：作为第二导电型区域的p型耐压保持区域3p与最外侧(即，与p型耐压保持区域3p最接近的)晶体管单元TC(即，最外侧晶体管单元TC的p型阱区域3s)之间的间隔d小于这些p型阱区域3下的外延生长层的厚度tepi(d<tepi)。另外，形成为：作为第二导电型区域的p型耐压保持区域3p与构成最外侧晶体管单元TC的p型阱区域3s之间的间隔d小于相邻的晶体管单元TC之间的间隔(即，相邻的晶体管单元TC的阱区域3或者3s之间的间隔)dTr(d<dTr)。在该晶体管单元TC的收缩部(括れ部)50的一侧形成栅极垫，在另一侧形成源极垫。另外，在作为背面侧的第二面上形成漏电极9。
除此以外，与惯例的晶体管单元同样地形成本发明的实施方式1的晶体管单元TC，通过形成n型外延生长层2和p型阱区域3来形成该晶体管单元TC，其中，该n型外延生长层2通过外延生长而形成在期望浓度的n型SiC基板1的表面，该p型阱区域3形成在该n型外延生长层2内。而且，p型耐压保持区域3p和p型阱区域3通过同一工序形成，深度也相同。
每个晶体管单元TC包括：第二导电型的阱区域3、3s，它们形成在上述SiC基板1的第一面上；源区4，其由形成在上述阱区域3、3s内的第一导电型区域构成；栅电极7，其隔着上述栅极绝缘膜6而形成；源电极5，其形成为与上述源区4接触；以及漏电极9，其形成在上述SiC基板1的第二面侧。
另外，在该p型阱区域3内形成有作为n型区域的源区4，来作为第一导电型的杂质区域。而且，在其上层隔着栅极绝缘膜6形成有栅电极7。该栅电极7形成为横跨构成相邻的晶体管单元的p型阱区域3或者3s之间，对p型阱区域3或者3s的表面的沟道的形成进行控制。并且，在其上层隔着作为绝缘膜8的例如氧化硅膜形成有源电极5。该绝缘膜8不仅覆盖栅电极7，还覆盖了除与源区4的接触区域和芯片周缘部以外的整个基板表面。另外，在n型SiC基板1的背面侧、即第二面侧形成有漏电极9。P是覆盖基板表面的由聚酰亚胺膜等构成的保护膜。
根据该结构，不对与栅电极7和源电极5绝缘的晶体管单元TC周围的P型耐压保持区域3p与基板之间的pn结施加漏极与源极间的电压，由此能够减少pn结的漏电流量，从而能够实现漏电流的减少。
另外，只要在构成晶体管单元TC的p型阱区域3中的最外层的p型阱区域3s的外侧形成相同深度的p型耐压保持区域3p即可，因此除了变更掩模图案之外不需要任何附加工序。
而且，p型耐压保持区域3p与最外层的p型阱区域3s之间的间隔d小于这些p型阱区域3下的外延生长层的厚度tepi(d<tepi)，因此能够在耗尽层到达高浓度的n型SiC基板1之前用耗尽层覆盖p型耐压保持区域3p。因而，能够使耐压尽可能接近使得耗尽层到达高浓度的基板的耐压值。另外，p型耐压保持区域3p与最外层的p型阱区域3s之间的间隔d小于相邻的晶体管单元TC之间的间隔dTr(d<dTr)，因此能够抑制由于离晶体管单元的距离变大而引起的耐压下降。
此外，在SiC的情况下，相对于耗尽层的弯曲(即，电场集中)有高耐受性，耐压不易下降，因此能够使p型耐压保持区域3p浮置。
并且，从布局方面来看，在p型耐压保持区域3p中也不需要形成接触，只要存在即可，因此不需要用于图案形成的余量，其结果，能够实现芯片面积的减小或者有效元件表面积的增大。
以如下方式制造该SiCMOSFET。
首先，通过外延生长来在n+型SiC晶圆(基板1)表面形成比SiC晶圆的n浓度低的期望浓度的n型外延生长层2。然后，隔着掩模图案R利用p型杂质离子进行离子注入，在惰性环境中通过1600°C左右的激活退火工序形成p型耐压保持区域3p和晶体管单元的p型阱区域3、3s(图3的(a))。
接着，去除该掩模图案R，再次形成掩模图案，隔着该掩模图案利用n型杂质离子进行离子注入，在惰性环境中通过1600°C左右的激活退火工序形成作为源区4的n型区域。而且之后，在通过热氧化等形成作为栅极绝缘膜6的氧化硅膜等之后，通过CVD法形成多晶硅层，利用通过光刻法(photolithographic method)形成的掩模图案进行图案化来形成栅电极7(图3的(b))。
然后，在其上层通过CVD法形成氧化硅膜8，进一步使用掩模图案进行图案化来形成接触窗(图3的(c))。
之后，通过溅射法等在表面和背面形成铝、镍、银等的金属层，形成源电极5和漏电极9(图3的(d))。
然后，最后形成聚酰亚胺膜等来作为保护膜P，形成图2所示的SiCMOSFET。
接着说明将该SiC-MOSFET用作输出元件的半导体继电器。
通过布线L以外部连接来将如图4中示出的输出元件的元件结构那样作为输出元件30(30a、30b)的如下电路反向串联连接：该电路是将旁路用的硅(Si)二极管40a和40b的阴极K分别与SiC-MOSFET 31a和31b的漏极D相连接、并且将硅二极管40a和40b的阳极A与SiCMOSFET的源极S相连接而成。图4的(a)是表示实施方式1的将硅二极管进行外部连接的输出元件的连接例的说明图，图4的(b)是图4的(a)的等效电路图，在此仅示出了SiCMOSFET 31a和硅二极管40a的一个单元，但同样的单元如图1所示那样配设有两个。此外，在此，在构成输出元件30a和30b的SiC-MOSFET 31a和31b上分别并联连接有内置的SiC体二极管(body diode)32a和32b。
即，如图1所示，本实施方式的半导体继电器包括发光元件10、光电转换装置20以及输出元件30(30a、30b)。发光元件10包括具备第一输入端子T 1和第二输入端子T2的LED。而且，光电转换装置20包括与发光元件10的发光相应地产生电动势并输出电压的光电二极管阵列21和对光电二极管阵列21的输出电压进行充放电的充放电电路22。而且，通过对栅极施加光电二极管阵列21的输出电压，输出元件30被导通、截止。在此，输出元件30包括漏极与源极之间被导通、截止的两个作为输出元件的SiC-MO SFET 31a、31b，在SiC-MOSFET 31a、31b上分别并联连接有由Si二极管40a、40b构成的保护元件。在此，SiC体二极管32a、32b是内置二极管，是如图4所示那样形成在p型阱区域3与外延生长层2之间的pn结二极管。
两个SiC-MOSFET 31a、31b各自的栅极G与光电二极管阵列21的阳极端子A相连接，各自的源极在以反向串联的方式互相连接之后与光电二极管阵列21的阴极端子相连接。另外，SiC-MOSFET 31a的漏极与第一输出端子T3相连接，SiC-MOSFET 31b的漏极与第二输出端子T4相连接。
另外，图5、图6表示半导体继电器的局部剖切立体图和截面概要图的一例。该半导体继电器构成为：在引线框架15上安装有发光元件(LED)10、光电转换装置20以及输出元件30，其中，该发光元件(LED)10根据输入信号点亮或熄灭，该光电转换装置20包括接收来自该发光元件10的光信号并通过光电转换产生电动势的光电二极管阵列21和对由该光电二极管阵列21产生的电力进行充放电的充放电电路22，该输出元件30接受来自该光电转换装置20的输出电压的供给，包括SiC-MOSFET 31a、31b(以及内置的SiC体二极管32a、32b)，当SiC-MOSFET的栅极电压达到设定电压值时，SiC-MOSFET变为导通状态，使负载启动。在此，T1、Τ2是输入端子，T3、Τ4是输出端子，100是树脂封装。如图6所示，将发光元件10与光电转换装置20相对置地进行安装，以使来自发光元件10的光到达光电二极管阵列21。
接着，对这样构成的实施方式1所涉及的半导体继电器的动作进行说明。
发光元件10通过被输入来自第一输入端子Τ1和第二输入端子Τ2的输入信号来发光并生成光信号。光电二极管阵列21通过接收发光元件10的光信号来在其两端产生电动势并输出电压。
充放电电路22将光电二极管阵列21的输出电压进行充放电并施加到构成输出元件30(30a、30b)的SiC-MOSFET 31a、31b的栅极。而且，当对SiC-MOSFET 31a、31b的栅极施加的光电二极管阵列21的输出电压大于阈值电压Vth时，SiC-MOSFET31a、31b的漏极与源极之间被导通，第一输出端子T3与第二输出端子Τ4之间导通，从而继电器被闭合。
另一方面，在第一输入端子Τ1和第二输入端子Τ2中，当输入信号断开时，来自充放电电路22的输出电压消失，构成输出元件的SiC-MOSFET 31、31b的漏极与源极之间被截止，第一输出端子T3与第二输出端子Τ4之间被切断，从而继电器断开。
使用于实施方式1的半导体继电器的、构成输出元件30的半导体元件如上所述那样漏电流小，能够进一步实现小型化。因此，即使在将保护元件外部连接的情况下也能够保持为比较小型。在此，如图1、图4的(a)和(b)以及图5所示，输出元件30将SiC-MOSFET进行反向串联连接，经由引线框架15的各引线端子将硅二极管40a、40b的芯片外部连接到各SiC-MOSFET，因此在能够抑制在封装100内部SiC-MOSFET内的寄生元件(SiC体二极管32a、32b)进行动作的同时连接旁路元件。(作为内置的SiC体二极管32的SiC-pn二极管的正向压降Vf(大约3V)大于硅二极管的Vf(大约0.6V)，因此当从源极侧(+)对漏极侧(-)施加电压时，在没有硅二极管的情况下流向SiC-pn二极管32a、32b的电流通过硅二极管40a、40b被旁路。)其结果，能够防止由于对S iC体pn二极管通电而引起的SiC晶圆的晶体缺陷扩大，能够防止SiC-MOSFET的导通电阻增加。通过这样，即使在重复使用时也能够维持继电器输出触点的可靠性。
此外，考虑如下情况：SiC体二极管32的动作在对输出元件30施加的电压瞬间成为其耐压以上时，例如导致SiCMOSFET31a的耐压以上的施加电压量还被施加到SiC-MOSFET 31b。在此，如果没有连接硅二极管40b，则导致对SiC-MOSFET 31b的源极与漏极之间、即SiC体二极管32b的正向施加电压。
并且，除此之外，该半导体继电器具有如下特征。
1)使用外部连接的硅二极管作为保护元件，因此容易以简单的结构制造可靠性高的半导体装置，由于利用光耦合，因此能够将输入输出之间完全电分离。
2)使用功率用的SiC-MOSFET作为负载侧的开关，因此不会产生抖动(chattering)、机械噪声。在导通状态下线性度高，因此能够控制模拟信号。
3)输出电路是将FET进行反向串联连接而成的，因此能够适于交流和直流两用。
此外，在上述实施方式中，作为输出元件，使用了将两个SiC-MOSFET 31a、31b进行反向连接而得到的元件，但也可以如图7所示那样使用包括一个SiC-MOSFET 31的输出元件30，并将该输出元件30与一个Si二极管40并联连接。
(实施方式2)
作为本实施方式2的半导体装置，也可以不附加构成保护元件40(参照图1)的旁路用的半导体元件，而如图8所示那样仅由SiC-MOSFET 30a、30b来构成，这是理所当然的。除了不连接旁路用的半导体元件地形成这一点以外，与实施方式1中说明的半导体装置相同，因此在此省略说明。
此外，在实施方式1和实施方式2中说明了SiCMOSFET，但并不限定于MOSFET，也能够适用于肖特基栅(schottky gate)FET等使用了SiC系的化合物半导体的FET。
以上，说明了本发明的优选的实施方式，但本发明并不限于这些特定的实施方式，在不脱离权利要求书的范围的情况下能够进行各种变更和变形，这些变更和变形也属于本发明的范围内。

Claims (5)

1.一种半导体装置，在第一导电型的碳化硅基板即SiC基板内至少具备一个晶体管单元，
上述晶体管单元各自具备：第二导电型的阱区域，其形成在上述SiC基板的第一面上；源区，其形成在上述阱区域内，由第一导电型区域构成；栅电极，其隔着上述栅极绝缘膜而形成；源电极，其形成为与上述源区相接触；以及漏电极，其形成在上述SiC基板的第二面侧，
该半导体装置具备第二导电型区域，该第二导电型区域位于与上述晶体管单元中的最外侧单元的外侧相邻的位置，该第二导电型区域包围该阱区域并且相对于上述栅电极和上述源电极中的任一个都绝缘。
2.根据权利要求1所述的半导体装置，其特征在于，
上述第二导电型区域构成环区域。
3.根据权利要求1或2所述的半导体装置，其特征在于，
上述SiC基板在第一导电型的高浓度区域表面形成浓度更低的第一导电型的外延生长层，
上述第二导电型区域和与该第二导电型区域最接近的晶体管单元之间的间隔小于上述阱区域下的外延生长层的厚度。
4.根据权利要求1或2所述的半导体装置，其特征在于，
形成为使上述第二导电型区域和与该第二导电型区域最接近的晶体管单元之间的间隔小于相邻的上述晶体管单元之间的间隔。
5.一种半导体继电器，具备：
发光元件，其根据输入信号来发光；
光电二极管阵列，其接收该光来发电；
充放电电路，其与上述光电二极管阵列并联连接；以及
作为输出FET的根据权利要求1至4中的任一项所述的SiCFET，其将上述栅极和源极与光电二极管阵列的两端相连接。
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