CN102881597A - Method for manufacturing transistor - Google Patents
Method for manufacturing transistor Download PDFInfo
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- CN102881597A CN102881597A CN2012103889009A CN201210388900A CN102881597A CN 102881597 A CN102881597 A CN 102881597A CN 2012103889009 A CN2012103889009 A CN 2012103889009A CN 201210388900 A CN201210388900 A CN 201210388900A CN 102881597 A CN102881597 A CN 102881597A
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Abstract
The invention provides a method for manufacturing a transistor. The method comprises the following steps of: providing a semiconductor substrate, wherein a polycrystalline silicon layer, a hard mask layer, an anti-reflection layer and a graphical photoresist layer are formed on the semiconductor substrate; etching the anti-reflection layer by using the photoresist layer as a mask to form a graphical anti-reflection layer; etching the hard mask layer by using the graphical anti-reflection layer as a mask to form a graphical hard mask layer; removing the anti-reflection layer; and etching the polycrystalline silicon layer by using the graphical hard mask layer as a mask to form a gate. By the method, the shape of the formed gate is improved, and the performance of a device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to transistorized manufacture method.
Background technology
In semiconductor fabrication process, the manufacturing of grid is very crucial step, and is larger on the performance of devices impact of final formation.For the manufacturing of grid, the control of grid etch pattern is extremely important, usually requires the sidewall vertical smooth of grid, and not distortion.
Along with constantly dwindling of the critical size of semiconductor device, the size of transistorized grid is constantly dwindled.The photoresist layer that utilizes individual layer has been subject to the restriction of the aspects such as the thickness, reflectivity control, etch resistance of photoresist layer as etching barrier layer, the single-layer lithography glue-line can not satisfy integrated requirement as the barrier layer, therefore, utilize the different material of multilayer jointly as the barrier layer of etching grid.
Please refer to the transistorized manufacture method cross-sectional view of the prior art of Fig. 1-shown in Figure 2.Please refer to Fig. 1, be formed with successively grid oxic horizon 11, polysilicon silicon layer 12, hard mask layer 13, anti-reflecting layer 14 and patterned photoresist layer 15 on the Semiconductor substrate 10.The material of described hard mask layer 13 is amorphous carbon, and the material of described anti-reflecting layer 14 is antireflecting inorganic layer, such as being silica.Described photoresist layer 15 has defined the shape of the grid of final formation.Described photoresist layer 15, anti-reflecting layer 14, hard mask layer 13 common barrier layers as etch polysilicon layer 12.Prior art is carried out etching usually take described photoresist layer 15 as mask to described anti-reflecting layer 14, forms patterned anti-reflecting layer 14.
Then please refer to Fig. 2, remove photoresist layer, take described patterned anti-reflecting layer 14 as mask, the described mask layer 13 of firmly covering is carried out etching, form patterned hard mask layer 13.Through described etching technics of answering mask layer 13, described patterned anti-reflecting layer 14 still has part to residue on the hard mask layer 13.Then take described patterned anti-reflecting layer 14, residual hard mask layer 13 as mask, described polysilicon layer 12 is carried out etching technics, form grid 16.
Find that in practice the pattern distortion of the transistorized grid 16 that prior art forms has affected the control of technique and the performance of final device.
Summary of the invention
The problem that the present invention solves provides a kind of transistorized manufacture method, has improved the pattern of the grid that forms, and has improved performance of devices.
In order to address the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided, is formed with polysilicon layer, hard mask layer, anti-reflecting layer and patterned photoresist layer on the described Semiconductor substrate;
Take described photoresist layer as mask, described anti-reflecting layer is carried out etching technics, form patterned anti-reflecting layer;
Take described patterned anti-reflecting layer as mask, described hard mask layer is carried out etching technics, form patterned hard mask layer;
Remove described anti-reflecting layer;
Take described patterned hard mask layer as mask, described polysilicon layer is carried out etching technics, form grid.
Alternatively, the etching of described anti-reflecting layer adopts the plasma that contains carbon ion and fluorine ion to carry out.
Alternatively, the etching utilization of the described anti-reflecting layer plasma that contains CF4 carries out.
Utilize wet-etching technology to remove in, described anti-reflecting layer alternatively.
Alternatively, described anti-reflecting layer utilization contains the solution removal of hydrofluoric acid.
Alternatively, the mass ratio range of water and hydrofluoric acid is 150:1-250:1 in the described solution that contains hydrofluoric acid.
Alternatively, the etching technics of described polysilicon layer is plasma etch process.
Alternatively, the material of described hard mask layer is amorphous carbon.
Compared with prior art, the present invention has the following advantages:
The present invention is before the etch polysilicon layer, the anti-reflecting layer that will be positioned on the hard mask layer is removed, when thereby the etch polysilicon layer is made grid only with the hard mask layer on the polysilicon layer as mask, avoided two kinds of mask layers as the mask of the etch polysilicon layer problem to the sidewall that the brings distortion of grid, improve the pattern of the grid that forms, improved transistor and performance of devices.
Description of drawings
Fig. 1-Fig. 2 is the transistorized manufacture method cross-sectional view of prior art;
Fig. 3 is the transistorized manufacture method schematic flow sheet of one embodiment of the invention;
Fig. 4-Fig. 5 is the transistorized manufacture method cross-sectional view of one embodiment of the invention.
Embodiment
The pattern distortion of the transistorized grid that prior art is made.Please in conjunction with Fig. 1 and Fig. 2, this is that part anti-reflecting layer 14 still remains on the hard mask layer 13 because during etch polysilicon layer 12.At the initial period of etch polysilicon layer 12, anti-reflecting layer 14 is as mask, and at the etch polysilicon layer after 12 a period of time, and hard mask layer 13 is just as the mask of etch polysilicon layer 12.Therefore, form in the process of grid 16 at etch polysilicon layer 12, have anti-reflecting layer 14 and hard mask layer 13 such two mask layers.The material of anti-reflecting layer 14 is silica, and the material of hard mask layer 13 is amorphous carbon, and the material of the polymer protective layer that the material of these two kinds of mask layers produces in etching process is different.Therefore less at the polymer that utilizes anti-reflecting layer 14 etchings to form, thus so that the pattern of the upper and lower of the final grid 16 that forms is different, produced the problem of the pattern distortion of grid 16, finally affect the control of transistorized technique and device performance.
In order to address the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Step S1 provides Semiconductor substrate, is formed with polysilicon layer, hard mask layer, anti-reflecting layer and patterned photoresist layer on the described Semiconductor substrate;
Step S2 take described photoresist layer as mask, carries out etching technics to described anti-reflecting layer, forms patterned anti-reflecting layer;
Step S3 take described patterned anti-reflecting layer as mask, carries out etching technics to described hard mask layer, forms patterned hard mask layer;
Step S4 removes described anti-reflecting layer;
Step S5 take described patterned hard mask layer as mask, carries out etching technics to described polysilicon layer, forms grid.
Below in conjunction with specific embodiment technical scheme of the present invention is described in detail.For technical scheme of the present invention is described better, please refer to the transistorized manufacture method schematic flow sheet of one embodiment of the present of invention of Fig. 4-shown in Figure 5.
At first, please refer to Fig. 4, Semiconductor substrate 100 is provided, be formed with gate oxide 110, polysilicon layer 120, hard mask layer 130, anti-reflecting layer 140 and patterned lithography layer 150 on the described Semiconductor substrate 100.Described photoresist layer 150 has defined the shape and size of the grid of final formation.The material of described anti-reflecting layer 140 is silica.The material of described hard mask layer 130 is amorphous carbon.
Then, continue with reference to figure 4, take described photoresist 150 as mask, described anti-reflecting layer 140 is carried out etching technics, form patterned anti-reflecting layer 140.As an embodiment, described anti-reflecting layer 140 using plasma etching technics carry out.In the present embodiment, described anti-reflecting layer 140 adopts the plasma that contains carbon ion and fluorine ion to carry out etching, can adopt the plasma that contains CF4 to carry out such as described anti-reflecting layer 140.
Then, continue with reference to figure 4, take described patterned anti-reflecting layer 140 as mask, described hard mask layer 130 is carried out etching technics, form patterned hard mask layer 130.
Then, please refer to Fig. 5 and in conjunction with Fig. 4, remove described anti-reflecting layer 140.Described anti-reflecting layer 140 utilizes wet-etching technology to remove.In the present embodiment, described anti-reflecting layer 140 utilizes the solution removal that contains hydrofluoric acid.As selectable embodiment, the mass ratio range of water and hydrofluoric acid is 150:1-250:1 in the described solution that contains hydrofluoric acid.As preferred embodiment, the mass ratio range of water and hydrofluoric acid is 200:1 in the described solution that contains hydrofluoric acid.Carrying out to carry out cleaning after wet-etching technology removes anti-reflecting layer 140, removing particle contamination that described wet-etching technology forms at hard mask layer 130 etc.
Then, please refer to Fig. 5 and in conjunction with Fig. 4, with described patterned hard mask, 130 is mask, and described polysilicon layer 120 is carried out etching technics, form grid 160.As an embodiment, the etching technics of described polysilicon layer is plasma etch process.
To sum up, the present invention is before the etch polysilicon layer, the anti-reflecting layer that will be positioned on the hard mask layer is removed, when thereby the etch polysilicon layer is made grid only with the hard mask layer on the polysilicon layer as mask, avoided two kinds of mask layers as the mask of the etch polysilicon layer problem to the sidewall that the brings distortion of grid, improve the pattern of grid, improved transistor and performance of devices.
Therefore, above-mentioned preferred embodiment only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with technique can understand content of the present invention and according to this enforcement, can not limit protection scope of the present invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (8)
1. a transistorized manufacture method is characterized in that, comprising:
Semiconductor substrate is provided, is formed with polysilicon layer, hard mask layer, anti-reflecting layer and patterned photoresist layer on the described Semiconductor substrate;
Take described photoresist layer as mask, described anti-reflecting layer is carried out etching technics, form patterned anti-reflecting layer;
Take described patterned anti-reflecting layer as mask, described hard mask layer is carried out etching technics, form patterned hard mask layer;
Remove described anti-reflecting layer;
Take described patterned hard mask layer as mask, described polysilicon layer is carried out etching technics, form grid.
2. transistorized manufacture method as claimed in claim 1 is characterized in that, the etching of described anti-reflecting layer adopts the plasma that contains carbon ion and fluorine ion to carry out.
3. transistorized manufacture method as claimed in claim 2 is characterized in that, the plasma that the etching utilization of described anti-reflecting layer contains CF4 carries out.
4. transistorized manufacture method as claimed in claim 1 is characterized in that, described anti-reflecting layer utilizes wet-etching technology to remove.
5. transistorized manufacture method as claimed in claim 1 is characterized in that, described anti-reflecting layer utilization contains the solution removal of hydrofluoric acid.
6. transistorized manufacture method as claimed in claim 5 is characterized in that, the mass ratio range of water and hydrofluoric acid is 150:1-250:1 in the described solution that contains hydrofluoric acid.
7. transistorized manufacture method as claimed in claim 1 is characterized in that, the etching technics of described polysilicon layer is plasma etch process.
8. transistorized manufacture method as claimed in claim 1 is characterized in that, the material of described hard mask layer is amorphous carbon.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012103889009A CN102881597A (en) | 2012-10-12 | 2012-10-12 | Method for manufacturing transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103889009A CN102881597A (en) | 2012-10-12 | 2012-10-12 | Method for manufacturing transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576392A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing finned field-effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
| US20050130354A1 (en) * | 2003-12-13 | 2005-06-16 | Jin-Young Kim | Metal oxide semiconductor (MOS) transistor including a planarized material layer and method of fabricating the same |
| CN101154572A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Fabricating method for semiconductor device |
| CN102867742A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Plasma etching method for eliminating morphologic deformation |
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2012
- 2012-10-12 CN CN2012103889009A patent/CN102881597A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
| US20050130354A1 (en) * | 2003-12-13 | 2005-06-16 | Jin-Young Kim | Metal oxide semiconductor (MOS) transistor including a planarized material layer and method of fabricating the same |
| CN101154572A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Fabricating method for semiconductor device |
| CN102867742A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Plasma etching method for eliminating morphologic deformation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576392A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing finned field-effect transistor |
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Application publication date: 20130116 |