CN103515290A - Double-shallow-trench isolation process - Google Patents
Double-shallow-trench isolation process Download PDFInfo
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- CN103515290A CN103515290A CN201310491854.XA CN201310491854A CN103515290A CN 103515290 A CN103515290 A CN 103515290A CN 201310491854 A CN201310491854 A CN 201310491854A CN 103515290 A CN103515290 A CN 103515290A
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- Prior art keywords
- shallow trench
- compared
- photoresist
- etching
- barrier layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
The invention discloses a double-shallow-trench isolation process which comprises the following steps of providing a substrate and carrying out photoetching gluing and development on the substrate; etching the substrate to form two first shallow trenches (I and II) by using silicon nitride or amorphous carbon as a barrier layer; filling photoresist in the region where the first shallow trench I is positioned and developing the region where the first shallow trench II is positioned; further etching the first shallow trench II by using photoresist as a barrier layer so as to form a second deep trench; ashing and removing the photoresist and carrying out chemical cleaning. According to the invention, firstly, the high-quality mask (the silicon nitride or the amorphous carbon) is utilized to etch the first shallow trenches and then the second deep trench is etched by using the photoresist as the barrier layer, so that the double-shallow-trench process can be implemented; the photoresist is used as the barrier layer, and thus not only is limitation to the light resistance and the thickness of the photoresist reduced, but also the problem of selection ratio of etching to photoresistance is solved, so that the process difficulty is lowered and the production cost is reduced.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly a kind of dual shallow trench isolation technique.
Background technology
Below deep-submicron, in the technology of (≤65nm), the photosensitive area of cmos image sensor (CIS) and the memory cell of peripheral logic district and memory device and peripheral logic district often require to form different shallow trench isolations from the degree of depth.While all requiring smaller active area live width for Zhe Liangkuai region, with regard to two high-grade masks of needs (high grade mask), need carry out respectively exposure imaging through immersion lithography equipment twice, so just increased manufacturing cost.
Except expensive problem, also there is a problem in current technological process: be exactly when doing second compared with shallow trench etching, need the higher selection to photoresistance to compare.Current way is; after first forms compared with deep trench; with bottom anti-reflection layer (BARC; English full name: Bottom Anti-reflective Coating) fill therebetween; through immersion lithography, develop and do second compared with shallow trench etching; in this etching process, need to retain the groove that photoresistance has formed with protection always, this just needs higher hard mask and silicon substrate for the selection ratio of photoresistance.But along with crucial live width is more and more less, the thickness of photoresistance is just more and more thinner, thereby limited greatly the state space of etching.
Summary of the invention
The invention provides a kind of technique of dual shallow trench isolation cheaply, to solve the problems of the technologies described above.
For solving the problems of the technologies described above, the invention provides a kind of dual shallow trench isolation technique, comprising: substrate is provided, described substrate is carried out to photoetching gluing and development; With silicon nitride or non-type Tan Wei barrier layer, described substrate etching is formed to two firsts compared with shallow trench; One of them first is carried out to photoresist filling compared with shallow trench region, and another first is developed compared with shallow trench region; The photoresist of take carries out further etching to another first compared with shallow trench as barrier layer, forms second compared with deep trench; Photoresist ashing is removed and carried out chemical cleaning.
As preferably, take silicon nitride or non-type carbon as hard mask forms two firsts compared with in shallow trench step to described substrate etching, adopt HBr, O
2or HBr, O
2and SF
6as etching gas.
As preferably, adopt and contain HBr and O
2another first of the further etching of mist compared with shallow trench, form second compared with deep trench.
As preferably, take silicon nitride as barrier layer to described substrate etching form two firsts compared with shallow trench after, carry out that original position photoresist is removed and acid tank cleaning.
As preferably, with non-type Tan Wei barrier layer to described substrate etching form two firsts compared with shallow trench after, adopt photoresist ashing equipment to remove described non-type carbon.
As preferably, adopt KrF lithographic equipment to develop compared with shallow trench region to described another first.
As preferably, the thickness of described photoresist is greater than 1um.
Compared with prior art, dual shallow trench isolation technique of the present invention, comprising: substrate is provided, described substrate is carried out to photoetching gluing and development; With silicon nitride or non-type Tan Wei barrier layer, described substrate etching is formed to two firsts compared with shallow trench; One of them first is carried out to photoresist filling compared with shallow trench region, and another first is developed compared with shallow trench region; The photoresist of take carries out further etching to another first compared with shallow trench as barrier layer, forms second compared with deep trench; Photoresist ashing is removed and carried out chemical cleaning.The present invention first utilizes high-quality mask (silicon nitride or non-type carbon) to carry out first compared with the etching of shallow trench, the photoresist of take again carries out second compared with the etching of deep trench as barrier layer, just can realize dual shallow trench technique, the photoresist of take has not only reduced the restriction to photoresistance and photoresist thickness as barrier layer, also solved etching and photoresistance has been selected to the problem of ratio, and then reduced technology difficulty, reduced production cost.
Accompanying drawing explanation
Device architecture schematic diagram after each processing step that Fig. 1～5 are respectively the present invention's one specific embodiment completes;
Fig. 6 is the flow chart of dual shallow groove isolation technology in the present invention's one specific embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.It should be noted that, accompanying drawing of the present invention all adopts the form of simplification and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Referring to Fig. 1～6, dual shallow trench isolation technique of the present invention mainly comprises the following steps:
Step 1, please refer to Fig. 1, to substrate 100 resist coatings 200 and development.Particularly, first on substrate 100, apply photoresist 200, then utilize immersion lithography equipment to develop to substrate 100, on substrate 100, form the STI pattern of more shallow depth groove.Preferably, before applying photoresist 200, can be on substrate 100 anti-reflection coating, be convenient to follow-up development and etching.
Step 2, as shown in Figure 2, usings silicon nitride or APF (agraphitic carbon) as barrier layer, carries out first compared with the etching of shallow trench, to form twice compared with shallow trench, first compared with shallow trench 310 and second compared with shallow trench 320.Particularly, if adopt SiN as barrier layer, after etching completes, do original position photoresist and remove (In-situ PR Strip); For the active area of live width less (45nm node is following), to use APF(agraphitic carbon) do barrier layer, after etching completes, then remove residual APF through photoresist ashing equipment.Further, adopt HBr, O
2or HBr, O
2and SF
6as etching gas, and by controlling O in described etching gas
2flow, can make first compared with the smooth-sided of shallow trench 300, make first more smooth compared with the bottom of shallow trench 300, to reduce the impact of bottom fillet on subsequent etching simultaneously.
Step 3, as shown in Figure 3, is filled into photoresist 200 only to need to form compared with the region of shallow trench, such as the memory block of CIS pixel region, memory device etc.; Then utilize KrF lithographic equipment to form the develop peripheral logic district etc. of ，RuCIS peripheral logic district, memory device, more deep Du region to needs, form shallow STI pattern.
In the present embodiment, setting first forms compared with the region of shallow trench for only needing compared with shallow trench 310 regions, corresponding second is to need to form more deep Du region compared with the region at shallow trench 320 places, therefore, step 3 can specifically be expressed as: photoresist 200 is filled into first compared with shallow trench 310 regions, then utilize KrF lithographic equipment to develop compared with shallow trench 320 regions to second, second, compared with shallow trench 320 regions, form STI pattern.
Step 4, as shown in Figure 4, utilizes photoresist 200 as barrier layer, form compared with the basis of shallow trench on, carry out second more deep plough groove etched.In the present embodiment, with described photoresist 200Wei barrier layer, described second carries out etching compared with shallow trench 320, thereby forms second compared with deep trench 400.Preferably, owing to making with photoresist 200 in this step as barrier layer, so photoresist can accomplish to be greater than 1um thickness, and etching process does not need to consider photoresistance to select the problem of ratio.
Step 5, as shown in Figure 5, the removal of photoresist and chemical cleaning.
Continue referring to Fig. 1～6, the present invention can the CIS dual STI technique of following for 65nm (deep-submicron is following) in, concrete steps are as follows:
Step 1, oxygen pad layer 120 and the silicon nitride 130 of on silicon substrate 110, growing successively, be then coated with anti-reflecting layer, utilizes immersion lithography equipment to develop to full wafer substrate 100;
Step 2, carries out the etching of more shallow depth groove, obtain the degree of depth and be 1500 dusts first compared with shallow trench 310 and second compared with shallow trench 320.In etching process, use silicon nitride 130 as the barrier layer of etching groove, after silicon nitride 130 is opened, does original position photoresist and remove, make after acid tank cleans, thickness 780 Izods of residual nitrogen SiClx 130 are right;
Step 3, is filled in CIS pixel region (first compared with shallow trench 310 regions) with photoresists 200 more than 5000 dusts, then uses KrF lithographic equipment to develop to peripheral logic area (the second shallow trench 320 regions);
Step 4, carries out the more deep plough groove etched of peripheral logic district, 1500 angstroms depths that formed second compared with the basis of shallow trench 320 on, utilize photoresistance as barrier layer, then continue the degree of depth of etching 1500 dusts; Finally obtained the second of 3000 dusts compared with deep trench 400;
Step 5, carries out photoresist 200 ashing removal and chemical cleaning, has finally obtained the sti structure of dual-depth (1500 dusts and 3000 dusts).
To sum up, dual shallow trench isolation technique of the present invention, comprising: substrate 100 is provided, described substrate 100 is carried out to gluing and development; With silicon nitride or non-type Tan Wei barrier layer, described substrate 100 etchings are formed to two firsts compared with shallow trench; One of them first is carried out to photoresist 200 compared with shallow trench region and fill, and another first is developed compared with shallow trench region; With photoresist 200Wei barrier layer, another first is carried out to further etching compared with shallow trench, form second compared with deep trench; Photoresist 200 ashing are removed and carry out chemical cleaning.The present invention first utilizes high-quality mask (silicon nitride or non-type carbon) to carry out first compared with the etching of shallow trench, and the photoresist of take again carries out second compared with the etching of deep trench as barrier layer, just can realize the dual shallow trench technique below deep-submicron.And take photoresist, as barrier layer, not only reduce the restriction to photoresistance and photoresist thickness, also solved etching and photoresistance has been selected to the problem of ratio, and then reduced technology difficulty, reduced production cost.Therefore, in the present invention, only need a high-quality mask plate and carry out infiltration type etching one time, just having realized two trench isolation process, compared with prior art more simple and low-cost.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these change and modification.
Claims (7)
1. a dual shallow trench isolation technique, comprising:
Substrate is provided, described substrate is carried out to photoetching gluing and development;
With silicon nitride or non-type Tan Wei barrier layer, described substrate etching is formed to two firsts compared with shallow trench;
One of them first is carried out to photoresist filling compared with shallow trench region, and another first is developed compared with shallow trench region;
The photoresist of take carries out further etching to another first compared with shallow trench as barrier layer, forms second compared with deep trench;
Photoresist ashing is removed and carried out chemical cleaning.
2. dual shallow trench isolation technique as claimed in claim 1, is characterized in that, take silicon nitride or non-type carbon as hard mask forms two firsts compared with in shallow trench step to described substrate etching, adopts HBr, O
2or HBr, O
2and SF
6as etching gas.
3. dual shallow trench isolation technique as claimed in claim 1, is characterized in that, adopts another first of the further etching of mist that contains HBr and O2 compared with shallow trench, forms second compared with deep trench.
4. dual shallow trench isolation technique as claimed in claim 1, is characterized in that, take silicon nitride as barrier layer to described substrate etching form two firsts compared with shallow trench after, carry out that original position photoresist is removed and acid tank cleaning.
5. dual shallow trench isolation technique as claimed in claim 1, is characterized in that, with non-type Tan Wei barrier layer to described substrate etching form two firsts compared with shallow trench after, adopt photoresist ashing equipment to remove described non-type carbon.
6. dual shallow trench isolation technique as claimed in claim 1, is characterized in that, adopts KrF lithographic equipment to develop compared with shallow trench region to described another first.
7. dual shallow trench isolation technique as claimed in claim 6, is characterized in that, the thickness of described photoresist is greater than 1um.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310491854.XA CN103515290A (en) | 2013-10-18 | 2013-10-18 | Double-shallow-trench isolation process |
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| CN201310491854.XA CN103515290A (en) | 2013-10-18 | 2013-10-18 | Double-shallow-trench isolation process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115616850A (en) * | 2022-12-05 | 2023-01-17 | 合肥新晶集成电路有限公司 | Mask, semiconductor structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646063A (en) * | 1996-03-28 | 1997-07-08 | Advanced Micro Devices, Inc. | Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device |
| US20050142808A1 (en) * | 2003-12-26 | 2005-06-30 | Nec Electronics Corporation | Method for manufacturing semiconductor device |
| CN1938831A (en) * | 2004-04-01 | 2007-03-28 | 微米技术有限公司 | Methods of forming trench isolation regions |
-
2013
- 2013-10-18 CN CN201310491854.XA patent/CN103515290A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646063A (en) * | 1996-03-28 | 1997-07-08 | Advanced Micro Devices, Inc. | Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device |
| US20050142808A1 (en) * | 2003-12-26 | 2005-06-30 | Nec Electronics Corporation | Method for manufacturing semiconductor device |
| CN1938831A (en) * | 2004-04-01 | 2007-03-28 | 微米技术有限公司 | Methods of forming trench isolation regions |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115616850A (en) * | 2022-12-05 | 2023-01-17 | 合肥新晶集成电路有限公司 | Mask, semiconductor structure and preparation method thereof |
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