CN102867742A - Plasma etching method for eliminating morphologic deformation - Google Patents
Plasma etching method for eliminating morphologic deformation Download PDFInfo
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- CN102867742A CN102867742A CN2012103434662A CN201210343466A CN102867742A CN 102867742 A CN102867742 A CN 102867742A CN 2012103434662 A CN2012103434662 A CN 2012103434662A CN 201210343466 A CN201210343466 A CN 201210343466A CN 102867742 A CN102867742 A CN 102867742A
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- etching method
- polysilicon gate
- plasma etching
- pattern distortion
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Abstract
The invention relates to a polysilicon etching method, and particularly relates to a plasma etching method for eliminating morphologic deformation. According to the plasma etching method for eliminating morphologic deformation, a high-selection-ratio polysilicon gate etching process based on oxide is adopted prior to polysilicon gate etching, so that residual anti-reflection coating is completely removed, thereby enabling the morphology of the etched polysilicon to be smooth and complete and ensuring that the process and the equipment performance are improved.
Description
Technical field
The present invention relates to a kind of method of etch polysilicon, relate in particular to a kind of plasma etching method of eliminating the pattern distortion.
Background technology
In the semiconductor fabrication process, the manufacturing of polysilicon gate is very crucial, and is also very large on the impact of device.Wherein particularly important to the control of etching polysilicon pattern, require generally speaking the etching surface vertical smooth, not distortion.
Because the size of polysilicon gate is constantly dwindled, original single-layer lithography glue is subject to the characteristics such as thickness, reflectivity control, etch resistance of photoresist self as etching barrier layer, can not satisfy integrated requirement.The polysilicon gate construction of the multilayer barrier layer of newly developing at present, as shown in Figure 1a, this structure composition is mainly from the bottom up successively deposition substrate silicon chip 5, oxide 4, polysilicon gate 3, agraphitic carbon 2, antireflecting coating 1, photoresist (not shown).When the polysilicon gate construction to this multilayer barrier layer carried out etching, existing lithographic method was first etching antireflecting coating 1, and then etch amorphous carbon 2, and the etch polysilicon grid 3 again.
But because before the etching polysilicon gate step, antireflecting coating 1 still has a certain amount of residual, as shown in Figure 1a, be as etching barrier layer with antireflecting coating 1 in the incipient stage of polysilicon gate construction etching, etching after a period of time agraphitic carbon 2 just as etching barrier layer, thereby form the situation that two kinds of etching barrier layers coexistences are arranged in the polysilicon gate construction etching process.Yet the Main Ingredients and Appearance of antireflecting coating 1 is SiO
2 Agraphitic carbon 2 Main Ingredients and Appearances are carbon; this obviously exerts an influence for the formation of the polymer protective layer in the etching process, in general, when antireflecting coating 1 during as etching barrier layer polymer less; when agraphitic carbon 2 during as etching barrier layer polymer more; thereby so that polysilicon forms obvious boundary, make the pattern distortion, shown in Fig. 1 b; polysilicon gate 3 patterns are unsmooth, finally affect the control of technique and device performance.
Summary of the invention
Problem for above-mentioned existence, purpose of the present invention provides a kind of plasma etching method of eliminating the pattern distortion, by before etching polysilicon gate, increasing the oxidation step thing to the etching technics of polysilicon gate high selectivity, remove residual antireflecting coating fully, so that the polysilicon pattern after the etching is smooth complete, guarantee that technique and device performance promote.
The objective of the invention is to be achieved through the following technical solutions:
A kind of plasma etching method of eliminating the pattern distortion wherein, may further comprise the steps:
Step 1: polysilicon gate construction is from the bottom up successively deposition oxide, polysilicon gate, agraphitic carbon, antireflecting coating, photoresist on a silicon substrate;
Step 2: described polysilicon gate construction is put into reaction chamber;
Step 3: take described photoresist as mask, the described antireflecting coating outside the described photoresist of etching covers is to the upper surface of described agraphitic carbon;
Step 4: continue take remaining described antireflecting coating as mask, the described agraphitic carbon of etching is to the upper surface of described polysilicon gate;
Step 5: utilize wafer to remove the remaining described antireflecting coating in described agraphitic carbon surface fully;
Step 6: utilize described wafer to continue the upper surface of the described oxide of described polysilicon gate best outside the described agraphitic carbon covering of etching, remove remaining described agraphitic carbon.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, each step of described plasma etching method all adopts dry plasma etch technique.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, oxide described in the step 1 is to selection ratio＞7 of described polysilicon gate.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, antireflecting coating described in the step 1 adopts SiO2 class inorganic anti-reflective coating.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 3 uses CF4 to be main etching gas.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 4 uses O2 to be main etching gas.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 is controlled the loss＜20A of described polysilicon gate.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 is used the etching gas as leading take C4F8 or C5F8, and C4F8 or C5F8 flow are 5-10sccm simultaneously.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 uses supply voltage and bias power all more than or equal to 200W and less than or equal to 300W.
The invention has the beneficial effects as follows by before etching polysilicon gate, increasing the oxidation step thing to the etching technics of polysilicon gate high selectivity, so that the polysilicon pattern after the etching is smooth complete, guarantee that technique and device performance promote, reduce the production loss, improve productivity effect.
Description of drawings
Fig. 1 a-1b is the etching schematic flow sheet of existing polysilicon gate construction;
Fig. 2 a-2d is a kind of schematic flow sheet of eliminating the plasma etching method of pattern distortion of the present invention.
Embodiment
The invention will be further described below in conjunction with schematic diagram and concrete operations preferred version.
Shown in Fig. 2 a-2d, a kind of plasma etching method of eliminating the pattern distortion wherein, may further comprise the steps:
Shown in Fig. 2 a, step 1: polysilicon gate construction is from the bottom up successively deposition oxide 22, polysilicon gate 23, agraphitic carbon 24, antireflecting coating 25, photoresist 26 on a silicon substrate 21;
In a preferred version of the present invention, each step of plasma etching method of the present invention all adopts dry plasma etch technique, selection ratio＞7 of 22 pairs of polysilicon gates 23 of oxide;
Further, antireflecting coating 25 adopts SiO
2The class inorganic anti-reflective coating.
Step 2: polysilicon gate construction is put into reaction chamber;
On the technique scheme basis, further, following steps can be integrated into same reaction chamber and finish, and also can be chosen in different reaction chambers and finish respectively.
Shown in Fig. 2 b, step 3: take photoresist 26 as mask, the antireflecting coating 25 outside etching photoresist 26 covers is to the upper surface of agraphitic carbon 24;
Further, etching process is used CF in this step
4It is main etching gas.
Shown in Fig. 2 c, step 4: continue take remaining antireflecting coating 25 as mask, etch amorphous carbon 24 is to the upper surface of polysilicon gate 23;
Further, etching process is used O in this step
2It is main etching gas.
Step 5: utilize plasma process to remove the remaining antireflecting coating 25 in agraphitic carbon 24 surfaces fully;
Further, the loss＜20A of etching process control polysilicon gate 23 in this step;
In a preferred version of the present invention, but the etching process choice for use is take C4F8 or C5F8 as main etching gas in this step, C4F8 or C5F8 flow are 5-10sccm simultaneously, simultaneously, use supply voltage and bias power all more than or equal to 200W and less than or equal to 300W.
Shown in Fig. 2 d, step 6: utilize wafer to continue the polysilicon gate 23 of etch amorphous carbon 24 outside covering to the upper surface of oxide 22, remove remaining agraphitic carbon 24.
Polysilicon pattern after the etching is smooth complete, guarantees that technique and device performance promote.
More than concrete preferred version of the present invention is described in detail, but the present invention is not restricted to concrete preferred version described above, it is just as example.To those skilled in the art, any equivalent modifications and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (9)
1. a plasma etching method of eliminating the pattern distortion is characterized in that, may further comprise the steps:
Step 1: polysilicon gate construction is from the bottom up successively deposition oxide, polysilicon gate, agraphitic carbon, antireflecting coating, photoresist on a silicon substrate;
Step 2: described polysilicon gate construction is put into reaction chamber;
Step 3: take described photoresist as mask, the described antireflecting coating outside the described photoresist of etching covers is to the upper surface of described agraphitic carbon;
Step 4: continue take remaining described antireflecting coating as mask, the described agraphitic carbon of etching is to the upper surface of described polysilicon gate;
Step 5: remove the remaining described antireflecting coating in described agraphitic carbon surface fully;
Step 6: continue the upper surface of the described oxide of described polysilicon gate best outside the described agraphitic carbon covering of etching, remove remaining described agraphitic carbon.
2. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that each step of described plasma etching method all adopts dry plasma etch technique.
3. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that oxide described in the step 1 is to selection ratio＞7 of described polysilicon gate.
4. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that, antireflecting coating described in the step 1 adopts SiO
2The class inorganic anti-reflective coating.
5. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that, the etching process of step 3 is used CF
4It is main etching gas.
6. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that, the etching process of step 4 is used O
2It is main etching gas.
7. the plasma etching method of elimination pattern distortion according to claim 1 is characterized in that the etching process of step 5 is controlled the loss＜20A of described polysilicon gate.
8. the plasma etching method of elimination pattern distortion according to claim 7 is characterized in that, the etching process of step 5 is used with C
4F
8Or C
5F
8Be main etching gas, while C
4F
8Or C
5F
8Flow is 5-10sccm.
9. the plasma etching method of elimination pattern distortion according to claim 8 is characterized in that, the etching process of step 5 uses supply voltage and bias power all more than or equal to 200W and less than or equal to 300W.
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| CN201210343466.2A CN102867742B (en) | 2012-09-17 | 2012-09-17 | Plasma etching method for eliminating morphologic deformation |
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| CN102867742B CN102867742B (en) | 2015-06-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881597A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for manufacturing transistor |
| CN108133887A (en) * | 2017-12-04 | 2018-06-08 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6797552B1 (en) * | 2002-11-19 | 2004-09-28 | Advanced Micro Devices, Inc. | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices |
| US6989332B1 (en) * | 2002-08-13 | 2006-01-24 | Advanced Micro Devices, Inc. | Ion implantation to modulate amorphous carbon stress |
| CN1809916A (en) * | 2003-07-28 | 2006-07-26 | 飞思卡尔半导体公司 | A semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
| US20110049098A1 (en) * | 2009-08-27 | 2011-03-03 | Tokyo Electron Limited | Plasma etching method |
-
2012
- 2012-09-17 CN CN201210343466.2A patent/CN102867742B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989332B1 (en) * | 2002-08-13 | 2006-01-24 | Advanced Micro Devices, Inc. | Ion implantation to modulate amorphous carbon stress |
| US6797552B1 (en) * | 2002-11-19 | 2004-09-28 | Advanced Micro Devices, Inc. | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices |
| CN1809916A (en) * | 2003-07-28 | 2006-07-26 | 飞思卡尔半导体公司 | A semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
| US20110049098A1 (en) * | 2009-08-27 | 2011-03-03 | Tokyo Electron Limited | Plasma etching method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881597A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for manufacturing transistor |
| CN108133887A (en) * | 2017-12-04 | 2018-06-08 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
| CN108133887B (en) * | 2017-12-04 | 2019-07-02 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
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| CN102867742B (en) | 2015-06-24 |
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