CN104851775A - Method for repairing damage on substrate in source/drain region - Google Patents
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- CN104851775A CN104851775A CN201410050502.5A CN201410050502A CN104851775A CN 104851775 A CN104851775 A CN 104851775A CN 201410050502 A CN201410050502 A CN 201410050502A CN 104851775 A CN104851775 A CN 104851775A
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Abstract
The invention relates to the technical field of semiconductor manufacture, and particularly to a method for repairing damage on a substrate in a source/drain region. After a process which causes the damage to the source/drain region substrate, one time or multiple times of selective epitaxial growth process are performed on the substrate in the source/drain region, thereby growing a repairing film of which the material, the physical property, the chemical property and the like are totally same with that of the substrate on the surface of the damaged substrate, thereby finishing repair such as material structure loss compensation and substrate surface roughness reduction on the damage, thereby further improving the performance of a final prepared CMOS device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of reparation and be positioned at the method that active area substrate damages.
Background technology
At present, along with the miniaturization trend of semiconductor device structure, the size of cmos device product also reduces continual, and the loss (the substrate and material loss) of substrate and material is more and more serious in the preparation technology of device products.
According to international semiconductor Technology Roadmap (International Technology RoadmapFor Semiconductors, be called for short ITRS) display, surface roughness (surface roughness) damage of cmos device structure and silicon (silicon), the loss (loss) of oxide (oxide) becomes more and more serious, as in the preparation process of CMOS product, when carrying out master stela erosion (main-spacer etch)/biased side wall etching (offset etch) processing step, all can cause loss or the damage (Si substrate recess/damage) of silicon substrate.
Concrete, carrying out as gate dielectric layer and side wall film (sidewall fiim) peel off (scaling) technique, or adopt reactive ion etching process (Reactive Ion Etching, be called for short RIE) etch formation gate patterns (gate patterning) or grid curb wall (spacer) technique, the even cleaning (cleaning) of device surface, in ashing (ash) technique, all can be thinner due to the etching stop layer (etch stop layer) covering surface of silicon, the major injury (very grievoussubstrate damage) that silicon substrate is subject to when carrying out above-mentioned technique cannot be stopped, as when carrying out above-mentioned technique, can to being positioned at active area (i.e. source/drain region (source/drain, be called for short S/D)) the silicon of surface of silicon and the material such as oxide cause serious loss (material loss), also can increase the roughness on the surface of silicon substrate further.
Summary of the invention
For above-mentioned technical problem, this application provides a kind of reparation and be positioned at the method that active area substrate damages, be mainly used in the reparation of the damage (as the roughness increasing surface of silicon, the loss etc. that causes the materials such as the silicon of surface of silicon and oxide serious) carrying out causing the silicon substrate being positioned at active area (S/D district) time prepared by cmos device.
The application describes a kind of reparation and is positioned at the method that active area substrate damages, and wherein, described method comprises:
The Semiconductor substrate that one is provided with active area is provided;
When carrying out cmos device preparation technology in this Semiconductor substrate, after the Semiconductor substrate being positioned at active area forms damage, selective epitaxial growth process is adopted to repair described damage.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described cmos device preparation technology comprises gate patterns metallization processes, biased side wall etching technics, master stela etching technique, cineration technics and cleaning;
Carry out described gate patterns metallization processes, described biased side wall etching technics, described master stela etching technique, described cineration technics and/or described cleaning in described Semiconductor substrate after, selective epitaxial growth process is adopted to repair described damage.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described damage comprises material unaccounted-for (MUF) and substrate surface for roughness increases.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described material unaccounted-for (MUF) comprises silicon loss and/or oxide loss.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described selective epitaxial growth process forms one and repairs plastic film covering in the Semiconductor substrate being positioned at active area, to repair described damage.
Above-mentioned reparation is positioned at the method that active area substrate damages, wherein, and identical all with described Semiconductor substrate of the material of described reparation film and physicochemical properties thereof.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, the thickness of described reparation film is 20 ~ 100 dusts.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, is under the condition of 500 ~ 800 DEG C in temperature, adopts SiH
4or DCS is as reacting gas, in reaction chamber, pass into H simultaneously
2and HCL, carry out described selective epitaxial growth process.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described Semiconductor substrate is silicon substrate.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, adopts monolithic or batch processed system to carry out described cmos device preparation technology.
The application also describes a kind of reparation and is positioned at the method that active area substrate damages, and wherein, described method comprises:
Semi-conductive substrate is provided;
After the upper surface of this Semiconductor substrate covers a gate oxide layers, prepare polysilicon layer or amorphous silicon layer at the upper surface of this gate oxide;
Continue to carry out gate patterning process, biased side wall preparation technology, light dope technique, annealing process, master wall preparation technology and source/drain injection technology successively;
Wherein, after biased side wall preparation technology and/or master wall preparation technology, selective epitaxial growth process is carried out to the surface of the Semiconductor substrate exposed.
Above-mentioned reparation is positioned at the preparation method of the method that active area substrate damages, wherein, all cause damage to the semiconductor substrate surface exposed when carrying out biased side wall preparation technology and master wall preparation technology, described selective epitaxial growth process is repaired described damage.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described selective epitaxial growth process forms one and repairs plastic film covering in the Semiconductor substrate exposed, to repair described damage.
Above-mentioned reparation is positioned at the method that active area substrate damages, wherein, and identical all with described Semiconductor substrate of the material of described reparation film and physicochemical properties thereof.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, the thickness of described reparation film is 20 ~ 100 dusts.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described damage comprises material unaccounted-for (MUF) and substrate surface for roughness increases.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described material unaccounted-for (MUF) comprises silicon loss and/or oxide loss.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, is under the condition of 500 ~ 800 DEG C in temperature, adopts SiH
4or DCS is as reacting gas, in reaction chamber, pass into H simultaneously
2and HCL, carry out described selective epitaxial growth process.
Above-mentioned reparation is positioned at the method that active area substrate damages, and wherein, described Semiconductor substrate is silicon substrate.
In sum, owing to have employed technique scheme, a kind of reparation that the application proposes is positioned at the method that active area substrate damages, be applied in the preparation technology of cmos device, by after technique active area substrate being caused to damage, the substrate being positioned at this active area is carried out to the selective epitaxial growth process of one or many, to grow completely identical with this substrate reparation film of the character such as a material and physical chemistry thereof at the substrate surface sustained damage, and then complete the compensation that above-mentioned damage is lost as material structure and the roughness etc. reducing substrate surface, further to improve the performance of the cmos device of final preparation.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram that the application's reparation is arranged in method one embodiment that active area substrate damages;
Fig. 2 ~ 6 are flowage structure schematic diagrames that the application's reparation is arranged in another embodiment of method that active area substrate damages.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 1 is the method flow schematic diagram that the application's reparation is arranged in method one embodiment that active area substrate damages; As shown in Figure 1, a kind of reparation in the application is positioned at the method that active area substrate damages, can be applicable in the preparation technology of cmos device (advanced CMOS logic), especially be applied in the preparation technology of the cmos device adopting monolithic (single wafer) or batch processed (batch) system to carry out, the method comprises:
First, provide one for the preparation of the Semiconductor substrate of cmos device structure as silicon substrate etc., and this silicon substrate is preset with active area (i.e. source/drain region).
Secondly, this Semiconductor substrate is carried out the preparation technology of cmos device structure, when the preparation technology carried out causes damage lose (as silicon or oxide loss etc.) as structural material or increase the roughness etc. of substrate surface to the Semiconductor substrate being arranged in active area, adopt optionally epitaxial growth technology (selective Si epi-growth, be called for short SEG), selective growth one material and chemical physical property all identical reparation films with this Semiconductor substrate is carried out for the Semiconductor substrate being positioned at active area, and then complete the technique that above-mentioned damage is repaired.
Preferably, as when carrying out the preparation technology of cmos device structure to the silicon substrate being provided with active area, when carrying out gate patterns metallization processes (gate patterning), biased side wall etching technics (offset etch), master stela etching technique (main spacer etch), after cineration technics (ashprocess) and/or cleaning (clean prcess), certain silicon loss all can be caused to the silicon substrate being positioned at active area, also increase the roughness of the surface of silicon of active area simultaneously, and the loss of silicon materials and larger surface roughness all can produce certain negative effect to the performance of follow-up fabricate devices product in silicon substrate, in order to further improve performance and the stability thereof of follow-up fabricate devices product, in the present embodiment be then temperature be 500 ~ 800 DEG C (as 500 DEG C, 600 DEG C, 700 DEG C or 800 DEG C etc.) condition under, adopt SiH
4or DCS(SiH
2cl
2) as reacting gas, in reaction chamber, pass into H simultaneously
2and HCL, on the surface of the silicon substrate of active area, selective epitaxial growth a layer thickness is
(as
or
deng) reparation film, the material of this reparation film identical with the material of silicon substrate (namely the material of this reparation film is silicon), and identical all with above-mentioned silicon substrate of the physicochemical properties of this reparation film, and then at effective compensation due to above-mentioned etching (RIE etch, namely as gate patterns metallization processes, biased side wall etching technics and/or master stela etching technique etc.), the silicon materials loss that the techniques such as cleaning or ashing cause, greatly reduce again the roughness (namely planarization (flat) having been carried out to the surface of silicon substrate) of surface of silicon simultaneously, and then improve the performance (improve transistor performance) of device.
Further, all to there being the silicon substrate of damage to carry out once above-mentioned selective epitaxial growth process after carrying out each above-mentioned processing step (i.e. gate patterns metallization processes, biased side wall etching technics, master stela etching technique, cineration technics (ash process) and cleaning), also can after carrying out multiple above-mentioned processing step, again to there being the silicon substrate of damage to carry out the above-mentioned selective epitaxial growth process of one or many, damage as long as namely make silicon substrate in the last device architecture formed can not cause because of each above-mentioned processing step.
Fig. 2 ~ 6 are flowage structure schematic diagrames that the application's reparation is arranged in another embodiment of method that active area substrate damages; As figures 2-6, a kind of reparation is positioned at the method that active area substrate damages, can be applicable in the preparation technology of cmos device (advanced CMOS logic), especially be applied in the preparation technology of the cmos device adopting monolithic (single wafer) or batch processed (batch) system to carry out, the method comprises:
First, one is provided for the preparation of the Semiconductor substrate 1 of cmos device structure, material preferably silicon etc. of this Semiconductor substrate 1; In the upper surface of this Semiconductor substrate 1 deposit a gate medium (Gate dielectric) as gate oxide (Gate oxide) after, deposition of amorphous silicon or polycrystalline silicon gate layer (UPY or APY dep), after gate patterning process (Gate Patterning), the grid stacked structure be made up of gate oxide 2 and grid 3 is formed in Semiconductor substrate 1, and hard mask layer 4(Hard Mask is coated with in the upper surface of grid 3 after above-mentioned gate patterning process), namely form structure as shown in Figure 2.
Secondly, continue the depositing operation (offset spacer dep) of biased side wall layer 5, and then form structure as shown in Figure 3; As shown in Figure 3, gate oxide 2 part of preparation is covered in the upper surface of Semiconductor substrate 1, the upper surface of grid 3 covering gate oxide layer 2, hard mask layer 4 covers the upper surface of grid 3, biased side wall layer 5 covers top surface and the sidewall thereof of hard mask layer 4, the upper surface of the also sidewall of cover gate 3, the sidewall of gate oxide 2 and Semiconductor substrate 1 exposure simultaneously.
Wherein, above-mentioned grid 3 can be grid (poly gate) or the sample grid (dummy gate) of cmos device, and when this grid 3 is the grid of cmos device, gate oxide 2 is the grid oxide layer (oxide) of cmos device, and when this grid 3 is sample grid, this gate oxide 2 is sample gate oxide layers (dummy oxide); The material preferably SiN of biased side wall layer 5.
Afterwards, selective etch technique (offset etch) is carried out to biased side wall layer 5, to remove the biased side wall layer 5 be positioned on the upper surface of hard mask layer 4 and the upper surface of Semiconductor substrate 1, and make remaining biased side wall layer on the sidewall of grid stacked structure, form biased side wall 51, and this biased side wall 51 also covers the sidewall of hard mask layer 4; When carrying out the etching technics of this step, generally need first to carry out photoetching process, namely after spin coating photoresist covers the surface of structure as shown in Figure 3, the photoresistance with side wall figure is formed through exposure, developing process, again with this photoresistance for mask etching is biased side wall layer 5, and after utilizing ashing, cleaning removal photoresistance, form structure as shown in Figure 4.
Wherein, when carrying out above-mentioned etching, ashing, cleaning, all can cause certain damage to the surface (being generally the follow-up position being formed with source region) that Semiconductor substrate 1 exposes, and be coated with hard mask layer 4 due to grid 3 upper surface and its sidewall is coated with biased side wall 51, and then make when carrying out above-mentioned technique, grid 3 can well be protected, and then effectively avoids sustaining damage; As shown in Figure 4, after etching technics, remaining Semiconductor substrate 11 surface just have lost the material 12 of a part, and the roughness on its surface to be also increased a lot simultaneously, this all can cause certain negative effect to the performance of the device architecture of follow-up technique and final preparation.
Afterwards, in order to repair in above-mentioned etching, ashing and cleaning the damage that Semiconductor substrate causes, need to carry out selective epitaxial growth process in the remaining Semiconductor substrate 11 with damage, as shown in Figure 4, due to material preferably inorganic material as the upper face of hard mask (hard mask) 4 cover gate 3 of dielectric material etc., and material is that its surface also can not grown epitaxial layer in epitaxial growth technology for the biased side wall 51 of silicon nitride, therefore directly can carry out epitaxial growth technology (certainly to structure as shown in Figure 4, also can according to concrete technology demand first by preparation one mask layer, and this mask layer covers other regions extra-regional except the remaining Semiconductor substrate 11 sustained damage exposes, to avoid growing unwanted epitaxial loayer in other regions, affect processing quality), to repair above-mentioned damage.
Wherein, be then described for silicon substrate for Semiconductor substrate 1 in the present embodiment, as shown in Figure 5, the epitaxy technique 6 carried out is specially: adopt SiH
4or DCS(SiH
2cl
2) as reacting gas, be under the condition of 500 ~ 800 DEG C (as 500 DEG C, 650 DEG C, 750 DEG C or 800 DEG C etc.) in temperature, in reaction chamber, pass into H
2and HCL, with the upper surface selective epitaxial growth a layer thickness exposed in remaining Semiconductor substrate 11 be
(as
or
deng) reparation film 7, identical all with remaining Semiconductor substrate 11 of the material of this reparation film 7 and physicochemical properties, final formation structure as shown in Figure 6, and then the increase equivalent damage repairing material unaccounted-for (MUF) and the surface roughness caused in above-mentioned technique.
Further, when forming above-mentioned grid stacked structure, need etching grid layer and gate dielectric layer to Semiconductor substrate 1 surface, now also can cause certain material unaccounted-for (MUF) and the increase of surface roughness to the surface of this Semiconductor substrate 1, and it is follow-up for removing the ashing that photoresistance residual in above-mentioned etching technics carries out, cleaning equally also all can cause certain damage to the surface of Semiconductor substrate 1, also can in above-mentioned each etching, above-mentioned selective epitaxial growth process is carried out once after ashing and/or cleaning, also can after multiple processing step, the above-mentioned selective epitaxial growth process of carrying out one or many carries out the reparation to Semiconductor substrate surface damage.
Wherein, after carrying out above-mentioned selective epitaxial growth process, the mask layer of hard mask 4 and preparation can be removed immediately, also can under the prerequisite do not had an impact to subsequent technique, continues with this hard mask 4 and/or mask layer as mask carries out selective epitaxial growth process repeatedly.
Then, proceed light dope ion implantation technology (LDD IMP), thermal anneal process (thermal ann) and master wall preparation technology, and equally also need to carry out photoetching when carrying out this master wall preparation technology, etching, ashing, cleaning, as long as after carrying out causing the technique of damage to the surface of the Semiconductor substrate being positioned at active area, all above-mentioned selective epitaxial growth process can be carried out, to repair the damage produced, too can after last can produce the processing step of damage to Semiconductor substrate, carry out again above-mentioned selective epitaxial growth process, to repair the damage produced, because its processing step and relevant technological parameter are all similar to above-mentioned selective epitaxial growth process of carrying out after carrying out biased side wall preparation technology, at this, just it will not go into details.
Finally, after the ion implantation technology (S/D IMP) of carrying out source-drain electrode and annealing process, source-drain area is formed in the Semiconductor substrate through repairing, and after continuing the preparation technology of follow-up dielectric layer and through hole (Silicidation & Metallization), to form cmos device.
Wherein, each etching in the preparation technology of above-mentioned cmos device structure, after cleaning and/or ashing etc. cause damage technique to the Semiconductor substrate exposed, all can carry out once optionally renovation technique to the semiconductor substrate surface damage being positioned at exposure, also can in multiple etching, this Semiconductor substrate is being carried out to Selective repair technique after the techniques such as cleaning and/or ashing, concrete can set according to actual process demand, the thickness of the reparation film simultaneously grown after each Selective repair technique also can carry out the adjustment of humidity according to concrete process environments, active area silicon substrate damage is repaired for final purpose reaching.
To sum up, owing to have employed technique scheme, a kind of reparation that the application proposes is positioned at the method that active area substrate damages, can be applicable in the preparation technology of cmos device, by after technique active area substrate being caused to damage, the substrate being positioned at this active area is carried out to the selective epitaxial growth process of one or many, to grow completely identical with this substrate reparation film of the character such as a material and physical chemistry thereof at the substrate surface sustained damage, and then complete the compensation that above-mentioned damage is lost as material structure and the roughness etc. reducing substrate surface, further to improve the performance of the cmos device of final preparation.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, each middle change and correction undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (19)
1. reparation is positioned at the method that active area substrate damages, and it is characterized in that, described method comprises:
The Semiconductor substrate that one is provided with active area is provided;
When carrying out cmos device preparation technology in this Semiconductor substrate, after the Semiconductor substrate being positioned at active area forms damage, selective epitaxial growth process is adopted to repair described damage.
2. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, described cmos device preparation technology comprises gate patterns metallization processes, biased side wall etching technics, master stela etching technique, cineration technics and cleaning;
Carry out described gate patterns metallization processes, described biased side wall etching technics, described master stela etching technique, described cineration technics and/or described cleaning in described Semiconductor substrate after, selective epitaxial growth process is adopted to repair described damage.
3. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, described damage comprises material unaccounted-for (MUF) and substrate surface for roughness increases.
4. reparation according to claim 3 is positioned at the method that active area substrate damages, and it is characterized in that, described material unaccounted-for (MUF) comprises silicon loss and/or oxide loss.
5. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, described selective epitaxial growth process forms one and repairs plastic film covering in the Semiconductor substrate being positioned at active area, to repair described damage.
6. reparation according to claim 5 is positioned at the method that active area substrate damages, and it is characterized in that, identical all with described Semiconductor substrate of the material of described reparation film and physicochemical properties thereof.
7. reparation according to claim 5 is positioned at the method that active area substrate damages, and it is characterized in that, the thickness of described reparation film is 20 ~ 100 dusts.
8. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, is under the condition of 500 ~ 800 DEG C in temperature, adopts SiH
4or DCS is as reacting gas, in reaction chamber, pass into H simultaneously
2and HCL, carry out described selective epitaxial growth process.
9. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, described Semiconductor substrate is silicon substrate.
10. reparation according to claim 1 is positioned at the method that active area substrate damages, and it is characterized in that, adopts monolithic or batch processed system to carry out described cmos device preparation technology.
11. 1 kinds of reparations are positioned at the method that active area substrate damages, and it is characterized in that, described method comprises:
Semi-conductive substrate is provided;
After the upper surface of this Semiconductor substrate covers a gate oxide layers, prepare polysilicon layer or amorphous silicon layer at the upper surface of this gate oxide;
Continue to carry out gate patterning process, biased side wall preparation technology, light dope technique, annealing process, master wall preparation technology and source/drain injection technology successively;
Wherein, after biased side wall preparation technology and/or master wall preparation technology, selective epitaxial growth process is carried out to the surface of the Semiconductor substrate exposed.
12. reparations according to claim 11 are positioned at the preparation method of the method that active area substrate damages, it is characterized in that, all cause damage to the semiconductor substrate surface exposed when carrying out biased side wall preparation technology and master wall preparation technology, described selective epitaxial growth process is repaired described damage.
13. reparations according to claim 12 are positioned at the method that active area substrate damages, and it is characterized in that, described selective epitaxial growth process forms one and repairs plastic film covering in the Semiconductor substrate exposed, to repair described damage.
14. reparations according to claim 13 are positioned at the method that active area substrate damages, and it is characterized in that, identical all with described Semiconductor substrate of the material of described reparation film and physicochemical properties thereof.
15. reparations according to claim 13 are positioned at the method that active area substrate damages, and it is characterized in that, the thickness of described reparation film is 20 ~ 100 dusts.
16. reparations according to claim 11 are positioned at the method that active area substrate damages, and it is characterized in that, described damage comprises material unaccounted-for (MUF) and substrate surface for roughness increases.
17. reparations according to claim 16 are positioned at the method that active area substrate damages, and it is characterized in that, described material unaccounted-for (MUF) comprises silicon loss and/or oxide loss.
18. reparations according to claim 11 are positioned at the method that active area substrate damages, and it is characterized in that, are under the condition of 500 ~ 800 DEG C in temperature, adopt SiH
4or DCS is as reacting gas, in reaction chamber, pass into H simultaneously
2and HCL, carry out described selective epitaxial growth process.
19. reparations according to claim 11 are positioned at the method that active area substrate damages, and it is characterized in that, described Semiconductor substrate is silicon substrate.
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| CN111133562A (en) * | 2018-05-15 | 2020-05-08 | 东京毅力科创株式会社 | Component forming method and substrate processing system |
| CN108735589A (en) * | 2018-05-25 | 2018-11-02 | 武汉新芯集成电路制造有限公司 | A kind of restorative procedure of polysilicon surface |
| CN114121612A (en) * | 2022-01-27 | 2022-03-01 | 广东省大湾区集成电路与系统应用研究院 | FDSOI silicon epitaxial growth process optimization method |
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