CN105185746B - The preparation method of germanium silicon epitaxial layer in cmos device technique - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 54
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 230000012010 growth Effects 0.000 claims abstract description 15
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- -1 silicon ion Chemical class 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000003851 corona treatment Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000006378 damage Effects 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000037230 mobility Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of preparation methods of germanium silicon epitaxial layer in cmos device technique, and the first hard mask and the second hard mask are formed first in semiconductor device substrates, the second hard mask of PMOS area are then removed, to expose PMOS area；Then, ion implanting is carried out to the source-drain area of PMOS, subsequently etches source-drain area surface again and carry out germanium and silicon epitaxial growth.Plasma causes to damage to the source-drain area surface of PMOS, so as to improve the etch rate on subsequent etching source-drain area surface, the source-drain area surface etch time is then accordingly reduced, in this way, it can reduce in etching process to the damage of surface of shallow trench isolation structure, it avoids too serious to surface of shallow trench isolation structure damage and exposes the surfaces of active regions of PMOS, so as to overcome in prior art easily PMOS boundaries grow extra germanium silicon epitaxial layer the defects of.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to the preparation side of germanium silicon epitaxial layer in a kind of cmos device technique
Method.
Background technology
Conventional silicon technologies are being faced with the problem of a series of new according to Moore's Law evolution, characteristic size constantly contracts
The problem of small and gate dielectric layer thickness reduction is brought includes ghost effect, and leakage current increase, short-channel effect is serious, hot current-carrying
Sub- effect and mobil-ity degradation, the difficulty and cost of technology, diffraction during photolithographic exposure etc., this causes cmos circuit
Performance is largely restricted by PMOS.
In the PMOS of 90nm, usually the source of device, water clock etching off are removed, then deposit germanium silicon layer (SiGe) again, this
Sample source and leakage will generate a compression stress to raceway groove, so as to improve the transmission characteristic of PMOS.
Referring to Fig. 1, in existing cmos device technique germanium silicon epitaxial layer preparation method, including：
Step L1：Fig. 2 a are please referred to, semiconductor device substrate 100 is provided；Semiconductor device substrates 100 have NMOS and
PMOS has fleet plough groove isolation structure 108 between the active area 101 of NMOS and PMOS；Grid are respectively provided in NMOS and PMOS
Pole 102, the source-drain area (not shown) positioned at 102 liang of side bottoms of grid, the side wall 103 positioned at gate lateral wall and positioned at grid
The first hard mask 104 on 102；
Step L2：Fig. 2 b are please referred to, in the first hard mask 104, side wall 103 and the fleet plough groove isolation structure of NMOS and PMOS
108 surfaces form the second hard mask 105；
Step L3：Fig. 2 c are please referred to, the second hard mask 105 are patterned, so as to expose the source-drain area of PMOS and shallow trench
108 surface of isolation structure；Here, when the second hard mask 105 of lithographic definition is to open source-drain area, since technique limits,
CD needs to be made slightly larger, inevitably etches away the second hard Mask portion on fleet plough groove isolation structure 108.
Step L4：Fig. 2 d are please referred to, the source-drain area of PMOS is performed etching, to form ditch on the source-drain area surface of PMOS
Slot；Meanwhile also groove 106 is formed on 108 surface of fleet plough groove isolation structure；
Step L5：Fig. 2 e are please referred to, cleaning is carried out to semiconductor device substrates 100；Then, in the source-drain area of PMOS
Germanium and silicon epitaxial growth is carried out in the groove on surface, so as to form germanium silicon epitaxial layer.Due to 108 surface of fleet plough groove isolation structure by
To etching and cleaning, PMOS active area border surfaces are exposed, so as to grow extra germanium in PMOS active area boundaries
Silicon epitaxy object 107.
In above-mentioned technique, in particular in 40nm, 28nm technical process, the growth and control of SiGe occur huge
Challenge, particularly process window limitation, in the etching process in step L4, as shown in Figure 2 d, shallow trench can be etched into
The oxidation film on 108 surface of isolation structure, and 101 border surface of PMOS active areas is exposed, after being etched in SiGe
Cleaning process before being grown with SiGe causes the further loss of oxide layer (Oxide) on fleet plough groove isolation structure (STI),
Cause grid (Poly) that can not all cover SRAM regions PMOS active areas boundary, the PMOS active areas in SiGe epitaxial growths
Edge is exposed and grows extra SiGe extensions object 107, forms defect, as shown in Figure 2 e, also, these SiGe are extra
The size and the direction of growth of object are unable to control, and subsequent technique is caused to seriously affect, and even result in SRAM failures, therefore find
Suitable technical process, which prevents PMOS active-surfaces from growing SiGe fifth wheels, to be especially important, is received so as to solve 45/40
Maximum process challenge in rice integrated circuit.
Invention content
In order to overcome problem above, the present invention is intended to provide in cmos device technique germanium silicon epitaxial layer preparation method, lead to
The source-drain area of PMOS is crossed using ion implanting, so as to accelerate the etching speed of the source-drain area, is reduced in the source-drain area etching process
In damage to surface of shallow trench isolation structure, to avoid active areas of the PMOS close to fleet plough groove isolation structure boundary is exposed.
To achieve these goals, the present invention provides a kind of preparation method of germanium silicon epitaxial layer in cmos device technique,
It includes the following steps：
Step 01：Semiconductor device substrate is provided；The semiconductor device substrates have NMOS and PMOS, described
There is fleet plough groove isolation structure between NMOS and the PMOS；Grid is respectively provided in the NMOS and the PMOS, positioned at institute
State source-drain area, the positioned at the side wall of gate lateral wall and on grid the first hard mask of two side bottom of grid；
Step 02：In the first hard mask, side wall and the surface of shallow trench isolation structure of the NMOS and PMOS
Form the second hard mask；
Step 03：The described second hard mask is patterned, so as to expose the PMOS and the fleet plough groove isolation structure table
Face；
Step 04：Under the protection of the described first hard mask and the second hard mask, to the source and drain of the PMOS
Area and the fleet plough groove isolation structure carry out ion implanting；
Step 05：Under the protection of the described first hard mask and the second hard mask, to the source and drain of the PMOS
Area performs etching, to form groove on the source-drain area surface of the PMOS；
Step 06：Under the protection of the described first hard mask and the second hard mask, germanium silicon is carried out in the trench
Epitaxial growth, so as to form germanium silicon epitaxial layer.
Preferably, in the step 02, the formation of the second hard mask includes：First, in the NMOS and described
The first hard mask, side wall and the surface of shallow trench isolation structure deposited silicon nitride layer of PMOS；Then, through O2At plasma
The silicon nitride layer surface is managed, so as to form silicon oxide layer on the silicon nitride layer surface；Surface has the silicon oxide layer
The silicon nitride layer forms the second hard mask.
Preferably, the thickness of the silicon oxide layer on the silicon nitride layer surface is 0.5~2nm.
Preferably, in the step 04, during the ion implanting, used ion is silicon ion or germanium ion.
Preferably, in the step 04, during the ion implanting, used ion implantation energy is 100~500KeV.
Preferably, in the step 04, during the ion implanting, used ion implantation dosage is 1E12~1E14/
cm2。
Preferably, the thickness of the described second hard mask is 5~20nm.
Preferably, the material of the described second hard mask is silicon nitride.
Preferably, in the step 05, the process performed etching to the source-drain area of the PMOS includes：It carries out first
Then U-shaped dry etch process carries out Σ type wet-etching technologies.
Preferably, after the step 05 and before the step 06, including：To the semiconductor device substrates into
Row wet clean process, so as to remove the flute surfaces of the source-drain area surface formation because the oxidation generated during etching technics
Object.
The preparation method of germanium silicon epitaxial layer, forms in semiconductor device substrates first in the cmos device technique of the present invention
Then first hard mask and the second hard mask remove the second hard mask of PMOS area, to expose PMOS area；Then, it is right
The source-drain area of PMOS carries out ion implanting, subsequently etches source-drain area surface again and carries out germanium and silicon epitaxial growth.Plasma pair
The source-drain area surface of PMOS causes to damage, and so as to improve the etch rate on subsequent etching source-drain area surface, source-drain area surface is carved
The erosion time is then accordingly reduced, in this way, it is possible to reduce to the damage of surface of shallow trench isolation structure in etching process, avoid to shallow ridges
Recess isolating structure surface damage is too serious and exposes the surfaces of active regions of PMOS, easily exists so as to overcome in prior art
PMOS boundaries grow the defects of extra germanium silicon epitaxial layer.
Description of the drawings
Fig. 1 is the flow diagram of the preparation method of germanium silicon epitaxial layer in existing cmos device technique
Fig. 2 a-2e are each step schematic diagram of the preparation method of germanium silicon epitaxial layer in existing cmos device technique
Flows of the Fig. 3 for the preparation method of germanium silicon epitaxial layer in the cmos device technique of the preferred embodiment of the present invention
Schematic diagram
Fig. 4-9 be the present invention a preferred embodiment cmos device technique in germanium silicon epitaxial layer preparation method it is each
Preparation process schematic diagram；Wherein, Fig. 8 is the cross section structure schematic diagram in AA ' directions in Fig. 7
Specific embodiment
To make present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Below in conjunction with attached drawing 3-9 and specific embodiment to the preparation side of germanium silicon epitaxial layer in the cmos device technique of the present invention
Method is described in further detail.It should be noted that attached drawing is using very simplified form, using non-accurate ratio, and only
Conveniently, clearly to achieve the purpose that aid in illustrating the present embodiment.
In the present embodiment, referring to Fig. 3, in cmos device technique germanium silicon epitaxial layer preparation method, include the following steps：
Step 01：Referring to Fig. 4, provide semiconductor device substrate；Semiconductor device substrates have NMOS and PMOS,
There is fleet plough groove isolation structure between NMOS and PMOS；Grid is respectively provided in NMOS and PMOS, positioned at two side bottom of grid
Source-drain area, the positioned at the side wall of gate lateral wall and on grid first hard mask；
Specifically, semiconductor device substrates 200 here can be, but not limited to as silicon substrate；There is device in silicon substrate 200
Part structure has the NMOS (pull down) of SRAM device and PMOS (pull up), has shallow ridges between NMOS and PMOS
Recess isolating structure 208,208 surface of fleet plough groove isolation structure have oxidation film；Polysilicon gate is respectively provided in NMOS and PMOS
202nd, the source-drain area positioned at 202 liang of side bottoms of polysilicon gate, positioned at 202 side wall of polysilicon gate side wall 203 and be located at
The first hard mask 204 on polysilicon gate 202；First hard mask 204 is used to protect polysilicon gate 202 in subsequent etching
In the process not by etching injury, the material of the first hard mask 204 can be, but not limited to as silicon nitride.
Step 02：Referring to Fig. 5, in the first hard mask, side wall and the surface of shallow trench isolation structure shape of NMOS and PMOS
Into the second hard mask；
Specifically, the formation of the second hard mask 205 can be, but not limited to using physical vaporous deposition, the second hard mask
205 material can be the silicon nitride that silicon nitride or surface have silicon oxide layer；In this step 02, the second hard mask 205
Formation includes：First, it is deposited on the first hard mask 204 of NMOS and PMOS, side wall 203 and 208 surface of fleet plough groove isolation structure
Silicon nitride layer；Then, through O2Corona treatment silicon nitride layer surface, so as to form silicon oxide layer on silicon nitride layer surface, this
In, the thickness of the silicon oxide layer on silicon nitride layer surface is 0.5~2nm；The silicon nitride layer that surface has silicon oxide layer forms second
Hard mask 205；Second hard mask 205 is for protecting NMOS area not etched, ion implanting and outside subsequent germanium silicon
NMOS area is protected to be grown without germanium and silicon epitaxial during epitaxial growth；The thickness of second hard mask 205 can be 5~20nm.
Step 03：Referring to Fig. 6, the second hard mask of patterning, so as to expose PMOS and surface of shallow trench isolation structure；
Specifically, it can be, but not limited to pattern the second hard mask 205 using lithography and etching technique, so as to expose
Entire 208 surface of PMOS area and fleet plough groove isolation structure；PMOS source drain region is used for subsequent growth germanium silicon epitaxial layer, it is therefore desirable to
It is exposed；First hard mask protection grid is not damaged in subsequent ion implanting and etching；Shallow trench isolation
Why 208 surface of structure is also exposed, and is the limitation because of process conditions, the second of surface of shallow trench isolation structure covers firmly
Film is inevitably etched into.
Step 04：Fig. 7 and Fig. 8 are please referred to, under the protection of the first hard mask and the second hard mask, to the source-drain area of PMOS
Ion implanting is carried out with fleet plough groove isolation structure；Wherein, Fig. 8 is the cross section structure schematic diagram in AA ' directions in Fig. 7；
Specifically, when carrying out ion implanting, used ion is silicon ion or germanium ion；Used ion implanting energy
It measures as 100~500KeV, used ion implantation dosage is 1E12~1E14/cm2.It is right by the ion implanting of this step
The source-drain area of pending etching has carried out effective damage so that subsequent etching is more easy.
Step 05：Referring to Fig. 9, under the protection of the first hard mask and the second hard mask, the source-drain area of PMOS is carried out
Etching, to form groove on the source-drain area surface of PMOS；
Specifically, the source-drain area of PMOS can include U-shaped and Σ types；Therefore, the mistake performed etching to the source-drain area of PMOS
Journey includes：U-shaped dry etch process is carried out first, and Σ type wet-etching technologies are then carried out using THAM liquids.Because silicon is carved
When erosion there is crystal orientation selectivity, taper, stepped recess can be etched.
After step 05 and before step 06, including：Wet clean process is carried out to semiconductor device substrates 200,
So as to remove the flute surfaces of source-drain area surface formation because the oxide generated during etching technics.
Due to having carried out ion implantation technology in above-mentioned steps 04 so that the etching process in this step 05 be easy into
Row, makes etch period effectively shorten, so as to reduce the loss amount of the oxidation film on 208 surface of fleet plough groove isolation structure, and increases
Add the cleaning window before germanium and silicon epitaxial growth so that during subsequent germanium and silicon epitaxial growth, fleet plough groove isolation structure 208
Adjacent active area boundary will not be exposed, thus will not be in the active area boundary adjacent with fleet plough groove isolation structure 208
Grow extra germanium silicon epitaxial layer；
Step 06：Under the protection of the first hard mask and the second hard mask, germanium and silicon epitaxial growth is carried out in the trench, so as to
Form germanium silicon epitaxial layer.
Specifically, common process may be used to carry out in the technical process of germanium and silicon epitaxial growth, which is not described herein again.
In conclusion the present invention cmos device technique in germanium silicon epitaxial layer preparation method, first in semiconductor devices
The first hard mask and the second hard mask are formed on substrate, the second hard mask of PMOS area is then removed, to expose PMOS areas
Domain；Then, the source-drain area of PMOS is subjected to ion implanting, subsequently etches source-drain area surface again and carry out germanium and silicon epitaxial growth.Deng
Gas ions cause to damage to the source-drain area surface of PMOS, so as to improve the etch rate on subsequent etching source-drain area surface, source and drain
Area's surface etch time is then accordingly reduced, in this way, it is possible to reduce to the damage of surface of shallow trench isolation structure in etching process, is kept away
Exempt from too serious to surface of shallow trench isolation structure damage and expose the surfaces of active regions of PMOS, so as to overcome in prior art
Easily PMOS boundaries grow extra germanium silicon epitaxial layer the defects of.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrate only for the purposes of explanation and
, the present invention is not limited to, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection domain that the present invention is advocated should be subject to described in claims.
Claims (10)
1. the preparation method of germanium silicon epitaxial layer in a kind of cmos device technique, which is characterized in that include the following steps：
Step 01：Semiconductor device substrate is provided；The semiconductor device substrates have NMOS and PMOS, in the NMOS and
There is fleet plough groove isolation structure between the PMOS；Grid is respectively provided in the NMOS and the PMOS, positioned at the grid
The source-drain area of two side bottoms, the positioned at the side wall of gate lateral wall and on grid first hard mask；
Step 02：It is formed in the first hard mask, side wall and the surface of shallow trench isolation structure of the NMOS and PMOS
Second hard mask；
Step 03：The described second hard mask is patterned, so as to expose the PMOS and the surface of shallow trench isolation structure；
Step 04：Under the protection of the described first hard mask and the second hard mask, to the source-drain area of the PMOS and
The fleet plough groove isolation structure carries out ion implanting；
Step 05：Under the protection of the described first hard mask and the second hard mask, to the source-drain area of the PMOS into
Row etching, to form groove on the source-drain area surface of the PMOS；
Step 06：Under the protection of the described first hard mask and the second hard mask, germanium and silicon epitaxial is carried out in the trench
Growth, so as to form germanium silicon epitaxial layer.
2. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that the step
In rapid 02, the formation of the second hard mask includes：First, the first hard mask of the NMOS and PMOS, side wall and
The surface of shallow trench isolation structure deposited silicon nitride layer；Then, through O2Silicon nitride layer surface described in corona treatment, so as to
Silicon oxide layer is formed on the silicon nitride layer surface；The silicon oxide layer and the silicon nitride layer collectively form described second and cover firmly
Film.
3. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 2, which is characterized in that the nitrogen
The thickness of the silicon oxide layer of SiClx layer surface is 0.5~2nm.
4. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that the step
In rapid 04, during the ion implanting, used ion is silicon ion or germanium ion.
5. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that the step
In rapid 04, during the ion implanting, used ion implantation energy is 100~500KeV.
6. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that the step
In rapid 04, during the ion implanting, used ion implantation dosage is 1E12~1E14/cm2。
7. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that described
The thickness of two hard masks is 5~20nm.
8. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that described
The material of two hard masks is silicon nitride.
9. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that the step
In rapid 05, the process performed etching to the source-drain area of the PMOS includes：U-shaped dry etch process is carried out first, then
Carry out Σ type wet-etching technologies.
10. the preparation method of germanium silicon epitaxial layer in cmos device technique according to claim 1, which is characterized in that in institute
Step 05 is stated later and before the step 06, including：Wet clean process is carried out to the semiconductor device substrates, so as to
Remove the oxide that the flute surfaces that the source-drain area surface is formed generate due to etching technics.
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| CN110828300B (en) * | 2019-11-25 | 2022-03-18 | 上海华力集成电路制造有限公司 | Epitaxial process |
| CN114686972A (en) * | 2022-02-21 | 2022-07-01 | 上海华力集成电路制造有限公司 | Method for improving abnormal growth of epitaxial layer |
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| CN104064521A (en) * | 2014-07-03 | 2014-09-24 | 上海华力微电子有限公司 | Semiconductor technology method and semiconductor structure |
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| CN103594420A (en) * | 2012-08-17 | 2014-02-19 | 中国科学院微电子研究所 | Manufacture method for semiconductor device |
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