JP2006332603A5 - - Google Patents
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- JP2006332603A5 JP2006332603A5 JP2006102623A JP2006102623A JP2006332603A5 JP 2006332603 A5 JP2006332603 A5 JP 2006332603A5 JP 2006102623 A JP2006102623 A JP 2006102623A JP 2006102623 A JP2006102623 A JP 2006102623A JP 2006332603 A5 JP2006332603 A5 JP 2006332603A5
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- Prior art keywords
- gate electrode
- forming
- island
- shaped semiconductor
- semiconductor film
- Prior art date
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Claims (4)
前記島状の半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を電子密度が１．０×１０ １１ ｃｍ −３ 以上１．０×１０ １３ ｃｍ −３ 以下であり、かつ電子温度は０．５ｅＶ以上１．５ｅＶ以下であるプラズマにより酸化することによって、前記ゲート電極をスリミング化することを特徴とする薄膜トランジスタの作製方法。 Forming an island- shaped semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a Gate electrode on the gate insulating film,
Wherein the gate electrode surface with an electron density of 1.0 × 10 11 cm -3 or more 1.0 × 10 13 cm -3 or less, and the electron temperature is oxidized by the plasma is not more than 1.5eV or 0.5eV a Thus, the method for manufacturing a thin film transistor characterized by slimming of the gate electrode.
前記島状の半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を電子密度が１．０×１０ １１ ｃｍ −３ 以上１．０×１０ １３ ｃｍ −３ 以下であり、かつ電子温度は０．５ｅＶ以上１．５ｅＶ以下であるプラズマにより酸化することによって、前記ゲート電極をスリミング化し、
前記ゲート電極表面に形成された酸化膜を除去することを特徴とする薄膜トランジスタの作製方法。 Forming an island- shaped semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a Gate electrode on the gate insulating film,
Wherein the gate electrode surface with an electron density of 1.0 × 10 11 cm -3 or more 1.0 × 10 13 cm -3 or less, and the electron temperature is oxidized by the plasma is not more than 1.5eV or 0.5eV the result, the gate electrode and slimming of,
A method for manufacturing a thin film transistor, comprising removing an oxide film formed on a surface of the gate electrode.
前記島状の半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を電子密度が１．０×１０ １１ ｃｍ −３ 以上１．０×１０ １３ ｃｍ −３ 以下であり、かつ電子温度は０．５ｅＶ以上１．５ｅＶ以下であるプラズマにより酸化することによって、前記ゲート電極をスリミング化し、
前記島状半導体膜に前記ゲート電極をマスクとして不純物イオンをドープし、
前記ゲート電極の側面にサイドウォールを形成し、
前記島状の半導体膜に、前記ゲート電極及び前記サイドウォールをマスクとして、前記不純物イオンより高濃度の不純物イオンをドープすることを特徴とする薄膜トランジスタの作製方法。 Forming an island- shaped semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a Gate electrode on the gate insulating film,
Wherein the gate electrode surface with an electron density of 1.0 × 10 11 cm -3 or more 1.0 × 10 13 cm -3 or less, and the electron temperature is oxidized by the plasma is not more than 1.5eV or 0.5eV the result, the gate electrode and slimming of,
The gate electrode impurity ions doped as a mask on the island-shaped semiconductor film,
Forming a sidewall on the side surface of the gate electrode;
A method for manufacturing a thin film transistor, wherein the island-shaped semiconductor film is doped with a higher concentration of impurity ions than the impurity ions using the gate electrode and the sidewall as a mask.
前記島状の半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を電子密度が１．０×１０ １１ ｃｍ −３ 以上１．０×１０ １３ ｃｍ −３ 以下であり、かつ電子温度は０．５ｅＶ以上１．５ｅＶ以下であるプラズマにより酸化することによって、前記ゲート電極をスリミング化し、
前記ゲート電極表面に形成された酸化膜を除去し、
前記島状半導体膜に前記酸化膜を除去したゲート電極をマスクとして不純物イオンをドープし、
前記ゲート電極の側面にサイドウォールを形成し、
前記島状の半導体膜に、前記ゲート電極及び前記サイドウォールをマスクとして、前記不純物イオンより高濃度の不純物イオンをドープすることを特徴とする薄膜トランジスタの作製方法。 Forming an island- shaped semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a Gate electrode on the gate insulating film,
Wherein the gate electrode surface with an electron density of 1.0 × 10 11 cm -3 or more 1.0 × 10 13 cm -3 or less, and the electron temperature is oxidized by the plasma is not more than 1.5eV or 0.5eV the result, the gate electrode and slimming of,
Removing the oxide film formed on the gate electrode surface;
Doping impurity ions using the gate electrode from which the oxide film has been removed as a mask to the island-shaped semiconductor film,
Forming a sidewall on the side surface of the gate electrode;
A method for manufacturing a thin film transistor, wherein the island-shaped semiconductor film is doped with a higher concentration of impurity ions than the impurity ions using the gate electrode and the sidewall as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006102623A JP4719054B2 (en) | 2005-04-28 | 2006-04-04 | Method for manufacturing thin film transistor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005133661 | 2005-04-28 | ||
| JP2005133661 | 2005-04-28 | ||
| JP2006102623A JP4719054B2 (en) | 2005-04-28 | 2006-04-04 | Method for manufacturing thin film transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006332603A JP2006332603A (en) | 2006-12-07 |
| JP2006332603A5 true JP2006332603A5 (en) | 2009-03-12 |
| JP4719054B2 JP4719054B2 (en) | 2011-07-06 |
Family
ID=37553917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006102623A Expired - Fee Related JP4719054B2 (en) | 2005-04-28 | 2006-04-04 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4719054B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009049207A (en) * | 2007-08-20 | 2009-03-05 | Spansion Llc | Semiconductor device manufacturing method |
| CN101978480B (en) * | 2008-04-25 | 2012-05-02 | 夏普株式会社 | Multilayer wiring, semiconductor device, substrate for display and display |
| US8592879B2 (en) | 2010-09-13 | 2013-11-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR20180079503A (en) * | 2016-12-30 | 2018-07-11 | 삼성디스플레이 주식회사 | Conductive pattern and display device having the same |
| WO2018158840A1 (en) * | 2017-02-28 | 2018-09-07 | シャープ株式会社 | Method for manufacturing active matrix substrate and method for manufacturing organic el display device |
| CN110383434B (en) * | 2017-03-07 | 2023-05-02 | 夏普株式会社 | Method for manufacturing active matrix substrate, method for manufacturing organic EL display device, and active matrix substrate |
| CN107910327B (en) * | 2017-11-07 | 2024-05-14 | 长鑫存储技术有限公司 | Capacitor array structure and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112222A (en) * | 1992-09-28 | 1994-04-22 | Seiko Epson Corp | Film semiconductor device and its manufacture |
| JP4197270B2 (en) * | 1994-04-29 | 2008-12-17 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor integrated circuit |
| WO1998033362A1 (en) * | 1997-01-29 | 1998-07-30 | Tadahiro Ohmi | Plasma device |
-
2006
- 2006-04-04 JP JP2006102623A patent/JP4719054B2/en not_active Expired - Fee Related
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