CN102812431A - 用于识别与保护一组源数据的完整性的方法 - Google Patents
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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Abstract
识别与保护一组源数据的完整性的方法,该方法产生并结合识别签名与检测和纠正余部,且扩充某些数据保证方法的现有能力。
Description
技术领域
本发明涉及一种用于识别与保护一组源数据的完整性的方法,特别涉及一种用于扩展检错纠错的方法的能力以包括改进的识别与保护的方法。
背景技术
W·W·彼得森(W.W.Peterson)在1962年在《科学美国人(Scientific American)》中所说的“无误表现是每套良好的通信系统的实现目标”仍然是老生常谈。可是,在全球的商业模式中,出现根本上不同、恶意的攻击,要在任务关键和安全关键系统中:a)变更设计;b)篡改硬件;以及c)包含欺骗性软件。过去,尤其是在保护嵌入式系统内的启动固件时,传统的检错纠错(error detection and correction,EDAC)技术大致已经足够满足数据传送中指定概率的未被检出的(随机)误差阈值。然而,在现今市场内,需要对这些算法有更多的防御以处理外包的系统开发和数据传递的识别、完整性和安全性问题。检测、纠正、追踪或阻遏由网际攻击所导致的蓄意的系统和数据损毁的问题特别受到关注。彼得森在当时提及的是免受“噪声”影响的保护,但现今我们务必包括在关键的环境中免受智能攻击的保护。这些关键的环境必须被设防御以幸免于物理安全性的损失。已有冗长的技术来用于不同层面的需要。普遍而言,加密用于保护大多数关键的数据,但通过不使用加密的系统编码来进行数据保护(或篡改侦测)也有其适用需求。某些双冗余系统具有严谨的实时启动和响应要求。用于对付恶意的攻击的任何EDAC数据处理的扩展或额外的保密(security)算法仍必须达到时间上的要求。
为响应启动固件潜在的保密性缺口,某些计算装置提供保密措施以确保该启动固件来自可信任的来源。这些保密措施依赖于唯一标识相关联的启动固件的来源的数字签名。所述计算装置可对数字签字进行译码以识别所述固件,并基于所述数字签字与已知值的比较而接受或拒绝所述启动。这个方法的困难在于所述设计受到恶意的攻击时,所述已知值可以容易地被修改以与计算值匹配。其他的缺陷会是计算装置在安装后只校验固件一次或只在启动时校验固件。启动后,便假设固件不受动态地更改。这些威胁并未通过被动性保密措施得到防止。
差错控制编码的进步已允许这些进展在数字信息存储和传送上的使用无所不在。所述数字信息的例子包括电话、因特网、DVD、电子商务交易、磁盘驱动器、ISBN(国际标准图书编号)、UPC(通用产品代码)和RFID(无线射频识别)标签。
现有技术提供了差错控制编码的部分的广义抽象概念。在图1a所示现有技术的基本例子中,源数据进入EDAC编码器,并且在编码后通过信道传输或传送。在数据接收器(sink)端、在信道之后,编码数据通过EDAC译码器检查错误。其中一类系统,是使用此设计的,其在检测到错误的情况下以重试请求进行响应。在另一类系统中,错误会由译码器纠正。两类系统对可被检出的、可纠正的、不可被检出的和不可纠正的错误的数目与类别均有其限制。这些类别的EDAC系统普遍并非这样设计以提供免受网际攻击的保护,而是设计成处理随机或猝发错误,或者随机或猝发错误的某些组合。
图1b所示的现有技术通过加入加密编码和加密译码来添加数据保密。通过在所述加密之前加上压缩阶段,某些表现与数大小限制得到改善,这是所述技术领域公知的。通常这些步骤远比仅有所述EDAC阶段时间集中,使它们在某些实时嵌入式系统中因涉及的风险而并不可行。
所述技术领域有更多的例子展示前述那个基本例子和那个较复杂的例子的变化,或展示连接、交叉、冗余和反馈之间的组合。这些变化的使用给磁盘驱动器在纠错后带来的未被检出的错误的概率处于数量级10-18级别。
某些应用要求有很低的未被检出的错误的概率。就最关键的航空电子设备的应用而言,未被检出的错误的概率的要求为10-9,另要求没有单点失效,以及没有针对硬件系统的共同原因。对于相似的关键软件系统,要求要满足所谓“A级”目标而非10-9,其他的要求则依然要达到。
有人曾指出在关键航空电子软件系统的端到端生命周期中,免受网际攻击的防护等级存在潜在缺口。保护这些缺口的解决方案一直是在开发时间EDAC编码器余部的可靠性,所述余部附属于启动代码映像902,可参图7的904。
当假定在不同物理层和装置内提供强大保护,将产生在数据生命周期内数据免受较高级别而日益明显的威胁的足够的端到端保护时,额外的缓解程序便是必需的。可行的部分的解决方案同样也是在所述源处附上对数据的足够的保护、并使其在预期使用期限内保持附上,且在过程中检查该部分。如前提及,考虑到新的威胁,对关键系统而言仅依赖EDAC的保护不再足够,但一如既往,任何解决方案必需是简单的、便宜的、适当的和快捷的。
在1974年1月15日发行的美国专利3,786,439中,麦克唐纳(McDonald)介绍新颖的想法“如应用于不同的错误码一样,通过使用与数据字段内的非线性变化结合的多个独立错误码,检错得以增强”。然后指出使用非线性置换,其通过“对多个独立代码之间的跟踪错误代码关系进行加扰”。非线性的定义没有明确地说明,但后来在该讨论中它看起来是指不进行循环置换。它指示将数据集分开成若干子集,以一个ECC-3端到端覆盖所有数据,见于以下陈述:“……产生第二个非线性相关之数据字段”及“由于所述两个代码之间的非线性差异,因此提供了高度的可靠性,其中错误状况与该两个代码属相同数学子段的概率变成非常之低”。后来,讨论中指出每一多项式均具有1+x的项。在所述权利要求中,跟随所述方法会显示“少于第一和第二组错误的第三组错误,该第三组包括均不在所述第一和第二组内的错误……”。
继麦克唐纳后,在1995年2月21日发行的美国专利5,392,299中,雷内斯(Rhines)等人介绍三维正交交错误差校正系统的想法。该系统用于为正使用的信道而设的随机与突发的增强保护。所述加扰是固定的并且所述方法要求三部分的正交交织。正交的定义为进行增强免受突发错误影响的保护的「左右移动」。后来,讨论中指出在编码之前或之后使用交织过程去提供对付包含的错误的额外保护,这属于所述技术领域公知。所述交织定义为在其中连续字节互相分开的过程,以免受猝发错误影响作出保护。
在1997年9月30日发行的美国专利5,673,316中,奥尔巴赫(Auerbach)等人讨论为信息部分的聚合的加密封装的创建与分配,其中要受保护的部分中的每个部分都经加密。
在《使用移动(TWINKLE)装置对大数字进行因子分解(Factoring LargeNumbers with the TWINKLE Device)》的摘要中,阿迪沙米尔(Adi Shamir)指出“RSA公钥密码体制的保密性根据对本身为两个大小相等的素数p和q的乘积的大数字n进行因子分解的难度而定”。他也指出“对大的RSA密钥进行因子分解的当前纪录是对465位数字的因子分解……‘移动’技术可增加可分解因子的数字的大小100至200位……”及“……可令512位RSA密钥(其保护95%现今因特网上的电子商务)十分易受攻击”。
在布罗(Berrou)于1996年发表的论文中,文中指出“2)非一致性交织:明显地,例如如图5所代表的,给予最短距离的形式可通过合宜的非一致性交织‘分开’,从而将可分开的FC[有限码字——由0开始的有限距离]形式转换成不可分开的FC或非FC。”“非一致性交织必须满足两个主要条件:如一般交织中最大的数据分散、以及在交织数据序列中最大的混乱。可能与前者有矛盾的后者是要使源自所述两个编码器产生的冗余代尽可能多种多样的。”
发明内容
本发明是识别与保护一组源数据的完整性的方法。所述源数据可以以软件或传输数据的形式存在。步骤(a)和步骤(b)可以是可编程的。所述源数据也可以完全地或部分地嵌入硬件。
本发明的一个实施例可以包括以下步骤:
(a)将所述源数据通过变换以产生经变换的一组源日期;
(b)利用畸变函数使得所述经变换的一组源数据畸变以产生中间的一组源数据;以及
(c)将所述中间的一组源数据通过EDAC(检错纠错)算法以产生余部,并将该余部附加到所述一组源数据以产生经编码的一组源数据。
在一个可替换实施例中,所述方法还可以包括以下步骤,就是将所述的一组源日期通过某第二EDAC算法以产生第二余部,并将该余部附加到所述经编码的一组源数据。
就嵌入式系统的情况,举例来说通过生成计算机,可以在将所述一组源数据嵌入前先计算所述余部中的一个或两个。
EDAC算法通常将所述源数据编码并产生余部,该余部用来警惕使用者在所述源数据中存在故意的或意外的变更。已知很多EDAC算法均适用于本发明的实施。所述EDAC算法和可能用上的第二EDAC算法可以是相同或不同的。所述EDAC算法通常通过多项式除数操作。所述EDAC算法可以使用不同的多项式。从现有技术得知的EDAC算法的例子包括CRC算法、里德-所罗门(Reed-Solomon)编码、维特比(Viterbi)编码、Turbo编码、MD5算法和SHA-1散列算法。
一类简单的变换是交织器。很多种类的交织器是所述技术公知的。交织器改变所述源数据的部分的相对位置。如美国专利5,393,299所示,可选择交织以致使结果与原本的正交。此外,交织器可以简单如位2的对的交换(“2-位交替”)。根据所选的多项式而定,2-位交替可被视作仿射变换。交织器也可以在较大的数据块上以较复杂的方式操作。一种现有技术中的交织器是称为福尼(Forney)交织器的交织器。交织器可完全地或部分地在硬件内执行。举例来说,交织器可包括串行至并行数据转换器,该数据转换器的输出与纵横交错布线矩阵交织。所述交织器也可以被实施为下述串行至并行数据转换器,所指数据转换器的输出与N乘N闪存(N-by-N FLASH memory)或N乘NRAM存储器(N-by-N RAM memory)交织。所述变换也可以在软件中执行,举例来说,可通过进行使得所述源数据发生非正交变换的仿射变换来执行。其他与此同类的变换可以包括没有反函数的变换、没有保护刚体(rigid)运动的变换、或LangGanong变换或源自非公理(non-axiomatic)变换的变换。
所述畸变函数的一个例子可包括在所述经变换的一组源数据与二进模式之间的异或(exclusive OR)运算。所述二进模式可从N乘NRAM存储器抽出。
一类非公理变换可以包括所述畸变函数为所述变换的一部分。一个例子是由m个元素映射n个元素,其中m<n或m>n。在某些实施例中,所述方法也可以包括以下步骤:通过重新计算所述两个余部中的一个或两个来校验源日期的完整性,将所述余部的重新计算值与所述余部的原始值比较,将所述余部的重新计算值与所述余部的原始值比较,以及在余部的集合之间的比较显示出不同的条件下提供指示符。可周期性地或非周期性地校验所述余部。所述余部的值可以提供给显示装置、通过在串行总线上放置提供、通过在并行总线上放置提供或提供给控制逻辑。所述余部的值可以响应于请求而提供。
附图说明
图1a为展示现有技术中数字通信系统的基本组件的图。
图1b为展示现有技术中数字通信系统较全面的组件的图。
图1c为展示本发明的IDAC编码器与IDAC译码器组件的组成的图。
图1d为展示EDAC1编码器、EDAC2编码器、以及所述IDAC编码器的其他部件的图。
图2为展示某IDAC编码器的实施例中的EDAC编码器的“T”副本的图。
图3为展示EDAC1译码器、EDAC2译码器、以及所述IDAC译码器的其他部件的图。
图4为展示具有挑战性的部件的两个IDAC译码器的双冗余实施例的图。
图5a为展示IDAC编码器或IDAC译码器的公开或秘密变换部件的分解图。
图5b为展示使用福尼交织器的IDAC的变换函数部件实施例的图。
图5c为展示在“有线”交织器周围使用串行至并行转换器和并行至串行转换器的IDAC的变换函数部件的另一实施例的图。
图5d为展示使用“线”交织器的IDAC的变换函数部件的另一实施例的图。
图5e为展示使用1位堆栈的IDAC的变换函数部件的另一实施例的图。
图5f为展示使用NxN FLASH或RAM的IDAC的变换函数部件的另一实施例的图。
图5g为展示使用LangGanong变换的将IDAC的变换函数部件与畸变函数部件结合的图。
图5h为展示所述IDAC的某实施例中的非公理变换的图。
图6a为展示使用NxN FLASH或RAM的IDAC的畸变函数部件的实施例的图。
图6b为展示使用LxL FLASH或RAM、为不可逆的、非一对一的、并且非映射的(onto)IDAC的畸变函数部件的另一实施例的图。
图6c为展示使用NxN FLASH或RAM、为可更新的的IDAC的一个组合的变换函数部件与畸变函数部件的实施例的图。
图6d为展示使用NxN FLASH或RAM、为可更新的的IDAC的一个组合的变换函数部件与畸变函数部件的另一实施例的图。
图7为展示受EDAC编码器和EDAC译码器保护的双冗余嵌入式固件的端到端生命周期内的组件的图。
具体实施方式
在以下的描述与讨论中,术语“码字”包括原本的一组源数据加上相对地唯一的标签(也称数字签名或散列),该标签为多个可能的编码之一的结果,正如所属技术领域所公知,所述编码例子是例如但不限于:a)循环冗余码校验(CRC)、b)里德-所罗门、c)维特比、d)Turbo、e)低密度奇偶校验(LDPC)、f)信息-摘要算法5(MD5)及g)安全散列算法(SHA-1)。该组源数据也可以在此称为消息、数据消息或源数据。源自检错纠错算法的余部也可以在此称为残数。
本发明在使用检错纠错代码时依赖反直觉的想法。该想法是在所述数据中加 入错误,实际上加入这样多的错误使为了要超过EDAC的能力。经过对经变换的一份数据消息进行编码时加入错误,在接收端电子欺骗会被显露(或者显露先前不可被检出的或不可纠正的错误)。所述技术改善了检测电子欺骗的能力,并可在创建所述数据消息时加到该消息以作为加强的数字签名,此签名比单靠所述第一EDAC产生的难被篡改。所以所述的基本想法是如在现有技术中一样使用一个EDAC,并且然后使用第二EDAC作为标识符或数字签名,其中第二EDAC使用与第一EDAC相同的编码器(或者在硬件内或软件内的复制出的编码器)。此外,由于所述变换步骤与畸变步骤已被分开且为并行进行的,所以它们是可编程的。如前提及,所述步骤的细节可以为公开的或私人的等等。另一优点是,由于所述步骤为并行的,故此所述步骤是可升级的。以32位CRC(称为REM1)为例,通过使得所述数据消息进行变换与畸变,可得到第二个32位CRC(或REM2),而无须采用独立的多项式。通过使得所述数据进行第三次的变换与畸变,可进一步得到另一个32位CRC(称作REM3),到现时为止总共96位。对于很小的512字节的消息,畸变的可能性为24096–1,这是很大的数字。通过加入非公理变换,譬如由4096映射8192,可能性会大得多。另有许多其他潜在的优点。以下是某些实施例的细节。
如图1c所示,在一个实施例中,源数据进入识别、检测和纠正(IDAC)编码器100,并被路由到两个分离的EDAC编码器,EDAC1编码器200和EDAC2编码器300。所述EDAC1编码器可以是所属技术领域所公知的多种编码器中的任何编码器。所述数据被编码而残数被传递到所述信道,再次如所属技术领域所公知的。所述EDAC2编码器同样可以包括任何编码器,但就本实施例而言,我们会使用与EDAC1相同类型的编码。复制出的一份源数据被编码并交给部件300,而所述残数如之前一样被传递到所述信道。部件200和部件300的细节将在后面描述。同样地,后面描述的IDAC译码器500包括容后描述的EDAC1译码器600和EDAC2译码器700。
若在EDAC2300内设定存有仿射变换,那么它的EDAC功能便与美国专利3,786,439相似,但没包含使用独立代码,且经EDAC2变换的数据并非传输或传送至所述信道的数据。EDAC2并非如美国专利3,786,439一样将所述数据变换得更能抵抗突发错误,因此EDAC2系统地发送所述原本未被改变的数据。EDAC2的目的是要使其本身更能抵抗怀恶意的攻击。此外,美国专利3,786,439并不包括畸变步骤。另外还有其他几个不同之处。
如图1d所示,所述源数据在102处进入IDAC编码器100的说明性实施例。所述数据在未被改变的情况下进入消息缓冲器/fifo 104,该过程受控制与定时部件128控制或发生在由该控制与定时部件128提供的位置、同时地或顺序地通过118经EDAC2300的公开或秘密变换部件314处理、以及同时受128指引(EDAC2的部件细节以双点划线标示)。部件314使得所述数据产生本地已知变化(或本地暂时性产生,又或者通过126由128远程接收与提供),然后将所述经改变的数据传送至EDAC2300的余部产生器2部件316,作为检查/标识符。更详细的描述由下面提出的题名为数据变换的部分提供。在此时(或此序列步骤)或者使用由128提供的相同位置,EDAC1200的余部产生器1部件212累积为所属技术领域公知的检查数据(EDAC1的部件细节以点划线标示)。所有所述源数据经部件314、316、212和214处理后,通过122部件212将其检查数据发送至EDAC1200的REM1部件206,并且通过124部件316将其检查数据发送至EDAC2300的REM2部件308。源自102的未被改变的信息源数据,在所述源数据之前、所述源数据之后、某些组合或单独地在部件128的控制下通过部件104到110。所述REM1检查/标识符数据和所述REM2检查/标识符数据在部件128控制下在110与该源数据合并。刚描述的过程可在仅硬件电路和/或硬件和软件的组合(固件)中实现。若有需要,当与验证设计或检测和计数器设计合而为一时,有供安全或保密的可选择的超驰(override)去禁用所述检查130。依赖性与保密性之间的平衡可通过部件130针对每项应用而设定,即只是安全性的、只是保密性的或某些组合。
如图2所示,由于EDAC1200和EDAC2300的编码操作以并行方式进行,因此所述IDAC可以设定存有EDAC2类编码器的T副本。(EDAC T 400的部件细节以点划线标示。)也可以被设定存有译码操作的T副本。
如图3所示,再一次,所述源数据在102进入所述IDAC译码器的实施例。在这种情况下所述源数据已具有将所述检测符号与所述消息在102进行合并,产生将要通过图3的实施例重新计算、并使用本地已知的或通过128远程提供的对象进行校验的码字。第一检查符号在REM1 SRC块552移除,并且第二检查符号则在REM2SRC块554移除。所述码字的消息部分通过部件104处理。图1d与图3之间的不同之处在于,在图3中,新的一组检查符号针对部件206和308而被计算,并在部件128的控制下通过部件560比较,通过/未通过的指示或所述REM会通过558交给部件128。部件128的控制与定时过程给部件564信号以通知可纠正的完整性上的错误,以通过162对所述消息作出反馈或抵抗行动。
图4的实施例为图1d和图3的提升,其使用所述IDAC仪器及方法的两个副本800-A和800-B,并加入挑战性的部件。每个副本均能实现,作为仅双冗余硬件仪器与方法之间的交叉检验,以及作为硬件/软件组合,或者作为别的成双或更多的之变化。在这情况下,单例的、周期性或非周期性挑战以本地产生、本地接收、或者本地已知或伪随机的消息变更(仿射的、非公理的或公认的)的形式出现,在挑战出现时间之始确定。这些变更交给所述系统的另一侧832、138(或834、139),且真实的第二检查符号必须在所述出现时间终止前交给第一侧150、846、144(或166、848、140)。(若消息变换仅包含线性变换,以前冲突的欺骗可维持冲突,如早前在例子1中所见。)由于该多项式恢复问题的不可行性,在所述出现时间内所述消息受怀恶意的源欺骗的可能性不高。挑战出现时间的最短长度不为本专利之作者所知,但研究显示它可能是NP-难解(NP-完全)的计算。本专利的申请人不知道任何已知解决方案。根据论文[“作为难题的加密和解码里德-所罗门代码(Cryptography and Decoding Reed-Solomon Codes as a Hard Problem),”AggelosKiayias and Moti Yung,2005,IEEE,0-7803-9491-7],选择变得比(n*(k-1))的平方根大的位的数目,所述多项式恢复问题依然是不可解的。所以选择变得仅低于此值的位的数目看起来是指来自怀恶意的源的任何额外的位变化会导致超越所述阈值,亦因而不能被所述怀恶意的源所解决(即不能受欺骗)。换句话说,所述EDAC算法的纠正能力已远被超越。另一可能是将所述变更供作在所属技术领域上公知为不可解决的一次性密钥(pad)。
如图5所示,所述公开或秘密变换块314包括两个部件,让数据通过118进入与通过319离开的变换函数302,以及让数据通过319进入与通过115离开的畸变函数304。
图5b为所述变换函数302的一个实施例,其包括为所属技术领域公知的福尼交织器302B。
图5c为所述变换函数302的一个实施例302C,其包括为首的串行至并行转换器、接着的线交织器、再接着的并行至串行转换器,所有部件都为所属技术领域公知的。
图5d为所述变换函数302的一个实施例302D,其包括并行输入数据118、有线交织器,经变换的并行数据在319离开。
图5e为所述变换函数302的一个实施例302E,其包括每两位交替的1位堆栈314。串行输入数据在118进入,而306控制所述堆栈。307选择并控制在所述变换后来自2到1多路复用器Mux 316的数据,交给输出319。
图5f为所述变换函数302的一个实施例,其包括NxN FLASH或RAM 318。有输入118映射到输出319的一对一映射。供所述变换的FLASH项目被预先输入。所述FLASH按需要可以是可移除的。在118处的数据模式用作查寻318内的项目的地址,然后该地址的输入值在319处输出。根据所述FLASH的预设项目,这项变换可以是非公理变换的例子。就具有N=64K字节的数据消息而言,所述FLASH会是32吉字节。
图5g为所述变换函数302的实施例,其包括早前所述的LangGanong变换302G。
图5h为所述变换函数302的实施例,其包括早前所述的非公理变换302H。
图6a为所述畸变函数302的实施例352A,其包括NxN FLASH或RAM 354。有输入118映射到输出319的一对一映射。供所述畸变的FLASH项目被预先输入。所述FLASH按需要可以是可移除的。在319处的数据模式用作查寻354内的项目的地址,然后该地址的输入值在115处输出。根据所述FLASH的预设项目,这项畸变可以是非公理变换的例子的部分。就具有N=64K字节的数据消息而言,所述FLASH会是32G字节。
图6b为所述畸变函数302的一个实施例352B,其包括LxL FLASH或RAM 356。使用非公理变换时,不需要有输入118映射到输出319的一对一或映成映射。供所述畸变的FLASH项目被预先输入。所述FLASH按需要可以是可移除的。在319处的数据模式用作查寻356内的项目的地址,然后该地址的输入值在115处输出。根据所述FLASH的预设项目,这项畸变可以是非公理变换的例子的部分。就具有N=64千字节的数据消息而言,所述FLASH会是32G字节。319的某些输入线与所述FLASH未必连接(NC),某些输入线则可短接(short)在一起。115的某些输出线在358处可绑定到逻辑“1”,某些则在360处可绑定到逻辑“0”,以建立随非公理变换之后的那项畸变。
图6c为所述畸变函数302的实施例352C,其包括NxN FLASH或RAM 354。有输入118映射到输出319的一对一映射。供所述畸变的FLASH项目被预先输入。所述FLASH按需要可以是可移除的。在319处的数据模式用作查寻354内的项目的地址,然后该地址的输入值在115处输出。根据所述FLASH的预设项目,这项畸变可以是非公理变换的例子的部分。就具有N=64K字节的数据消息而言,所述FLASH会是32G字节。挑战性的数据模式通过由Mux 362选择的126进入并存储在FLASH354中。
图6d为所述畸变函数302的某实施例352D,其包括N位寄存器366及在后的N位XOR 364。319处的数据模式是与所述N位寄存器的内容异或运算的变换函数的输出。所述N位寄存器可通过126更新。若如此设定,则挑战性的数据模式通过126进入。
图7展示在嵌入式固件的生命周期中IDAC编码器和IDAC译码器的使用。在所述编译计算机902内的实施例是在存储在设定管理档案918之前附加所述编码器904的REM1和REM2数字签名(识别与EDAC)的软件实施。就不同的活动而言,例如安装、校验、测试、质量保证、存储库的存储、托管存储、输出活动、证明、重新使用、维护、开发,所述数据信息从所述档案找回并通过所述IDAC译码器906识别与校验。就双冗余安装而言,两个副本通过908安装,并同样地通过所述IDAC译码器/编码器912识别与校验。若使用可加载字段的装置、在外部端口进入、或者进行证明或检验活动,则所述数据在914识别与校验。最后,另一IDAC译码器/编码器916在将所述数据载入目标920之前识别与校验所述数据。在所述双冗余系统中,922是第一路径和装置的复制品。
本发明的操作
对数字数据的未经授权的或非故意的修改可以通过检错纠错方法检测得到,如所属技术领域所公知。与现有技术相比,本发明所实施的新的改良是增加了检测以前未被检出的变更的能力。所述设备和方法通过在接收器和发送器两者所已知和所提供的位置将所述原始消息改变,然后计算这个现为第二消息上的第二检查符号,来实现所述改良。所述第二消息无须存储以成为所述码字的部分,只有所述第二检查能被传输或传送。
数据变换(公开的或秘密的变换)
所述变换包含仿射或非公理变换。仿射变换包括线性变换和平移(translation)。较早前已定义的非公理变换包括既非一对一、也非映成的非线性变换,以及平移。仿射变换的一个例子是排列和偏移(该仿射变换的实现可能是通过移位和XOR;就并行输入数据而言,仅数据位之硬连线纵横交错和半加器;或者就串行数据而言,交换了的触发器输出),其中的结果为原本的组中的项。非公理变换的例子可以产生在原本的组以外的结果(该非公理变换可以通过插入或改变所述消息数据位之前、之中或之后的位来实现。此外,它可以通过删除或忽略所述消息的某些位,或者通过一起简略(点或(dot-OR))消息的位来实现)。硬件和/或软件又或二者可通过并行方式执行以提升性能,并且可配合不同的变换多次重复以增加强度和坚固度及减少未被检出的变更。
两个例子将用于展示所述方法的较弱和较强的应用。首先,不能检测源于电子欺骗的数字数据变化,却仍提供独特签字的所述方法较弱的应用概要如下。
例子1
为使解释与计算简明,现采用3个字节的消息来发送(使用16位CRC算法)。该信息经电子欺骗,以致它具有的残数与原本具有的相同,例如:
类别 消息 残数(CRC)
原版 0x2A301C 0xDAC2
经电子欺骗成为 0xC06454 0xDAC2(匹配)
然后切换接收端的第一位(这是所述畸变步骤,但实施时不存仿射变换)。(在数学上,所指的执行如下:
接收的原版便是 0xAA301C 0xD62E
接收的电子欺骗成为 0x406454 0xD62E(再次匹配,电子欺骗未被检出)
将切换之间的距离变成>16位又如何?切换首位和末位(相隔23位)(再一次,限于仅畸变步骤):
接收的原版便是 0xAA301D 0xC7A7
接收的电子欺骗成为 0x406455 0xC7A7(仍未被检出)
然后,在所述畸变之前加入仿射变换,在这情况下,切换每两位。
例子2
类别 消息 残数(CRC)
原版 0x2A301C 0xDAC2
经电子欺骗成为 0xC06454 0xDAC2(匹配)
接着于接收端每两位交替(仿射变换直接的选择):
接收的原版便是 0x15302C 0x2728
接收的电子欺骗成为 0xC098A8 0x3289(不匹配,电子欺骗可被检出)
下一个情况是在接收端每两位交替及切换第一位:
接收的原版便是 0x95302C 0x2BC4
接收的电子欺骗成为 0x4098A8 0x3E65(不匹配,不同检测)
仿射变换的非直接选择要求就所述系统对已知多项式的已知关系作出严密的分析,当中需要概率计算。
那么在例子1中发生什么?可通过谈论距离进行解释,但距离在不同的情况下具有不同的意思。在数轴上,两点之间的距离,譬如7和4之间,正是它们之差的绝对值(|7–4|=3)。在欧氏二维空间,两点之间的距离,譬如a=(x0,y0)和c=(x1,y1),人通常会想及就顶点为(x0,y0)、(x1,y0)、(x1,y1)的三角形使用毕氏定理。不失普遍性,是直角三角形之斜边。所以,
距离
距离的其他可能的定义是:
(*)距离
此定义(*)有点奇特的,它指所述距离定义为仅是较长一边的长度。
(**)距离
此距离的定义(**)指它仅是那两边的和,忽略平方根。
(***)距离
此定义(***)较奇特,两不同的点之间的距离总是1。
使用有限集的数字时,所述奇特情况持续。让我们选具有素元alpha(α)的域F16,α2:=α+1。
0=0000
1=0001
α=0010
α2=0100
α3=1000
α4=0011
α5=0110
α6=1100
α7=1011
α8=0101
α9=1010
α10=0111
α11=1110
α12=1111
α13=1101
α14=1001
或,
0=0*α3+0*α2+0*α1+0*α0
1=0*α3+0*α2+0*α1+1*α0
α=0*α3+0*α2+1*α1+0*α0
α2=0*α3+1*α2+0*α1+0*α0
α3=1*α3+0*α2+0*α1+0*α0
α4:=(α+1)根据定义=0*α3+0*α2+1*α1+1*α0
α5=(α4*α1)=((α+1)*α)=α2+α=0*α3+1*α2+1*α1+0*α0
α6=(α4*α2)=((α+1)*α2)=α3+α2=1*α3+1*α2+0*α1+0*α0
α7=(α4*α3)=((α+1)*α3)=α4+α3=1*α3+0*α2+1*α1+1*α0等等……
α4与α之间的“距离”是1,原因是α4=α+1,暗示了α4-α=(α+1)-α=1。或者使用所述系数位:
同样地,α8与α4之间的距离是(a2+1)-(α+1)=α2+α。
或者使用所述位:
若我们根据所述4位二进制数的数顺序重新排列上表,我们看出不同的次序和距离的情况:
0-0000
1-0001
α-0010
α4-0011
α2-0100
α8-0101
α5-0110
α10-0111
α3-1000
α14-1001
α9-1010
α7-1011
α6-1100
α13-1101
α11-1110
α12-1111
还有另一方法去看例子1的电子欺骗的检测失败。假设我们有两个消息m1和m2,两者具有相同的CRC,称作r。那么,
r1=m1(模n),就某个n,及
r1=m2(模n)。
这意味着:
所以称作r2=(m2+d)(mod n)的余部对于所述两个经修改的消息中的每个也相同。
一般来说,正交变换暗示在欧氏空间中所述变换保存共线性、距离和垂直。三维空间的旋转和平移是例子。仿射变换暗示它保存共线性,但非保存距离和垂直,然而它提供存在性和独特性。仿射变换保存线的次序。切变是非正交的仿射变换的例子。前向纠错(FEC)EDAC可与仿射变换一起使用,原因是它是无损的。仿射变换(或仿射形式(morphism))的较正式的定义是:映射T:Em→Em被称为仿射变换,条件是有可逆的m乘m矩阵A与向量从而对于所有的
Tx=Ax+b。
不可逆的变换暗示它不能是仿射的,原因是存在性标准为仿射变换的必要条件。我们如此定义非公理变换,以暗示它不保存共线性、距离或垂直;且它并不暗示存在性或独特性。非公理变换是供与自动重复请求(ARQ)EDAC一起使用、加强数字签名的用途使用或与其他信息保证方法一起使用。非公理变换提供映射S:
S:Eu→Ev。
我们定义LangGanong变换为与P线性系统矩阵的系数矩阵相乘,所指P线性系统矩阵由在特定的Zariski表面上使用LangGanong定理产生。建议具有大亏格的所述表面为首选的。就选择LangGanong变换的直接的例子而言:
假设,
z2=xy5+y(作为我们的Zariski表面),
及f=x,所以p=2,
及g(x,y)=xy5+y。
而t的程度的界限为4。我们找出ag的公式是
或者找出ag是根据LangGanong定理,
那么,
及C2=[000010000000000]。
所述变换如所属技术领域公知般进行。
交织
如距离一样,“交织”在不同情况下具有不同意思。在某些现有技术中,交织在猝发错误为普遍的那些情况下使用,以分散周围的顺序数据,致使导致不可被检出的或不可纠正的错误的猝发的可能性低。在所述磁带机EDAC专利的案子中,磁带边缘较易受影响而发生错误,因此磁带边缘的物理磁道编号从逻辑上重新排列(‘交织’),来将错误的概率分布至其他磁道。所述三维正交专利将一排一排和/或一栏一栏的数据‘交织’,同样地是为要减低猝发错误的影响。所述Turbo专利陈述了若干目的,总结如下:1)很高的纠正能力、2)高效能、3)高可靠性的译码、4)很高的位速率、5)相对地容易的编码器和译码器的制造、6)要求仅一个时钟、7)高的总编码效率、8)高性能译码器、9)在硅表面上植入所述译码方法、10)制造许多种类的译码器、11)可获利、12)简单、以及13)用于多种不同的应用。这些Turbo编码显然很好。再一次,在所述涵盖交织的Turbo专利中,其多数实施例的使用都是重新排列顺序数据,以改善译码器的纠正能力,正如人对EDAC方法所预期的一样。
我们的交织的一个目标是仅去改变数据的次序,致使所述编码导致独特的残数。就非普通大小的数据消息而言,通过不去将所述交织限定为正交的、线性的或可能可逆的,交织方式的数目得以大大提升。在非公理变换的实施例中,结果可能源自以下这样的映射(形式或关系):
S:Eu→Ev,
唯一的规则会是就某特定输入而言所述映射为可重复的。
工业应用
所述设备及方法扩充某特定EDAC系统的能力,以及提供嵌入式系统在其生命周期内免受网际攻击的经改良的防护。所述设备及方法也应用于其他数字数据的保密的递送。
一般来说,本发明通过在系统开发时与简单、扩展的签名联系去识别与确保计算机系统内启动固件可靠的执行而被改良,从而容许在系统验证和认证期间所述签名的记录与文件编制,以及容许监控与校验所述固件的生命周期的各方面,例如配置管理归档、字段加载验证、运行时间验证、通过运行健全维护系统对挑战作出响应、登录资料档案库的端口的验证、认证授权的验证与可追踪性、研发人员进行的历史跟踪、在代管档案内、以及在下一代系统中的重新使用中。可以有大量若干不同的签名通过不同的变换或畸变与输入的数字数据联系。所述处理启动固件的实施例仅供说明之用,并不暗示会限制它在启动固件的数字数据上的使用。
参考
美国专利参考:
美国专利号3,786,439 1974年1月15日 McDonald等人。
美国专利号5,392,299 1995年2月21日 Rhines等人。
美国专利号5,446,747 1995年8月29日 Berrou。
美国专利号5,673,316 1997年9月30日 Auerbach等人。
美国专利号4,821,268 1989年4月11日 Berlekamp等人。
美国专利号4,633,470 1986年12月30日 Welch等人。
美国专利号7,672,453 2010年3月2日 Matolak。
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Claims (25)
1.一种用于识别与保护一组源数据的完整性的方法,其包括以下步骤:
(a)将所述源数据通过变换以产生经变换的一组源日期;
(b)利用畸变函数使得所述经变换的一组源数据畸变以产生中间的一组源数据;以及
(c)将所述中间的一组源数据通过EDAC算法以产生余部,并将该余部附加到所述一组源数据以产生经编码的一组源数据。
2.根据权利要求1的方法,进一步包括以下步骤:将所述经编码的一组源数据通过第二EDAC算法以产生某第二余部,并将该余部附加到所述经编码的一组源数据。
3.根据权利要求1的方法,其中所述变换包括包含2-位交替的交织器。
4.根据权利要求1的方法,其中步骤(b)的畸变函数包括在所述经变换的一组源数据与二进制模式之间的异或运算。
5.根据权利要求1的方法,其中所述一组源数据是嵌入式的一组源数据。
6.根据权利要求5的方法,其中所述余部在嵌入所述一组源数据之前计算。
7.根据权利要求1的方法,其中所述变换包括包含福尼交织器的交织器。
8.根据权利要求1的方法,其中所述变换包括交织器,该交织器包含串行至并行数据转换器,该数据转换器的输出与纵横交错布线矩阵交织。
9.根据权利要求1的方法,其中所述变换包括交织器,该交织器包含串行至并行数据转换器,该数据转换器的输出与N乘N闪存交织。
10.根据权利要求1的方法,其中所述变换包括交织器,该交织器包含串行至并行数据转换器,该数据转换器的输出与N乘N RAM存储器交织。
11.根据权利要求4的方法,其中所述二进制模式是从N乘N RAM存储器抽出的。
12.根据权利要求1的方法,其中所述变换包括仿射变换。
13.根据权利要求1的方法,其中所述变换包括非公理变换。
14.根据权利要求1的方法,其中所述变换从群组中选择,该群组包含没有反函数的变换、没有保护刚体运动的变换、以及LangGanong变换矩阵。
15.根据权利要求2的方法,其中所述EDAC算法与所述第二EDAC算法相同。
16.根据权利要求2的方法,其中所述EDAC算法与所述第二EDAC算法不同。
17.根据权利要求16的方法,其中所述第一EDAC算法包括第一多项式,并且所述第二EDAC算法包括与所述第一多项式不同的某第二多项式。
18.根据权利要求1的方法,其中所述EDAC算法是从群组中选择的,该群组包含CRC算法、里德-所罗门编码、维特比编码、Turbo编码、MD5算法和SHA-1哈希算法。
19.根据权利要求5的方法,其中所述步骤(a)和(b)为可编程的。
20.根据权利要求17的方法,其中所述余部周期性地被校验。
21.根据权利要求17的方法,其中所述余部非周期性地被校验。
22.根据权利要求1的方法,进一步包括校验所述源日期的完整性的步骤,所述步骤包含重新计算所述余部、将所述余部的重新计算的值与在步骤(c)中计算出的所述余部的值比较、以及在所述比较显示所述余部与所述余部的所述重新计算的值不同时提供指示符。
23.根据权利要求22的方法,进一步包括将所述余部供给接收器的步骤。
24.根据权利要求23的方法,其中所述接收器是从群组中选择的,该群组包含显示装置、在串行总线上的布置、在并行总线上的布置和控制逻辑。
25.根据权利要求22的方法,进一步包括响应于请求而提供所述余部的步骤。
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EP2438511A4 (en) | 2013-01-09 |
EP2438511B1 (en) | 2019-07-03 |
US8769373B2 (en) | 2014-07-01 |
WO2011119137A1 (en) | 2011-09-29 |
JP2013523043A (ja) | 2013-06-13 |
EP2438511A1 (en) | 2012-04-11 |
US20130019140A1 (en) | 2013-01-17 |
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