CN102782824B - 半导体装置中的无电镍及金镀敷 - Google Patents

半导体装置中的无电镍及金镀敷 Download PDF

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CN102782824B
CN102782824B CN201080065192.4A CN201080065192A CN102782824B CN 102782824 B CN102782824 B CN 102782824B CN 201080065192 A CN201080065192 A CN 201080065192A CN 102782824 B CN102782824 B CN 102782824B
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nickel
region
gold
semiconductor device
layer
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CN102782824A (zh
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胡安·亚力杭德罗·赫布佐默
奥斯瓦尔多·洛佩斯
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Texas Instruments Inc
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Abstract

一种所描述的实例半导体装置包含在半导体衬底(210)及金属接触垫(220)的一部分上形成的钝化层(230)。使用ENIG无电镀敷工艺，将镍沉积于所述钝化层及金属接触垫上，且将金沉积于所述镍上。所述镍包含在所述镍与所述钝化层的界面(180)处及在所述镍与所述钝化层及金属接触垫的结(290)处的无多孔镍的第一无孔镍区域(层250A)。所述镍还包含在第一镍层(250A)上的多孔镍区域(层270)。金区域(层260)在多孔镍层(270)上。第二无孔镍区域(层250B)可在所述多孔镍区域与所述金区域之间。富含金的镍区域(275)可在所述多孔镍区域与所述金区域之间。对所沉积镍与所沉积金的相对厚度进行选择以防止在无电金镀敷工艺期间镍层的腐蚀到达装置层。

Description

半导体装置中的无电镍及金镀敷
技术领域
本发明涉及在制造半导体装置的过程中镍及金的无电镀敷的方法及利用此无电镀敷制造的装置。
背景技术
本发明涉及的类型的无电镀敷是用于将镍(Ni)层及金(Au)层镀敷在半导体装置的金属垫(例如，铝垫)上的方法。无电镀敷优于电解镀敷，这是因为无电镀敷的设备更廉价且此方法消耗更少的镍及金材料。
当在镀敷半导体装置的过程中使用Ni/Au无电镀敷时，发明者发现Ni与Au反应且在装置层的临界界面及接合点产生“腐蚀”区域。此腐蚀特别地影响在Ni与下部钝化氧化物(PO)层之间的接合。腐蚀可呈沿着Ni/PO界面的极多孔Ni层、孔洞及其中Ni层极富含Au的区域的形式。由于腐蚀，湿气及离子污染物可能朝向IC的有源区域迁移，且造成装置失效。
需要即使在无电镀敷工艺完成之后也能够维持装置层界面及结处的镍层的完整性。
发明内容
本发明提供用于在完成无电镀敷工艺之后维持半导体装置的层界面与结之间的机械接合的方法及结构。
实例实施例包含确定金(Au)层的厚度，然后确定在完成金镀敷工艺之后在镍/钝化层界面及在镍/钝化层/金属结处留有无孔镍层所需要的镍(Ni)的厚度。
另一实例实施例可包含下部金属垫、在镍/钝化层/金属结的结处的无孔镍层、在无孔镍层上的多孔镍层、在多孔镍上的金层，及在金层与多孔镍区域之间的富含金的镍区域。
附图说明
下面参看附图描述本发明的实例实施例实施原理，附图中：
图1是半导体装置的镍/钝化层界面附近的层的横截面图像；
图2是根据实例实施例的半导体装置的横截面图；
图3A及3B说明根据实施实施例形成半导体装置的方法。
具体实施方式
无电镍浸金(ENIG)指以浸金层覆盖以保护镍不被氧化的无电镍镀敷。此是例如用在印制电路板上的表面镀敷类型。
根据实例实施例，在完成无电镀敷工艺之后，利用无孔镍层在镍/钝化层界面及镍/钝化层/金属结处维持机械完整性。
图1描绘扫描电子显微镜(SEM)显微图，其展示实例半导体装置100中的腐蚀关系的区域。在图1中，描绘半导体装置100的部分且其包含有关于本文中的实例实施例的某些层。特定地说，装置100可包含衬底110、在衬底110上的金属垫120、在衬底110及金属垫120上的钝化层130及镍/金(Ni/Au)无电镀敷层150/160。在镍层150与钝化层130之间可见界面180，且在镍层150、钝化层130与金属垫120的结合处可见结190。
图1中描绘的腐蚀可在典型无电工艺期间由金对镍层的电化侵蚀造成。图1中可观察到三个腐蚀区域，包含：1)其中电化侵蚀(例如，在金与镍间的过度活跃的电化学反应)产生极多孔镍层的区域；2)其中镍完全溶解而产生孔洞的区域；及3)其中EDX(能量色散X射线光谱)检测到极富含金的镍层的区域。
结合本发明，曾确定在镍与钝化层130(钝化氧化物(PO))之间的接合是机械的而不是化学的。当镍变得多孔时此机械接合变弱，多孔性使得金原子扩散进镍层中且在金镀敷反应期间通过取代而替代镍原子。接近金层处镍的损耗造成镍原子朝向金层扩散且因此在下部镍层150中产生孔洞。孔洞允许外来化学试剂(比如湿气及离子污染物)渗透、穿过开口迁移，且到达集成电路的有源区域以损坏装置，并最后导致装置失效。换句话说，假如镍层/保护层界面或镍层/保护层/金属垫结处的镍层的完整性受到损害，则污染物离子可到达装置而导致金属垫的腐蚀，且假如离子到达装置的有源区域，则可导致装置泄漏。
图2说明实施本发明的原理的半导体装置200。所说明的装置200仅仅是实施方案的一个实例，且应了解可包含额外元件或一些所说明的元件可被修改或省略。
所说明的半导体装置200包含衬底210、在衬底210上形成的金属接触垫220、在衬底210及金属接触垫220的一部分上形成的钝化层230及在金属垫220与钝化层230上以ENIG工艺形成的镍250及金260的无电镀敷层。无电镀敷镍层250可包含第一无孔镍层或区域250A、多孔镍层或区域270及第二无孔镍层或区域250B。多孔镍层270夹在无孔镍层250A与250B之间。第二无孔镍层250B包含初始无电镍沉积在ENIG工艺中对金层260进行无电镀敷期间未被金层260侵蚀的那部分。
衬底210可包括此项技术中已知的硅衬底。金属接触垫220包括金属且例如可包含铜(Cu)或铝(Al)。出于说明的目的且不希望为限制性的，金属接触垫220包括铝且将被称为铝垫。钝化层230可包含此项技术中已知的钝化氧化物(PO)层。
如所描述的，镀敷镍层250可包含第一无孔镍层250A及在第一无孔镍层250A上的多孔镍层270。第一无孔镍层250A可在镍层/钝化层界面280处及在镍层/钝化层/金属接触垫结290处。由于无电镀敷镍层250的预定厚度且由于金层260的预定厚度，在无电镀敷工艺完成之后，保留下第一及第二无孔镍层250A及250B。金层260在多孔镍层250上形成，且由于无电镀敷工艺的缘故，可在金层260与多孔镍区域270间产生富含金的镍区域275。然而，第一无孔镍层250A保护钝化层230使其免受富含金的镍区域275的直接影响。将了解，虽然第一及第二无孔镍层250A、250B及多孔镍层270称为“层”，但希望这些层也可表征为无电镍250的“区域”，因为金层与镍的镀敷及相互作用本身并不一定导致将在确定层中清楚地产生的均匀性。
如图2中所描绘，无电镍层250可具有厚度以维持装置200在镍/钝化层(即，Ni/PO)界面280处及在镍/钝化层/金属接触垫(即，Ni/PO/Al)结290处的机械完整性。同样如图2中所描绘，无电镍层250可具有足以获得预定厚度的Au层260的厚度，而多孔镍层270的厚度没有到达钝化层230、金属垫220、或半导体装置200的有源表面。
图3A说明根据本发明的原理用于制作半导体装置的工艺的实例实施例的流程图300。所属领域的一般技术人员应容易明白，在图3中描绘的流程图300代表一般化示意实例流程且可添加额外步骤或所展示步骤可经修改或省略。
如图3A的框310中展示，所述工艺通过为所得结构(例如，用于引线接合与焊接)确定金层的厚度而开始。如框320中展示，所述工艺包含然后确定用于金镀敷的速率及时间以达到金层的所确定厚度。如框330展示，所述工艺包含然后确定在金镀敷步骤期间多孔镍层的前缘进展有多快。如框340展示，所述工艺通过确定防止多孔(部分，即，海绵结构Ni层)镍层到达钝化层或金属垫所需的金层下方的镍层的厚度而继续。在此确定之后，且在框350，可通过用镍层镀敷金属垫及在镍层上镀敷金层而处理半导体芯片。所述工艺在框360结束。
在所说明的方法中，无孔镍层与钝化层形成机械接合。所述方法维持所述无孔镍层与钝化层的界面处及在无孔镍层与钝化层及金属接触垫的结处的无孔镍层。如前面提到，金属接触垫可包括铝(Al)，且无电镀敷工艺可为ENIG工艺。
图3B说明利用经修改流程的实例方法，其中镍层的厚度保持在固定值且金层的厚度或镀敷速率/时间经选择使得所形成的多孔镍边缘保留在距金属垫/钝化层界面合理的距离处。
实例无电镀敷工艺及所得结构与电解镀敷相比的优势可包含成本优势及简洁性。另一优势是结构的稳定性，其中多孔镍区域接触金属(例如，Al或Cu)垫。实例实施例使得所得半导体装置在存在湿气及离子污染的情况下更稳健，因为在钝化层与无电镍及金镀敷之间的界面处的机械完整性防止湿气及离子到达装置的有源区域。
本文意图涵盖具有在实例实施例的背景下描述的特征或步骤中的一者或一者以上的不同组合的实施例，所述实例实施例具有此些特征或步骤的全部或仅其中一些。所属领域的技术人员将了解，在所主张的本发明的范围内许多其它实施例及改变也是可能的。

Claims (12)

1.一种半导体装置，其包括：
衬底；
金属接触垫，其在所述衬底上形成；
钝化层，其在所述衬底上及在所述金属接触垫的一部分上形成；及
镍及金的无电镀敷层，其在所述金属接触垫及钝化层上形成；
其中所述镍及金的无电镀敷层包含：在所述镍与所述钝化层的界面处及在所述镍与所述钝化层及金属垫的结处的无多孔镍的第一无孔镍区域；在所述第一无孔镍区域上的多孔镍区域；及在所述多孔镍区域上的金区域。
2.根据权利要求1所述的半导体装置，其中所述镍及金的无电镀敷层进一步包括在所述多孔镍区域与所述金区域之间的第二无孔镍区域。
3.根据权利要求2所述的半导体装置，其进一步包括在所述金区域与所述多孔镍区域之间的富含金的镍区域。
4.根据权利要求3所述的半导体装置，其中所述金属接触垫包括铝接触垫。
5.根据权利要求4所述的半导体装置，其中所述镍及金的无电镀敷层是通过无电镍浸金镀敷工艺沉积的层。
6.一种制造半导体装置的方法，其包括：
在衬底上形成金属接触垫；
在所述衬底上及在所述金属接触垫的一部分上形成钝化层；
在所述金属接触垫及钝化层上沉积镍；及
在所述镍上沉积金；
其中使用无电镀敷工艺沉积所述镍及金；所沉积的镍包含：在所述镍与所述钝化层的界面处及在所述镍与所述钝化层及金属垫的结处的无多孔镍的第一无孔镍区域；及在所述第一无孔镍区域上的多孔镍区域；且所沉积的金包含在所述多孔镍区域上的金区域。
7.根据权利要求6所述的制造半导体装置的方法，其中所述所沉积的镍进一步包含在所述多孔镍区域与所述金区域之间的第二无孔镍区域。
8.根据权利要求7所述的制造半导体装置的方法，其中所述所沉积的镍及所沉积的金进一步包括在所述金区域与所述多孔镍区域之间的富含金的镍区域。
9.根据权利要求8所述的制造半导体装置的方法，其中所述金属接触垫包括铝接触垫。
10.根据权利要求9所述的制造半导体装置的方法，其中所述无电镀敷工艺是无电镍浸金镀敷工艺。
11.一种在镍/金无电镀敷工艺中维持半导体装置的镍/钝化界面处的无孔镍层的方法，所述方法包括：
确定所述半导体装置的金层的厚度；
确定所述金层的无电镀敷速率及镀敷时间以达到所确定的厚度；
确定所述金层下方的镍厚度以在无电金镀敷工艺终止时维持所述镍/钝化界面处的所述无孔镍层；及
循序将所述半导体装置的所述无孔镍层及金层中的每一者无电镀敷到所述所确定的厚度。
12.根据权利要求11所述的在镍/金无电镀敷工艺中维持半导体装置的镍/钝化界面处的无孔镍层的方法，其中所述半导体装置包括在衬底上形成的金属接触垫，所述方法在所述无电金镀敷工艺完成之后在钝化层、所述无孔镍层及所述金属接触垫的结处维持无孔镍层。
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