CN102723368A - BE-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge and forming method of BE-SONOS structural device - Google Patents
BE-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge and forming method of BE-SONOS structural device Download PDFInfo
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- CN102723368A CN102723368A CN2012102044522A CN201210204452A CN102723368A CN 102723368 A CN102723368 A CN 102723368A CN 2012102044522 A CN2012102044522 A CN 2012102044522A CN 201210204452 A CN201210204452 A CN 201210204452A CN 102723368 A CN102723368 A CN 102723368A
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Abstract
The invention provides a B E-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge. A gate which is in a multiple-layered structure is disposed on the silicon substrate. The gate comprises from bottom to top, a silicon oxide layer (31), a silicon nitride layer (32) containing rich nitrogen, a silicon oxide layer (33), a silicon nitride layer (34), an oxidation resisting layer (35) and a control gate. The silicon oxide layer is contacted with the silicon substrate.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of BE-SONOS structure devices and formation method with low compiling voltage.
Background technology
Flash memory is a kind of of nonvolatile storage spare, and traditional flash memory is to utilize the floating boom of polysilicon extremely to store data, because polysilicon is a conductor, is continuous distribution so be stored in floating boom utmost point charge stored.In the time of a leakage path, whole floating boom is extremely gone up charge stored and all can be lost through this leakage path.Therefore the biggest obstacle that limits the scaled ability of flash memory is that its tunnel oxide layer thickness can not continue to reduce.Because under thin tunnel oxide situation, the leakage current that direct Tunneling and stress cause etc. all can propose great challenge to the electric leakage control of memory.The SONOS structure of latest developments; Silicon nitride layer with having the charge trap ability replaces original polysilicon stored charge layer; Because it uses the trapped charge stored charge; So charge stored is a discrete distribution, such leakage path can not cause big leakage current, so reliability improves greatly.
Typical SONOS structure is made up of silicon substrate (S)-tunnel oxide (O)-charge storage layer silicon nitride (N)-barrier oxide layer (O)-polysilicon gate (S).This structure utilizes the tunnelling of electronics to compile, and wiping of data carried out in the injection in hole.For the speed that makes compiling and wipe improves, need thin tunnel oxide (about 3nm), yet so thin thickness can reduce the hold facility of electric charge and the durability in compiling/erase process.But if adopt thicker tunnel oxide, compiling and wiping just needs bigger electric field.Big electric field when wiping can make the electronics of grid arrive the silicon nitride accumulation layer through barrier oxide layer.These injected electrons with reach dynamic balance from the substrate injected holes, cause the saturated of erase state, if bigger voltage can make and wipe and can not carry out, influence the performance of device.How in the operation of low electric field, promote the usefulness of tunnel dielectric layer, realization is a new challenge when realizing fast erasing with hold facility and endurance.
People such as Lue disclose a kind of tunnel dielectric layer of BE-SONOS structure of energy band engineering in U.S. Pat 2006/0198189A1 (" Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operation Cells and Arrays ").The technical papers about BE-SONOS that people such as Lue deliver (" BE-SONOS:A Bandgap Engineered SONOS with Excellent Performance and Reliability ". IEEE 2005; " A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory " IEEE 2007) performance of this structure is discussed.The BE-SONOS technology has been proved the usefulness that can provide, can realize erasing speed, promotes in the time of hold facility and endurance.
Hang-Ting Lue utilizes silica and silicon nitride to make up U type band structure, replaces the structure of bottom oxidization layer with the ONO layer of the thin silicon nitride of two layers of thin oxide layer folder one deck.Ultra-thin O1/N1/O2 is as a tunneling medium layer that does not have charge trap, and this is that electronics also is not able to do in time limited because catch the thickness that the mean free path of electric charge is greater than this ONO layer, has just passed this layer.N2 is the layer of stored charge, is used for storing the electric charge of injection.O3 is a barrier oxide layer, and it can prevent the injection of gate charge.Ultra-thin " O1/N1/O2 " provides one " tunneling barrier of being modulated "; This potential barrier can suppress direct Tunneling under low electric field; Tunneled holes increases the efficient of wiping to the silicon nitride layer of stored charge because the skew that can be with has efficiently under High-Field.
Summary of the invention
The present invention is directed to typical B E-SONOS structure and only pass bottom oxidization layer (O1) in order to make the hole, intermediate thin silicon nitride layer (N1) and top oxide layer must reach certain can be with skew.Making tunneled holes is not to be determined by intermediate layer (thin silicon nitride layer) potential barrier for the hole through the skew of being with of middle dielectric layer (thin silicon nitride) just.The skew of being with of upper strata oxide layer (O2) also can influence entering charge storage silicon nitride layer (N2) in hole when wiping.Reduce the operating voltage when wiping through improving middle dielectric layer, further reduce the injection of gate electron.Make the erasing speed of device, electric charge hold facility and endurance reach synchronous improvement.The middle dielectric layer that the taper band structure of accumulation layer is used for thin ONO layer.Though the ONO layer is enough thin, makes the mean free path of its thickness less than electron capture, the capture ability with regard to electronics when electronics is through this layer like this dies down.But for silicon nitride layer, still have some electronics and in compiling, caught by the trap layer of silicon nitride, these captive electronics possibly understood the reliability that influence device in compiling and the circulation of wiping.
To achieve these goals, the present invention provides a kind of BE-SONOS structure devices that low compiling voltage is caught electric charge that has, and silicon substrate is provided with the grid of sandwich construction, and said grid comprises from bottom to up:
Silicon oxide layer (31), the silicon nitride layer (32) that contains rich nitrogen, silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), said silicon oxide layer contacts with silicon substrate.
In the preferred embodiment, said silicon substrate is a P type silicon substrate among the present invention.
Silicon nitride layer (32) thickness that among the present invention in the preferred embodiment, the thickness of said silicon oxide layer (31) is 1.5nm, contain rich nitrogen is that the thickness of 2nm, silicon nitride layer (34) is that the thickness of 7nm, barrier oxide layer (35) is 9nm at the thickness of 0 ~ 3.0nm, silicon oxide layer (33).
Among the present invention in the preferred embodiment, the Si/N concentration ratio in the said silicon nitride layer (32) that contains rich nitrogen is 0.05 ~ 0.2.
Another object of the present invention is to provide a kind of method that forms above-mentioned BE-SONOS structure devices; On silicon substrate, successively prepare silicon oxide layer (31), contain silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and the control gate (36) of rich nitrogen, back etching is removed redundance formation grid.
The thickness that among the present invention in the preferred embodiment, the silicon oxide layer of formation (31) thickness is 1.5nm, contain the silicon nitride layer (32) of rich nitrogen is that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm at 0 ~ 3.0nm, silicon oxide layer (33) thickness.
Among the present invention in the preferred embodiment, the Si/N concentration ratio in the said silicon nitride layer (32) that contains rich nitrogen is 0.05 ~ 0.2.
The present invention forms the O1/rich-N/O2 layer of the silicon nitride layer with rich nitrogen through improving thin ONO layer structure in the BE-SONOS structure.Have the low charge-trapping ability of silicon nitride layer of the rich nitrogen of deep trap energy level in the thin O1/rich-N1/O2 structure, can reduce electronics catching in the compilation process in thin intermediate.Be trapped in the electronics in the tunnel layer O1/rich-N1/O2 layer through reduction, can suppress to compile with the erase state circulation in destabilizing factor, the for example drift of threshold voltage, degradation problem under the efficiency of erasing.
Description of drawings
Fig. 1 is the structural representation that low compiling attitude is caught the BE-SONOS structure devices of electric charge that has provided by the invention.
Fig. 2 be BE-SONOS device with O1/TN1/O2 layer keep charge state can be with sketch map.
Fig. 3 is the BE-SONOS device compiling attitude energy band diagram with O1/TN1/O2 layer.
Fig. 4 be have the O1/TN1/O2 layer BE-SONOS device erase state can be with sketch map.
Embodiment
The present invention provides and utilizes the low electric charge ability of catching of the rich nitrogen silicon nitride layer with deep energy level to reduce a kind of charge storage structure of catching that the BE-SONOS structure devices compiles voltage.Reduce the ability of ONO layer trapped electrons in the compilation process of BE-SONOS through the N1 layer in the ONO structure of replacing the O1/N1/O2 among original BE-SONOS with the silicon nitride layer of rich nitrogen, improve the reliability in compiling and the erase cycles.Can make simultaneously thicker that this layer of rich nitrogen do, improve the electric charge hold facility of device.
Below have BE-SONOS structure devices and the formation method that low compiling voltage catches electric charge and explain further details provided by the invention through embodiment; So that better understand the present invention creativity and innovation is provided, but embodiment does not limit protection scope of the present invention.
The process that formation has the BE-SONOS structure devices that low compiling voltage catches electric charge is following:
Preparation one layer thickness is the thin silicon oxide layer 31 (being designated as O1) of 1.5nm on P type silicon substrate 1 earlier; Preparation one layer thickness is the thin silicon nitride layer that contains rich nitrogen 32 (being designated as rich-N1) of 2.0nm on this silicon oxide layer 31 then, and the Si/N concentration in the silicon nitride layer of formation is 0.1.It is the thin silicon oxynitride layer 33 (being designated as SiON) of 2.5nm that the silicon nitride layer 32 (rich-N1) that contains rich nitrogen at this layer is then gone up another layer thickness of preparation.On silicon oxynitride layer 33, prepare the thick silicon nitride layer with charge storage 34 (being designated as N2) of one deck 7nm then; The thick barrier oxide layer 35 (being designated as O3) of thermal oxidation one deck 9nm on this layer charge storage nitration case goes up preparation polysilicon control grid 36 in barrier oxide layer (O3) at last.Through above process, prepare the stacked gate architectures of improving tunnel oxide in the BE-SONOS structure, the BE-SONOS device architecture of formation is as shown in Figure 1.
Fig. 2 be the BE-SONOS device keep charge state can be with sketch map.Because big thickness and the high potential barrier of silica makes the electronics of preservation and the hole of substrate can not pass the O1/rich-N1/O2 layer after the match low.Thereby keep stored charge hold facility preferably.
Fig. 3 is a BE-SONOS device compiling attitude energy band diagram.Have two aspects can guarantee that electronics is difficult for being caught by the silicon nitride of rich nitrogen: the mean free path of (1) electron capture is bigger than the silicon nitride layer that contains rich nitrogen 32, does not have too many electronics and is caught by silicon nitride layer 34.(2) be difficult for trapped electrons owing to contain the deep trap energy level of the silicon nitride layer 32 of rich nitrogen, captive probability descended when electronics passed through this layer silicon nitride 32.Can reduce the captive probability of electronics so contain the silicon nitride layer 32 of rich nitrogen; Electronics in the compilation process is descended by the probability of trap in the silicon nitride layer that contains rich nitrogen 32; The capture rate of its silicon nitride layer 34 is raise, improve the reliability in compiling and the erase cycles.Can make simultaneously thicker that the silicon nitride layer 32 that contains rich nitrogen does, improve the electric charge hold facility of device.
Fig. 4 be BE-SONOS device erase state can be with sketch map.When wiping, the silicon nitride layer 32 (rich-N1) that contains rich nitrogen is consistent with silicon nitride, also has enough being with skew or offsetting that the hole is passed through.Simultaneously top silica (O2) can be with the skew that also reaches certain, influence very little to the tunnelling of electronics.And owing to contain in the silicon nitride layer 32 of rich nitrogen and do not catch electric charge in the compiling attitude, it is compound at the ONO layer in erase state electronics and hole just can not take place so, influences the problem of erasing speed, has further improved the reliability of device.
Embodiment 2
Present embodiment is slightly different with embodiment 1, through regulating the thickness proportion of rich nitrogen silicon nitride and N1, is that the N1 layer of 2-t nm replaces to the silicon nitride layer that contains rich nitrogen 32 that thickness is t nm with thickness among original BE-SONOS.
Compare tangible erasing speed and be because silicon and silicon nitride interface for the potential barrier in hole (< 1.9eV) less than silicon and silicon oxide interface potential barrier (4.6eV) for the hole.Under High-Field, this is for the big potential barrier difference in hole, can under electric field, produce big can be with skew, make the hole only fast tunnelling cross the O1 layer.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (7)
1. one kind has the BE-SONOS structure devices that low compiling voltage is caught electric charge, it is characterized in that silicon substrate is provided with the grid of sandwich construction, and said grid comprises from bottom to up:
Silicon oxide layer (31), the silicon nitride layer (32) that contains rich nitrogen, silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36), said silicon oxide layer contacts with silicon substrate.
2. according to the said BE-SONOS structure devices of claim 1, said silicon substrate is a P type silicon substrate.
3. according to the said BE-SONOS structure devices of claim 1, silicon nitride layer (32) thickness that the thickness of said silicon oxide layer (31) is 1.5nm, contain rich nitrogen is that the thickness of 2nm, silicon nitride layer (34) is that the thickness of 7nm, barrier oxide layer (35) is 9nm at the thickness of 0 ~ 3.0nm, silicon oxide layer (33).
4. according to the said BE-SONOS structure devices of claim 1, the Si/N concentration ratio in the said silicon nitride layer (32) that contains rich nitrogen is 0.05 ~ 0.2.
5. one kind forms that claim 1 is said to have a method that low compiling voltage is caught the BE-SONOS structure devices of electric charge; It is characterized in that; On silicon substrate, successively prepare silicon oxide layer (31), contain silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and the control gate (36) of rich nitrogen, back etching is removed redundance formation grid.
6. according to the said method of claim 6; It is characterized in that the thickness that the silicon oxide layer of formation (31) thickness is 1.5nm, contain the silicon nitride layer (32) of rich nitrogen is that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm at 0 ~ 3.0nm, silicon oxide layer (33) thickness.
7. according to the said method of claim 6, the Si/N concentration ratio in the said silicon nitride layer (32) that contains rich nitrogen is 0.05 ~ 0.2.
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| WO2020205752A1 (en) * | 2019-03-29 | 2020-10-08 | Texas Instruments Incorporated | Process and method for achieving high immunity to ultrafast high voltage transients across inorganic galvanic isolation barriers |
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| CN1877857A (en) * | 2005-06-10 | 2006-12-13 | 旺宏电子股份有限公司 | Methods of operating P-channel non-volatile memory devices |
| US20090050953A1 (en) * | 2007-08-22 | 2009-02-26 | Macronix International Co., Ltd. | Non-volatile memory device and method for manufacturing the same |
| US7772072B2 (en) * | 2007-08-28 | 2010-08-10 | Macronix International Co., Ltd. | Method for manufacturing non-volatile memory |
| CN101079426B (en) * | 2006-05-23 | 2010-09-15 | 旺宏电子股份有限公司 | Structure and method of sub-gate AND architectures employing bandgap engineered SONOS devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1877857A (en) * | 2005-06-10 | 2006-12-13 | 旺宏电子股份有限公司 | Methods of operating P-channel non-volatile memory devices |
| CN101079426B (en) * | 2006-05-23 | 2010-09-15 | 旺宏电子股份有限公司 | Structure and method of sub-gate AND architectures employing bandgap engineered SONOS devices |
| US20090050953A1 (en) * | 2007-08-22 | 2009-02-26 | Macronix International Co., Ltd. | Non-volatile memory device and method for manufacturing the same |
| US7772072B2 (en) * | 2007-08-28 | 2010-08-10 | Macronix International Co., Ltd. | Method for manufacturing non-volatile memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020205752A1 (en) * | 2019-03-29 | 2020-10-08 | Texas Instruments Incorporated | Process and method for achieving high immunity to ultrafast high voltage transients across inorganic galvanic isolation barriers |
| US10998278B2 (en) | 2019-03-29 | 2021-05-04 | Texas Instruments Incorporated | Process and method for achieving high immunity to ultrafast high voltage transients across inorganic galvanic isolation barriers |
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