CN102610654A - Device with conical energy band silicon nitride layer SONOS (silicon oxide nitride oxide semiconductor) structure and high erasing speed - Google Patents
Device with conical energy band silicon nitride layer SONOS (silicon oxide nitride oxide semiconductor) structure and high erasing speed Download PDFInfo
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- CN102610654A CN102610654A CN2012100665260A CN201210066526A CN102610654A CN 102610654 A CN102610654 A CN 102610654A CN 2012100665260 A CN2012100665260 A CN 2012100665260A CN 201210066526 A CN201210066526 A CN 201210066526A CN 102610654 A CN102610654 A CN 102610654A
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Abstract
The invention provides a device with a conical energy band silicon nitride layer SONOS (silicon oxide nitride oxide semiconductor) structure and a high erasing speed. A grid electrode with a multilayered structure is arranged on a silicon substrate with source and drain electrodes, the grid consists of a silicon oxide layer, a thin silicon nitride layer, an oxide layer, a gradual-change silicon nitride layer, a blocking oxide layer and a control grid from bottom to top, the silicon oxide layer contacts with the silicon substrate, silicon and nitrogen contents of the gradual-change silicon nitride layer are gradually changed from a lower layer to an upper layer of the gradual-change silicon nitride layer, the nitrogen content is linearly reduced from a nitrogen-rich end to a silicon-rich end, the silicon content is linearly increased from the nitrogen-rich end to the silicon-rich end, side walls are disposed on the periphery of the grid electrode, and the source and drain electrodes are respectively disposed in the silicon substrate and positioned on two sides of the grid electrode.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to a kind of taper and can be with silicon nitride layer SONOS structure devices with high erasing speed.
Background technology
Kuo-Hong Wu is at SONOS device with tapered bandgap nitride layer, IEEE transaction on electron devices, and Vol. 52; No. 5, May 2005. Kuo-Hong Wu are among the et.al; Propose a kind of have taper can be with the SONOS structure of silicon nitride layer; Promptly recently control the silicon nitride layer Si/N content of generation, make and contain more Si element, and contain more N element near the silicon nitride of barrier oxide layer near bottom oxidization layer (tunnel oxide) silicon nitride partly through the flow velocity of control reacting gas; Si/N is than gradually changing, and its structure is shown in accompanying drawing 1.From the energy band diagram that Fig. 2 showed with gradual change silicon nitride layer SONOS structure, can find being with of silicon nitride layer because Silicon-rich is different with the energy gap of rich nitrogen silicon nitride layer, silicon nitride layer has the band structure of taper.Under best P/E operating voltage; Standard silicon nitride layer, silicon-rich silicon nitride layer and Si/N gradual change silicon nitride layer are carried out P/E speed; The electric charge hold facility, device endurance and anti-test of reading disturbance: find that the Si/N gradual change silicon nitride layer device with taper band structure has bigger threshold voltage shift and bigger memory window.Endurance through to new unit is tested, and the Si/N gradual change silicon nitride layer of finding to have the taper band structure is in P/E circulation 10
6After inferior, do not observe the degeneration of endurance yet.The electric charge hold facility of device does not improve under the room temperature; But because bigger threshold voltage shift is arranged; The utilization extrapolation is inferred; Through still also having the memory window of 1.3V after 10 years, and the device with Si/N gradual change silicon nitride layer of taper band structure has the ability of good anti-read operation disturbance.But this erasing speed of Si/N gradual change silicon nitride layer structure devices with taper band structure is slower.
Hang-Ting Lue; Szu-Yu Wang, people such as Erh-Kun Lai have proposed improving one's methods for SONOS structure erasing speed in " BE-SONOS:A Bandgap Engineered SONOS with Excellent Performance and Reliability " and " A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory ".Propose a kind of through traditional bottom oxidization layer is carried out energy band engineering, the method that its erasing speed is increased.They have made up the SONOS structure that replaces traditional bottom oxidization layer with the bottom layer of the thin silicon nitride of oxide layer folder one deck of two layers of thin.Thin O1/N1/O2 is as a tunneling medium layer that does not almost have charge trap, and this is that electronics does not also have enough time to be hunted down because catch the thickness that the mean free path of electric charge is greater than this ONO layer, has just passed this layer.N2 is the charge storage layer with high trap, and this layer can trapped electrons, is the layer of stored charge.O3 is a barrier oxide layer, and it can prevent the injection of gate charge." O1/N1/O2 " that approaches provides one " tunneling barrier of being modulated ", and this potential barrier is in the low tunnelling that can suppress electric charge after the match, and tunneled holes increases the speed of wiping to the silicon nitride layer of stored charge owing to can be with skew to have efficiently under High-Field.
Summary of the invention
The present invention is in order to solve the problem that exists in the prior art, and the present invention has the erasing speed that taper can improve taper band structure SONOS with bottom oxidization layer (tunnel oxide) in the stored charge silicon nitride layer SONOS structure through the ONO structure replacement with O1/N1/O2.This thin ONO layer is hanging down after the match owing to there is barrier layer can keep charge stored preferably; Under High-Field since thin silicon nitride layer N1 and second layer oxide layer O2 can be with skew; Make this two-layer tunnelling that does not influence the hole; Can make hole tunnelling peroxidating fast layer, thus improved original have taper can be with the erasing speed of stored charge silicon nitride layer SONOS structure devices.The energy band engineering through will storing silicon nitride layer and the energy band engineering of tunnel layer combine, and make device have erasing speed faster.
To achieve these goals; The present invention provides a kind of taper with high erasing speed can be with silicon nitride layer SONOS structure devices; Has the grid that is provided with sandwich construction on the silicon substrate of source-drain electrode; Said grid comprises from bottom to up: silicon oxide layer, thin silicon nitride layer, oxide layer, gradual change silicon nitride layer, barrier oxide layer and control gate, and said silicon oxide layer contacts with silicon substrate; The silicon nitrogen content of said gradual change silicon nitride layer gradually changes from the lower floor to the upper strata, and nitrogen content reduces to Silicon-rich end line type from rich nitrogen end, and silicone content increases to Silicon-rich end line type from rich nitrogen end; Be provided with side wall around the said grid, said source-drain electrode is located at respectively in the silicon substrate of grid both sides.
Can be with in the silicon nitride layer SONOS structure devices in the above-mentioned taper that provides, wherein said silicon substrate is a P type silicon substrate.
Can be with in the silicon nitride layer SONOS structure devices in the above-mentioned taper that provides, the rich nitrogen end of wherein said gradual change silicon nitride layer contacts with barrier oxide layer, and the Silicon-rich end of said gradual change silicon nitride layer contacts with oxide layer.
Another object of the present invention be to provide a kind of form above-mentioned taper can be with the method for silicon nitride layer SONOS structure devices; On silicon substrate, successively prepare silicon nitride layer, thin silicon nitride layer, oxide layer, gradual change silicon nitride layer, barrier oxide layer and control gate; Back etching is removed redundance, makes side wall and source-drain electrode.
Can be with in the silicon nitride layer SONOS structure devices in the above-mentioned taper that provides, wherein prepare in the said gradual change silicon nitride layer process, the SiH during deposit gradual change silicon nitride layer bottom
2Cl
2/ NH
3Gas volume than for 2.07:1, the SiH of deposit gradual change silicon nitride layer top layer
2Cl
2/ NH
3Gas volume than for 1:10.
Taper provided by the invention can be with silicon nitride layer SONOS structure devices, has the gradual change silicon nitride layer that taper can be with through improving silicon nitride layer structure in the SONOS structure, forming.The band structure of the ONO structure of thin O1/N1/O2 can be implemented under the situation that does not influence compilation speed, improves erasing speed.The deep trap energy level that is produced by the gradual change silicon nitride layer can receive the electric charge that passes through horizontal vaults from the shallow trap energy level.So not only obtain more electric charge, and these electric charges are limited in the holding time that darker trap level can increase electric charge, the reliability of device is increased.The ONO structure of this thin layer not only can improve have taper can be with the erasing speed of SONOS structure, possibly can also improve the voltage window of device compiling and erase state through the increase of erasing speed.
Description of drawings
Fig. 1 is the sketch map that has taper band gap silicon nitride layer SONOS structure devices in the prior art.
Fig. 2 be have taper band gap silicon nitride layer SONOS structure devices in the prior art can be with sketch map.
Fig. 3 is that taper provided by the invention can be with the sketch map of silicon nitride layer SONOS structure devices.
What Fig. 4 was that taper provided by the invention can be with silicon nitride layer SONOS structure devices can be with sketch map.
Fig. 5 is that taper provided by the invention can be with sketch map with what silicon nitride layer SONOS structure devices kept charge state.
What Fig. 6 was that taper provided by the invention can be with silicon nitride layer SONOS structure devices erase state can be with sketch map.
Embodiment
The present invention provides a kind of taper can be with silicon nitride layer SONOS structure devices; Has the grid that is provided with sandwich construction on the silicon substrate of source-drain electrode; Said grid comprises from bottom to up: silicon oxide layer, thin silicon nitride layer, oxide layer, gradual change silicon nitride layer, barrier oxide layer and control gate, and said silicon oxide layer contacts with silicon substrate; The silicon nitrogen content of said gradual change silicon nitride layer gradually changes from the lower floor to the upper strata, and nitrogen content reduces to Silicon-rich end line type from rich nitrogen end, and silicone content increases to Silicon-rich end line type from rich nitrogen end; Be provided with side wall around the said grid, said source-drain electrode is located at respectively in the silicon substrate of grid both sides.
Below can do further detailed explanation through embodiment with silicon nitride layer SONOS structure devices to taper provided by the invention so that better understand the content of the invention, but the embodiment content does not limit the invention protection range.
Making has the taper of high erasing speed and can be with silicon nitride layer SONOS structure devices process following:
The silicon oxide layer 25 (being designated as O1) that preparation one deck approaches on P type silicon substrate 1 earlier; The thin silicon nitride layer 26 (being designated as N1) of preparation one deck on this thin silicon oxide layer 25 is gone up the thin oxide layer 27 (being designated as O2) of another layer of preparation at this layer thin silicon nitride layer 26 (N1) then then.The silicon nitride layer 28 (being designated as N2) of preparation silicone content gradual change on the oxide layer 27 forms the silicon nitride layer end face of rich nitrogen and the silicon nitride end face of Silicon-rich respectively, the electric charge that gradual change silicon nitride layer 28 stored are thicker then.In thin ONO layer preparation, guarantee that the interface of O1 and N1 and the interfacial state at O2 and N1 interface lack as far as possible, then the silicon nitride layer of formation silicone content gradual change on this layer ONO.
Gradual change silicon nitride layer 28 can be realized Different Silicon content and nitrogen content silicon nitride layer through controlling siliceous and ratio or flow velocity nitrogenous gas.SiH during deposit gradual change silicon nitride layer bottom
2Cl
2/ NH
3Ratio be 2.07:1 to the maximum, the SiH of deposit gradual change silicon nitride layer top layer
2Cl
2/ NH
3The ratio minimum be 1:10.
On gradual change nitration case 28, prepare thicker barrier oxide layer 29 (being designated as O3) afterwards again, then preparation control gate 24 on barrier oxide layer 29.At last, etching is removed redundance, makes the side wall and the source- drain electrode 12,13 of device.
Through above process, prepare provided by the present invention have taper can be with the device of silicon nitride layer SONOS structure, wherein original bottom oxidization layer and stored charge silicon nitride layer have all utilized the SONOS structure of energy band engineering, concrete structure is as shown in Figure 3.
Fig. 4 be by taper provided by the invention can be with silicon nitride layer SONOS structure devices can be with sketch map.Can find out in the compiling attitude; The tunnelling to electronics of being with of N1 layer and O2 layer does not influence, and compile time is because the compensation that N1 layer and O2 layer can be with; The effective thickness of O1/N1/O2 and traditional bottom oxidization layer thickness equate or approximate situation under, to almost not influence of compilation speed.There is not tangible compilation speed improvement ability to be because differ less for the potential barrier (2.1eV) for electronics between the potential barrier (3.15eV) of electronics and silicon and the silicon nitride between silicon and the silica.If the effective thickness of O1/N1/O2 and traditional bottom oxidization layer thickness near the time, compilation speed is not had too much influence.
Fig. 5 is that taper provided by the invention can be with sketch map with what silicon nitride layer SONOS structure devices kept charge state.As can be seen from the figure, null field O1/N1/O2 tunnel layer can be with sketch map.Because high potential barrier and big effective thickness make the hole can not pass the O1/N1/O2 layer after the match low.
What Fig. 6 was that taper provided by the invention can be with silicon nitride layer SONOS structure devices erase state can be with sketch map.In the situation of erase process and since N1 layer and O2 layer can be with skew, the tunnelling to the hole of being with after the skew does not have barrier effect, the O1 layer is crossed in hole tunnelling apace, thereby makes the erasing speed increase.This structure compare with oxide layer tangible erasing speed improve be because silicon and silicon nitride interface for the potential barrier (1.9eV) in hole less than silicon and silicon oxide interface potential barrier (4.6eV) for the hole.Under High-Field, this is for the big potential barrier difference in hole, can produce big can be with skew, make the hole only fast a tunnelling cross the O1 layer.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. the taper with high erasing speed can be with silicon nitride layer SONOS structure devices, it is characterized in that having the grid that is provided with sandwich construction on the silicon substrate of source-drain electrode, and said grid comprises from bottom to up:
Silicon oxide layer, thin silicon nitride layer, oxide layer, gradual change silicon nitride layer, barrier oxide layer and control gate, said silicon oxide layer contacts with silicon substrate;
The silicon nitrogen content of said gradual change silicon nitride layer gradually changes from the lower floor to the upper strata, and nitrogen content reduces to Silicon-rich end line type from rich nitrogen end, and silicone content increases to Silicon-rich end line type from rich nitrogen end;
Be provided with side wall around the said grid, said source-drain electrode is located at respectively in the silicon substrate of grid both sides.
2. said taper can be with silicon nitride layer SONOS structure devices according to claim 1, and said silicon substrate is a P type silicon substrate.
3. said taper can be with silicon nitride layer SONOS structure devices according to claim 1, and the rich nitrogen end of said gradual change silicon nitride layer contacts with barrier oxide layer, and the Silicon-rich end of said gradual change silicon nitride layer contacts with oxide layer.
One kind form taper according to claim 1 can be with the method for silicon nitride layer SONOS structure devices; It is characterized in that; On silicon substrate, successively prepare silicon nitride layer, thin silicon nitride layer, oxide layer, gradual change silicon nitride layer, barrier oxide layer and control gate; Back etching is removed redundance, makes side wall and source-drain electrode.
5. according to the said method of claim 4, prepare in the said gradual change silicon nitride layer SiH during deposit gradual change silicon nitride layer bottom
2Cl
2/ NH
3Gas volume than for 2.07:1, the SiH of deposit gradual change silicon nitride layer top layer
2Cl
2/ NH
3Gas volume than for 1:10.
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| CN101471384A (en) * | 2007-12-28 | 2009-07-01 | 东部高科股份有限公司 | Nonvolatile memory device and method for manufacturing the same |
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| US20110303968A1 (en) * | 2010-04-07 | 2011-12-15 | Macronix International Co., Ltd. | Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack |
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2012
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| CN1992352A (en) * | 2005-12-27 | 2007-07-04 | 东部电子股份有限公司 | Flash memory device and method of manufacturing the same |
| CN101093858A (en) * | 2006-06-21 | 2007-12-26 | 旺宏电子股份有限公司 | Memory element |
| US20090050953A1 (en) * | 2007-08-22 | 2009-02-26 | Macronix International Co., Ltd. | Non-volatile memory device and method for manufacturing the same |
| CN101383353A (en) * | 2007-08-27 | 2009-03-11 | 旺宏电子股份有限公司 | Memory device having memory cell array and manufacturing process thereof |
| CN101471384A (en) * | 2007-12-28 | 2009-07-01 | 东部高科股份有限公司 | Nonvolatile memory device and method for manufacturing the same |
| CN101872767A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component |
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Application publication date: 20120725 |