CN102683350A - Electric charge capturing storer - Google Patents
Electric charge capturing storer Download PDFInfo
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- CN102683350A CN102683350A CN2012101170636A CN201210117063A CN102683350A CN 102683350 A CN102683350 A CN 102683350A CN 2012101170636 A CN2012101170636 A CN 2012101170636A CN 201210117063 A CN201210117063 A CN 201210117063A CN 102683350 A CN102683350 A CN 102683350A
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Abstract
The invention provides an electric charge capturing storer, comprising a substrate, a source electrode, a drain electrode, a tunneling layer, an electric charge capturing layer, a barrier layer and a plurality of grid electrodes enclosing a channel, wherein the source electrode and the drain electrode are respectively formed at two ends of the substrate, the tunneling layer formed above the substrate separates the source electrode from the drain electrode, the electric charge capturing layer, the barrier layer and the plurality of grid electrodes enclosing the channel are sequentially arranged on the tunneling layer, and the plurality of grid electrodes enclosing the channel sequentially enclose the tunneling layer, the electric charge capturing layer and the barrier layer. According to the electric charge capturing storer disclosed by the invention, the programming time and the erasing time of the storer can be shortened, the programming voltage can be reduced, and the information keeping time can be improved.
Description
Technical field
The present invention relates to the nonvolatile memory technical field, particularly a kind of multiple-grid trapped-charge memory.
Background technology
Non-volatile type memory has the advantages that still can not lose after the outage of storage data, and this specific character is applicable to contemporary mobile communication well, fields such as picture-storage and Computer Storage parts.Some non-volatile type memories also have high density, big capacity storage capability, and this has more satisfied the various application such as information processing of people's daily lifes.
Trapped-charge memory (BE-SONOS type memory) has silicon, first oxide layer, first nitration case, second oxide layer, second nitration case, the 3rd oxide layer, silicon structure; Wherein first oxide layer, first nitration case, second oxide layer are closed and are called tunnel oxide; So can equivalence think that the charge trap-type non-volatility memorizer is by one deck tunnel oxide, one deck silicon nitride layer and one deck barrier oxide layer are formed.The charge trap-type non-volatility memorizer adopts quantum FN tunnelling; Direct Tunneling; Correlation effect such as the auxiliary tunnelling of trap and hot carrier injection effect are injected into silicon nitride layer with electric charge (electronics or hole) through tunnel oxide; And captured by the charge trap in the silicon nitride layer, thereby cause the change of device cell threshold voltage, reach the effect of storage.
As shown in Figure 1; At present trapped-charge memory adopts silicon materials to make, though silicon materials can satisfy such as performances such as high-breakdown-voltage and high power capacity, along with the development of scientific and technological and experimental technique; Increasing space, silicon dioxide (SiO are being arranged aspect the material selection
2) become silicon nitride (Si
3N
4) dielectric material, making that Leakage Current reduces in the device, capacity increases; Along with development of integrated circuits, size of devices is more and more littler, because silicon materials are in the obstacle of size aspect further dwindling and the physical limitation that brings for the Standard Thin film properties; Have to make industry to consider to seek more high performance alternative material; Along with dwindling of device size, produced short-channel effect (The Short Channel Effect), this has influenced the operate as normal of semiconductor device to a certain extent; This is because after channel length is reduced to a certain degree; The depletion region of source electrode, drain electrode shared proportion in whole raceway groove increases, and the silicon face below the grid forms the required quantity of electric charge of inversion layer and reduces, thereby threshold voltage reduces.The interior depletion region of substrate increases threshold voltage along the electric charge of channel width side direction dwell portion simultaneously.When channel width was reduced to the same magnitude of depletion width, the threshold voltage increase became very significantly.The short channel device threshold voltage is very responsive to the variation of channel length
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve provides a kind of trapped-charge memory, can make the voltage when multiple-grid memory program, time of wiping shorten and can be reduced in programming, improves the information retention time.
(2) technical scheme
The present invention provides a kind of trapped-charge memory; Comprise: the multiple-grid utmost point of substrate, source electrode, drain electrode, tunnel layer, electric charge capture layer, barrier layer and encirclement raceway groove; The two ends of said substrate form source class and drain electrode; The tunnel layer that is formed on the said substrate separates said source electrode and drain electrode, on said tunnel layer, is followed successively by the multiple-grid utmost point of electric charge capture layer, barrier layer and encirclement raceway groove, and the multiple-grid utmost point of said encirclement raceway groove surrounds tunnel layer, electric charge capture layer and barrier layer successively.
Better, said grid material comprises: at least a in the composition that platinum, gold, titanium aluminide alloy, palladium, aluminium constituted, metal nitride, metal boron nitride, metal silicon nitride, metal silicide and the metal aluminum nitride.
Better; Said electric charge capture layer material comprises: tantalum oxide, titanium dioxide, barium titanate, at least a in strontium titanates, zirconium dioxide, lead zirconate titanate, hafnium oxide, aluminium oxide, yittrium oxide, lanthana, rich oxygen containing silicon oxynitride, the silicon oxynitride that is rich in nitrogen, aluminium nitride, silicon nitride, the nitride that is rich in silicon, hafnium oxide, titanium oxide, nitrogen hafnium oxide and the hafnium silicate.
Better; Said barrier material is the dielectric material of dielectric constant greater than the dielectric constant of silicon dioxide, and it comprises: the oxide of the oxide of the oxide of silicon, the oxide of hafnium, zirconium, the nitride of silicon, aluminium, nitrogen hafnium oxide compound, hafnium compound, titanium dioxide, tantalum pentoxide; Aluminium oxide; Ceria, tungstic acid, at least a in the yittrium oxide.
Better, the dielectric constant of said silicon dioxide is 3.9, and said barrier oxide layer dielectric constant is at least 7.
Better, said barrier layer is formed by the oxide of hafnium, is entrained in transition metal in the said barrier layer and is at least a in tantalum, vanadium, ruthenium and the niobium.
Better, said barrier layer is formed by the oxide of zirconium, is entrained in transition metal in the said barrier layer and is at least a in tungsten, ruthenium, molybdenum, nickel, niobium, vanadium, titanium and the zinc.
Better, said tunnel layer material comprises: at least a in alundum (Al, praseodymium sesquioxide, titanium dioxide, silicon dioxide, hafnium oxide, zirconium dioxide, silicon nitride, aluminium nitride, the hafnium nitride.
Better, said tunnel layer comprises: first oxide layer, nitration case and second oxide layer that forms successively or first nitration case, oxide layer and second nitration case.
(3) beneficial effect
Multiple-grid trapped-charge memory provided by the invention can make in multiple-grid memory program, the time shortening of wiping and can be reduced in the voltage when programming; The raising information retention time; The more important thing is; The short-channel effect that produces along with not only dwindling of device technology, the multiple-grid storage component part can well overcome this point.Simultaneously, behind the trapped-charge memory of employing multiple-grid,, well reduced the operating voltage of device because the control ability of grid strengthens.
Description of drawings
Fig. 1 is the overall structure sketch map of prior art trapped-charge memory;
Fig. 2 is the overall structure sketch map of trapped-charge memory of the present invention;
Fig. 3 is the x0y cross-sectional view of Fig. 2 trapped-charge memory;
Fig. 4 is the programming operation sketch map of trapped-charge memory of the present invention;
Fig. 5 is the erase operation sketch map of trapped-charge memory of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
Fig. 2 is the overall structure sketch map of trapped-charge memory of the present invention; Fig. 3 is the x0y cross-sectional view of Fig. 2 trapped-charge memory, as shown in Figures 2 and 3, and trapped-charge memory of the present invention; Comprise: substrate 101b, source electrode 100s, drain electrode 102d, tunnel layer 109 (are followed successively by on the direction by raceway groove to grid: first oxide layer 103; Nitration case 104, the second oxide layers 105 or first nitration case, oxide layer; Second nitration case), the multiple-grid utmost point 108g of electric charge capture layer 106, barrier layer 107 and encirclement raceway groove; The two ends of said substrate 101b form source class 100s and drain electrode 102d, and the tunnel layer 109 that is formed on the said substrate 101b separates said source electrode 100s and drain electrode 102d, on 109 layers of said tunnellings, are followed successively by electric charge capture layer 106, barrier layer 107 and surround the multiple-grid utmost point 108g of raceway groove; The multiple-grid 108g utmost point of said encirclement raceway groove surrounds tunnel layer 109, electric charge capture layer 106 and barrier layer 107 successively.
Said grid 401 materials comprise: at least a in the materials such as the composition that platinum, gold, titanium aluminide alloy, palladium, aluminium constituted, metal nitride, metal boron nitride, metal silicon nitride, metal silicide and metal aluminum nitride.
Said barrier layer 402 materials are the dielectric material of dielectric constant greater than the dielectric constant of silicon dioxide, and the dielectric constant of said silicon dioxide is 3.9, and said barrier oxide layer dielectric constant is at least 7, and it comprises: the oxide (Si of silicon
xO
y), the oxide (Hf of hafnium
xO
y), the oxide (Zr of zirconium
xO
y), the nitride (Si of silicon
xN
y), the oxide (Al of aluminium
xO
y), nitrogen hafnium silicon oxide compound (Hf
xSi
yO
zN
k), nitrogen hafnium oxide compound (Hf
xO
yN
z), hafnium compound (Hf
xAl
yO
z), titanium dioxide, tantalum pentoxide, aluminium oxide, ceria, tungstic acid, at least a in the high dielectric materials such as yittrium oxide.In addition, the oxide (Hf when said barrier layer 402 by hafnium
xO
y) form, be entrained in transition metal in the said barrier layer and be at least a in the transition metal such as tantalum, vanadium, ruthenium and niobium.If oxide (Zr when said barrier layer 402 by zirconium
xO
y) form, be entrained in transition metal in the said barrier layer and be at least a in the transition metal such as tungsten, ruthenium, molybdenum, nickel, niobium, vanadium, titanium and zinc.
Said electric charge capture layer 403 materials comprise: tantalum oxide, titanium dioxide, barium titanate, at least a in the materials such as strontium titanates, zirconium dioxide, lead zirconate titanate, hafnium oxide, aluminium oxide, yittrium oxide, lanthana, rich oxygen containing silicon oxynitride, the silicon oxynitride that is rich in nitrogen, aluminium nitride, silicon nitride, the nitride that is rich in silicon, hafnium oxide, titanium oxide, nitrogen hafnium oxide and hafnium silicate.The emphasis that industry is paid close attention to concentrates on hafnium oxide (HfO
2) and zirconium dioxide (ZrO
2), and HfO
2Or the hafnium thing become first-selection, and because of it has high-k, volatility and thermal stability have good balance and reasonably treat the advantage of gap length degree in deposition process.With HfO
2Material is compared, appropriate ZrO
2Form has better dielectric constant performance, but band gap is narrow slightly, and the problem of revealing is towards periphery arranged.But can form the such layer structure of zirconium dioxide/alundum (Al/zirconium dioxide (general name ZAZ), solve the problem of leakage.
Said tunnel layer comprises: the first oxide layer 404a, nitration case 404b and the second oxide layer 404c that form successively, said tunnel layer 404 high dielectric materials are: at least a in the materials such as alundum (Al, praseodymium sesquioxide, titanium dioxide, silicon dioxide, hafnium oxide, zirconium dioxide, silicon nitride, aluminium nitride, hafnium nitride.In addition; If comprised plural sublayer in the said tunnel layer 404; So said two above sublayers are: aluminium oxide, praseodymium sesquioxide, silicon dioxide, titanium dioxide, hafnium oxide, zirconium dioxide, silicon nitride, aluminium nitride, hafnium nitride, HfAlO, HfSiO, HfLaO, rich oxygen containing silicon oxynitride (SiON) (refractive index is about 1.5); Be rich in the silicon oxynitride (SiON) (refractive index is 1.8) of nitrogen, one in the mixed oxide of the mixed oxide of hafnium and aluminium and hafnium and titanium.
The characteristics of high dielectric constant material of the present invention: traditional SiO
2The gate dielectric layer energy gap is 8.9eV, is far longer than the 1.1eV of silicon, and at SiO
2Can be with skew with there is a comparison symmetry at the interface of Si; Thereby it stops electronics to wear the barrier height of wearing then from valence band with the hole then from conduction band all to have about 4eV; This has determined its good insulation performance property; This advantage can well be applied in the barrier oxide layer of BE-SONOS, because the too high meeting of dielectric radio makes the physical thickness of material excessive, and the problems such as climbing in the time of the photoetching degree of depth and wiring in explained hereafter, will occurring; And dielectric radio is too low, then can not embody the superiority of novel high-dielectric-coefficient grid medium.The size of high-dielectric-coefficient grid medium layer leakage current is except outside the Pass thickness of dielectric layers has, with the band structure relation of material itself very closely.Generally, dielectric constant is big more, and the energy gap of medium is more little, can be with skew also smaller between they and the Si, and the easy like this barrier height that has caused heat emission to be worn all has about 4eV, has determined his good insulation performance property.
Fig. 4 is the programming operation sketch map of trapped-charge memory of the present invention; As shown in Figure 4; Adopt channel hot electron to inject during programming, when the drain electrode 202d and the grid 208g of device cell add positive high voltage, when source class 200s and substrate 201b ground connection; The channel hot electron that produces is injected near the silicon nitride layer 206 the drain electrode 202d through tunnel oxide 209, and the threshold voltage of whole memory cell is raise.
Fig. 5 is for the erase operation sketch map of trapped-charge memory of the present invention, and is as shown in Figure 5, and wiping is to adopt the hot hole of drain terminal to inject through tunnel oxide; When the drain electrode 302d of device cell adds positive high voltage; Grid 308g adds negative high voltage, and during substrate 301b ground connection, the hot hole that band-to-band-tunneling produces will be injected near the silicon nitride layer 306 the drain electrode 302d; Neutralize the electronics that is stored in the inside, the threshold voltage of whole memory unit is descended.
Above execution mode only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (9)
1. trapped-charge memory; It is characterized in that; Comprise: the multiple-grid utmost point of substrate, source electrode, drain electrode, tunnel layer, electric charge capture layer, barrier layer and encirclement raceway groove, the two ends of said substrate form source class and drain electrode, and the tunnel layer that is formed on the said substrate separates said source electrode and drain electrode; On said tunnel layer, be followed successively by the multiple-grid utmost point of electric charge capture layer, barrier layer and encirclement raceway groove, the multiple-grid utmost point of said encirclement raceway groove surrounds tunnel layer, electric charge capture layer and barrier layer successively.
2. charge trap-type non-volatility memorizer as claimed in claim 1; It is characterized in that said grid material comprises: at least a in the composition that platinum, gold, titanium aluminide alloy, palladium, aluminium constituted, metal nitride, metal boron nitride, metal silicon nitride, metal silicide and the metal aluminum nitride.
3. charge trap-type non-volatility memorizer as claimed in claim 1; It is characterized in that; Said electric charge capture layer material comprises: tantalum oxide, titanium dioxide, barium titanate, at least a in strontium titanates, zirconium dioxide, lead zirconate titanate, hafnium oxide, aluminium oxide, yittrium oxide, lanthana, rich oxygen containing silicon oxynitride, the silicon oxynitride that is rich in nitrogen, aluminium nitride, silicon nitride, the nitride that is rich in silicon, hafnium oxide, titanium oxide, nitrogen hafnium oxide and the hafnium silicate.
4. charge trap-type non-volatility memorizer as claimed in claim 1 is characterized in that, said barrier material is the dielectric material of dielectric constant greater than the dielectric constant of silicon dioxide; It comprises: the oxide of the oxide of the oxide of silicon, the oxide of hafnium, zirconium, the nitride of silicon, aluminium, nitrogen hafnium oxide compound, hafnium compound, titanium dioxide; Tantalum pentoxide, aluminium oxide, ceria; Tungstic acid, at least a in the yittrium oxide.
5. charge trap-type non-volatility memorizer as claimed in claim 4 is characterized in that, the dielectric constant of said silicon dioxide is 3.9, and said barrier oxide layer dielectric constant is at least 7.
6. charge trap-type non-volatility memorizer as claimed in claim 4 is characterized in that said barrier layer is formed by the oxide of hafnium, is entrained in transition metal in the said barrier layer and is at least a in tantalum, vanadium, ruthenium and the niobium.
7. charge trap-type non-volatility memorizer as claimed in claim 4 is characterized in that said barrier layer is formed by the oxide of zirconium, is entrained in transition metal in the said barrier layer and is at least a in tungsten, ruthenium, molybdenum, nickel, niobium, vanadium, titanium and the zinc.
8. charge trap-type non-volatility memorizer as claimed in claim 1; It is characterized in that said tunnel layer material comprises: at least a in alundum (Al, praseodymium sesquioxide, titanium dioxide, silicon dioxide, hafnium oxide, zirconium dioxide, silicon nitride, aluminium nitride, the hafnium nitride.
9. charge trap-type non-volatility memorizer as claimed in claim 8 is characterized in that, said tunnel layer comprises: first oxide layer, nitration case and second oxide layer that forms successively or first nitration case, oxide layer and second nitration case.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107863349A (en) * | 2017-10-17 | 2018-03-30 | 安阳师范学院 | Based on HfxSi1‑xO2Charge storage device of multivariant oxide storage material and preparation method thereof |
| CN111564499A (en) * | 2020-05-20 | 2020-08-21 | 北京大学 | Low-voltage multifunctional charge-trapping type synaptic transistor and preparation method thereof |
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| CN111564499A (en) * | 2020-05-20 | 2020-08-21 | 北京大学 | Low-voltage multifunctional charge-trapping type synaptic transistor and preparation method thereof |
| CN111564499B (en) * | 2020-05-20 | 2021-03-23 | 北京大学 | Low-voltage multifunctional charge-trapping type synaptic transistor and preparation method thereof |
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Application publication date: 20120919 |