CN102832175A - Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure - Google Patents
Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure Download PDFInfo
- Publication number
- CN102832175A CN102832175A CN2012103337094A CN201210333709A CN102832175A CN 102832175 A CN102832175 A CN 102832175A CN 2012103337094 A CN2012103337094 A CN 2012103337094A CN 201210333709 A CN201210333709 A CN 201210333709A CN 102832175 A CN102832175 A CN 102832175A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- silicon nitride
- charge storage
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for improving performance of a device of an SONOS (silicon-oxide-nitride-oxide-silicon) structure. The SONOS structure comprises a substrate, a tunneling dielectric layer, a charge storage layer, a barrier dielectric layer and a conducting layer, wherein the substrate comprises a source and a drain inside, and the tunneling dielectric layer, the charge storage layer, the barrier dielectric layer and the conducting layer are arranged on the substrate from bottom to top in sequence, wherein a concave SONOS structure design is adopted and a graded silicon nitride layer is used for forming the charge storage layer. The method has the following beneficial effects: the formation of the concave SONOS structure facilitates the difference of distribution of the electric field strength in different layers, so that the compiling and erasing speeds can be increased, and the impact of the erasing saturation on the erasing speed can be inhibited; due to relatively low difference between the Young's moduli of the graded silicon nitride layer and the tunneling silicon oxide layer, the impact of stress caused by relatively high difference between the Young's moduli of the tunneling silicon oxide layer and the silicon nitride on the device can be reduced; and the trapped electrons can be redistributed by the gradual silicon nitride layer, so that the storage charges can be distributed in the charge storage layer more uniformly.
Description
Technical field
The present invention relates to the SONOS technical field of structures, be specifically related to a kind of method of the SONOS of improvement structure devices performance.
Background technology
Flash memory is a kind of of nonvolatile storage spare, and traditional flash memory utilizes floating boom extremely to store data, because polysilicon is a conductor, floating boom utmost point charge stored is a continuous distribution.In the time of a leakage path, whole floating boom is extremely gone up charge stored and all can be lost through this leakage path.Therefore the biggest obstacle that limits the scaled ability of flash memory is that its tunnel oxide layer thickness can not continue to reduce.Because under thin tunnel oxide situation, the effects such as leakage current that direct Tunneling and stress cause all can propose great challenge to the electric leakage control of memory.Widespread usage along with flash memory; SONOS structure (the Sillicon-Oxide-Nitride-Oxide-Sillicon of newly-developed; Silicon-oxygen-nitrogen-oxygen-silicon); Silicon nitride layer with having the charge trap ability replaces original polysilicon stored charge layer, because it uses the trap level stored charge, so charge stored is a discrete distribution.So just can suppress reliability to be improved greatly because electric charge is revealed through conductive channel.
As shown in Figure 1, typical SONOS structure is made up of silicon substrate 1 (S)-tunnel oxide 2 (O)-charge storage layer silicon nitride 3 (N)-barrier oxide layer 4 (O)-polysilicon gate 5 (S), in substrate, comprises source electrode 6 and drain electrode 7.The operation principle of SONOS structure is: work as compile time, add bigger voltage at gate pole, source-drain electrode and substrate ground connection because tunneling effect makes electron tunneling cross the tunnel oxide silicon layer, are stored in the trap level in the silicon nitride layer.When wiping, gate pole adds negative voltage, source-drain electrode and substrate ground connection, and the electronics reverse tunnel in the silicon nitride layer returns substrate.For the speed that makes compiling and wipe improves, need thin tunnel oxide (about 3nm), so thin then thickness can make the hold facility of electric charge and the durability in compiling/erase process reduce.But the speed of wiping is directly proportional with electric field strength, and electric field is big more, and erasing speed is fast more.Carry out that in the SONOS structure two tunnelling processes are arranged in the erase process: the one, electronics is tunneling to substrate from silicon nitride layer; The 2nd, electronics gets into the stored charge silicon nitride layer through top barrier oxidation silicon layer from grid.As shown in Figure 1; In traditional SONOS structure, owing to be arranged in parallel between each layer, compile power line when wiping through the parallel distribution of each layer; The time to catch in the charge layer quantity of electronics many wiping beginning, and the electric field of tunneling medium layer is much larger than the electric field of top medium layer; But along with the carrying out of wiping, the electronics in the charge layer of catching reduces gradually, thus the electric field in the tunneling medium layer constantly reduce and in the top medium layer electric field constantly increase, two place's electric field strength equate when wiping fully.Therefore, electron tunneling can be with the weakening and weaken of dielectric layer electric field to the tunnelling speed of substrate in the silicon nitride, and can strengthen gradually to the tunnelling in the charge storage silicon nitride layer through gate tunneling.When the speed of two tunnellings equated, the electronics in the charge storage silicon nitride layer lost and injection reaches dynamic balance, got into and wiped saturated state, made and wiped and can not proceed, and erasing speed reduces.
Summary of the invention
To the problems referred to above that present SONOS structure technology exists, the present invention provides a kind of technical scheme of the SONOS of improvement structure devices performance.
A kind of method of improving SONOS structure devices performance, said SONOS structure comprises substrate, tunneling medium layer; Charge storage layer; Block media layer and conductive layer comprise an one source pole and a drain electrode in the said substrate, said tunneling medium layer, charge storage layer, block media layer and conductive layer are arranged on the said substrate in order from bottom to top; Wherein
Adopt gradual silicon nitride layer to form said charge storage layer, said gradual silicon nitride layer is from bottom to top by the shallow energy level gradual change to silicon-rich silicon nitride of the deep energy level of rich nitrogen silicon nitride.
Preferably, improve the method for SONOS structure devices performance, wherein, adopt silicon materials to process said substrate.
Preferably, improve the method for SONOS structure devices performance, wherein, adopt silica material to process said tunneling medium layer and said block media layer.
Preferably, improve the method for SONOS structure devices performance, wherein, adopt polysilicon gate to form said conductive layer.
Preferably, improve the method for SONOS structure devices performance, wherein, the upper surface of said tunneling medium layer, said charge storage layer, said block media layer and said polysilicon gate is set to convex surface.
Preferably, improve the method for SONOS structure devices performance, wherein, the lower surface of said tunneling medium layer, said charge storage layer, said block media layer and said polysilicon gate is set to convex surface.
Beneficial effect of the present invention:
1. formation has the SONOS structure of convex surface, impels electric field strength different in the distribution of different layers, near tunnel layer stronger electric field is arranged.The speed that can improve compiling and wipe, the while can be suppressed even eliminated and wipe saturated influence to erasing speed;
2. between gradual silicon nitride layer and the tunnel oxide silicon layer more approaching Young's modulus can reduce since between tunnel oxide silicon layer and the silicon nitride since the stress that the difference of Young's modulus causes more greatly to the influence of device;
3. injected electrons can be realized in the deep trap energy level of the silicon nitride of rich nitrogen the distribution again of trapped electrons charge stored being distributed more uniformly in the stored charge layer through horizontal vaults from the shallow trap energy level of the silicon nitride of Silicon-rich in the gradual silicon nitride layer;
4. making technology and CMOS are compatible, practice thrift cost.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings:
Fig. 1 is the power line and the structural representation of typical SONOS structure;
Fig. 2 is power line and the structural representation that has the SONOS structure of convex surface and gradual silicon nitride layer among the present invention;
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is described further, but not as qualification of the present invention.
Be illustrated in figure 2 as the SONOS structure devices of processing according to the method for a kind of SONOS of improvement structure devices of the present invention performance; This SONOS structure comprises substrate 21; Tunneling medium layer 22, charge storage layer 23, block media layer 24 and conductive layer 25; Comprise an one source pole 26 and a drain electrode 27 in the substrate, tunneling medium layer, charge storage layer, block media layer and conductive layer are arranged on the substrate from bottom to top in order; Wherein substrate is made up of silicon materials, and tunneling medium layer and block media layer are made up of silica material, and charge storage layer adopts silicon nitride material to process, and conductive layer is a polysilicon gate.
In order to prevent in the erase process because gate electron tunnelling wiping of crossing that the top barrier oxide layer gets into that charge storage layer causes is saturated; Adopt convex surface SONOS structural design in the present invention; The upper and lower surfaces that is tunneling medium layer, charge storage layer, block media layer and conductive layer all is a convex surface, and the upper surface of the substrate that contacts with tunneling medium layer also is convex surface.Have in the SONOS structure of convex surface at this; Because power line is perpendicular to the dielectric layer surface distributed; So in the structure of convex surface; Power line between substrate and the grid no longer is parallel distribution as in the typical SONOS structure, but from grid perpendicular to ONO layer (block media silicon oxide layer (O), stored charge silicon nitride layer (N) and tunnelling medium silicon oxide layer (O)) and focus on substrate.As shown in Figure 2, the density of power line is represented the size of electric field strength, and such electric force lines distribution makes grid constantly increase to the electric field strength of substrate.When wiping, can make charge storage layer to the tunnelling of substrate greater than tunnelling from gate pole iunjected charge accumulation layer, thereby can suppress even eliminate and wipe saturated appearance, improve erasing speed.
But be that convex configuration obviously is not enough only with typical SONOS architecture advances and since the electronics of gate pole through the barrier oxidation silicon layer inject caused wipe saturated, thereby improve the erasing speed of wiping device.But because certain flexibility, the Young's modulus difference that silicon oxide layer and silicon nitride layer are bigger can cause producing certain stress between two-layer.And because electric field is stronger in the field intensity of bottom, compile time is because convex surface causes the electric field strength at top bigger, the top iunjected charge accumulation layer of a large amount of electronics through convex surface, and fringe region since electric field a little less than, the electronics that passes through is less.Top area has the top that more electronics accumulates in convex surface, when wiping, also has more electronics so or the top is passed in the hole.In the compiling and the circulation of wiping, a large amount of electric charges that continue cause the degeneration of tunnel oxide silicon layer through meeting from the top.The degeneration of stress and tunnel oxide silicon layer all can influence the durability and the electric charge hold facility of device, thereby causes the decline of device reliability.
As shown in Figure 2; On above-mentioned improved basis; We use gradual silicon nitride layer 23 to replace common silicon nitride layer to form charge storage layer; Gradual silicon nitride layer is meant the silicon nitride layer of silicone content gradual change, can reduce like this between the big tunnel oxide silicon layer of silicon nitride and the flexibility of Silicon-rich because the stress that big Young's modulus causes between silicon nitride and the tunnel oxide silicon.Because the interface of charge storage layer and tunneling medium layer is obvious to the influence of device; And between the barrier oxidation silicon layer at storage silicon nitride layer and top a little less than the influence of interface to device, the stress between minimizing charge storage layer and the tunneling medium layer can effectively improve the performance of device.Simultaneously gradual silicon nitride layer changes greatly the memory window because the darker energy level of silicon nitride of rich nitrogen can be stored more electric charge, utilizes the shallow trap energy level of the silicon nitride of Silicon-rich can be easier to trapped electrons.When electronics when the shallow energy level horizontal vaults of silicon-rich silicon nitride are to the silicon nitride that silicone content reduces gradually; The electronics of storage is distributed once more; It is evenly distributed in the storage silicon nitride layer, improve since the electric field that the ONO layer of convex surface causes in the injection electronics concentrations that enhancing caused at the top of tunnel oxide silicon layer deficiency at the top.
The above is merely preferred embodiment of the present invention, is not so limits claim of the present invention, so the equivalent structure that all utilizations specification of the present invention and diagramatic content are made changes, all is included in protection scope of the present invention.
Claims (6)
1. method of improving SONOS structure devices performance, said SONOS structure comprises substrate, tunneling medium layer; Charge storage layer; Block media layer and conductive layer comprise an one source pole and a drain electrode in the said substrate, said tunneling medium layer, charge storage layer, block media layer and conductive layer are arranged on the said substrate in order from bottom to top; It is characterized in that
Adopt gradual silicon nitride layer to form said charge storage layer, said gradual silicon nitride layer is from bottom to top by the shallow energy level gradual change to silicon-rich silicon nitride of the deep energy level of rich nitrogen silicon nitride.
2. the method for improving SONOS structure devices performance as claimed in claim 1 is characterized in that, adopts silicon materials to process said substrate.
3. the method for improving SONOS structure devices performance as claimed in claim 1 is characterized in that, adopts silica material to process said tunneling medium layer and said block media layer.
4. the method for improving SONOS structure devices performance as claimed in claim 1 is characterized in that, adopts polysilicon gate to form said conductive layer.
5. the method for improving SONOS structure devices performance as claimed in claim 4 is characterized in that, the upper surface of said tunneling medium layer, said charge storage layer, said block media layer and said polysilicon gate is set to convex surface.
6. the method for improving SONOS structure devices performance as claimed in claim 5 is characterized in that, the lower surface of said tunneling medium layer, said charge storage layer, said block media layer and said polysilicon gate is set to convex surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103337094A CN102832175A (en) | 2012-09-11 | 2012-09-11 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103337094A CN102832175A (en) | 2012-09-11 | 2012-09-11 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102832175A true CN102832175A (en) | 2012-12-19 |
Family
ID=47335245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103337094A Pending CN102832175A (en) | 2012-09-11 | 2012-09-11 | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102832175A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253131A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253160A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1463045A (en) * | 2002-05-29 | 2003-12-24 | 株式会社东芝 | Semiconductor device and its mfg. method |
| US20050230766A1 (en) * | 2000-10-26 | 2005-10-20 | Kazumasa Nomoto | Non-volatile semiconductor memory device and method for producing same |
| CN101636845A (en) * | 2007-05-25 | 2010-01-27 | 赛普拉斯半导体公司 | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
| CN102280387A (en) * | 2011-08-31 | 2011-12-14 | 上海宏力半导体制造有限公司 | Method for forming silicon oxide nitride oxide semiconductor (SONOS) structure and SONOS memory |
-
2012
- 2012-09-11 CN CN2012103337094A patent/CN102832175A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050230766A1 (en) * | 2000-10-26 | 2005-10-20 | Kazumasa Nomoto | Non-volatile semiconductor memory device and method for producing same |
| CN1463045A (en) * | 2002-05-29 | 2003-12-24 | 株式会社东芝 | Semiconductor device and its mfg. method |
| CN101636845A (en) * | 2007-05-25 | 2010-01-27 | 赛普拉斯半导体公司 | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
| CN102280387A (en) * | 2011-08-31 | 2011-12-14 | 上海宏力半导体制造有限公司 | Method for forming silicon oxide nitride oxide semiconductor (SONOS) structure and SONOS memory |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253131A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253160A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253160B (en) * | 2014-07-31 | 2017-07-07 | 上海华力微电子有限公司 | A kind of B4 Flash with convex surface grid structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100527425C (en) | Method and apparatus for operating nonvolatile memory cells with modified band structure | |
| CN101728394B (en) | Groove type non-volatilisation memory for multi-digit storage | |
| CN1713372A (en) | Method of identifying logical information in a programming and erasing cell by on-side reading scheme | |
| CN100423230C (en) | Method for operating a memory element,Non-volatile memory device and method producing the same | |
| CN105226065B (en) | A kind of dibit SONOS memories and its compiling, erasing and read method | |
| CN102832175A (en) | Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure | |
| CN102683398B (en) | SONOS (Silicon Oxide Nitride Oxide Semiconductor) gate structure, manufacture method, and semiconductor device | |
| CN101013703B (en) | Array structure for assisted-charge memory devices | |
| CN102709291A (en) | SONOS storage unit, operation method of SONOS and SONOS storage | |
| CN102509559B (en) | Operation method for increasing high-density storage characteristic of non-volatile flash memory | |
| CN102436849B (en) | Operation method for realizing multiple-valued/multibit storage of partial capture-type flash memory | |
| CN100470810C (en) | Memory structures for expanding a second bit operation window | |
| US7903471B2 (en) | Method for improving memory device cycling endurance by providing additional pulses | |
| CN100505317C (en) | Memory element | |
| CN104253160A (en) | B4-Flash with convexity grid electrode structure | |
| CN102610617A (en) | Multi-bit SONOS (silicon-oxide-nitride-oxide-silicon) flash memory unit, multi-bit SONOS (silicon-oxide-nitride-oxide-silicon) flash memoryarray and operation method | |
| CN102832136B (en) | A kind of dibit NROM memory and improve the method and structure of its electron injection efficiency | |
| CN102769031B (en) | A kind of SONOS structure devices with low operating voltage | |
| CN103745749A (en) | Improved differential-architecture ETOX flash storage unit | |
| CN102723368B (en) | BE-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge and forming method of BE-SONOS structural device | |
| CN102945850A (en) | Image flash memory device and operating method thereof | |
| CN102769019B (en) | A kind of method utilizing asymmetric layering potential barrier to improve SONNS structure devices reliability | |
| CN104253131A (en) | B4-Flash with convexity grid electrode structure | |
| KR100591168B1 (en) | A flash memory device for increasing an erase characteristic, and a manufacturing method thereof | |
| CN103066131B (en) | Multi-bit nonvolatile memory and method of operation thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121219 |