CN102832175A - Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure - Google Patents

Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure Download PDF

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CN102832175A
CN102832175A CN2012103337094A CN201210333709A CN102832175A CN 102832175 A CN102832175 A CN 102832175A CN 2012103337094 A CN2012103337094 A CN 2012103337094A CN 201210333709 A CN201210333709 A CN 201210333709A CN 102832175 A CN102832175 A CN 102832175A
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silicon
dielectric layer
structure
charge storage
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田志
顾经纶
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上海华力微电子有限公司
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Abstract

The invention discloses a method for improving performance of a device of an SONOS (silicon-oxide-nitride-oxide-silicon) structure. The SONOS structure comprises a substrate, a tunneling dielectric layer, a charge storage layer, a barrier dielectric layer and a conducting layer, wherein the substrate comprises a source and a drain inside, and the tunneling dielectric layer, the charge storage layer, the barrier dielectric layer and the conducting layer are arranged on the substrate from bottom to top in sequence, wherein a concave SONOS structure design is adopted and a graded silicon nitride layer is used for forming the charge storage layer. The method has the following beneficial effects: the formation of the concave SONOS structure facilitates the difference of distribution of the electric field strength in different layers, so that the compiling and erasing speeds can be increased, and the impact of the erasing saturation on the erasing speed can be inhibited; due to relatively low difference between the Young's moduli of the graded silicon nitride layer and the tunneling silicon oxide layer, the impact of stress caused by relatively high difference between the Young's moduli of the tunneling silicon oxide layer and the silicon nitride on the device can be reduced; and the trapped electrons can be redistributed by the gradual silicon nitride layer, so that the storage charges can be distributed in the charge storage layer more uniformly.

Description

一种改善SONOS结构器件性能的方法 A method for improving the performance of SONOS device structure

技术领域 FIELD

[0001] 本发明涉及SONOS结构技术领域,具体涉及一种改善SONOS结构器件性能的方法。 [0001] The present invention relates to a SONOS structure technical field, particularly relates to a method for improving the performance of SONOS device structure. 背景技术 Background technique

[0002] 闪存是非易失存储器件的一种,传统的闪存利用浮栅极来存储数据,由于多晶硅是导体,浮栅极存储的电荷是连续分布的。 [0002] Flash memory is a nonvolatile memory device, the use of conventional flash floating gate to store data, since the polycrystalline silicon is a conductor, the charge stored in the floating gate is continuously distributed. 当有一个泄漏通道的时候,整个浮栅极上存储的电荷都会通过这个泄漏通道丢失。 When there is a leakage path, the entire charge stored on the floating gate will be lost through the leakage passage. 因此限制闪存按比例缩小能力的最大障碍是其隧穿氧化层厚度不能持续减小。 Therefore the biggest obstacle to limit the ability of a flash memory is scaled down tunnel oxide thickness which can not continue to decrease. 因为在薄的隧穿氧化层情况下,直接隧穿和应力引起的泄漏电流等效应都会对存储器的漏电控制提出巨大的挑战。 Because the thin tunneling oxide layer, the stress caused by direct tunneling leakage currents and the like effect will raise the leakage great challenge control memory. 随着闪存的普遍应用,新近发展的SONOS结构(Si I Iicon-Oxide-Nitride-Oxide-Si 11 icon,娃-氧_氮-氧_ 娃),用具有电荷陷讲能力的氮化硅层取代原有的多晶硅存储电荷层,由于其用陷阱能级存储电荷,所以存储的电荷是离散分布的。 With the widespread use of flash memory, the newly developed SONOS structure (Si I Iicon-Oxide-Nitride-Oxide-Si 11 icon, baby - oxo nitrogen _ - _ oxygen Wa), with a silicon nitride layer having a charge trap ability substituted original charge storage polysilicon layer, which was due to the charge stored in the trap level, the stored charge is discretely distributed. 这样就可以抑制由于电荷通过导电通道泄露,使可靠性大大提高。 This can suppress the leakage of charge through the conductive path, and the reliability is greatly improved.

[0003] 如图I所示,典型的SONOS结构由硅衬底I (S)-隧穿氧化层2 (O)-电荷存储层氮化硅3 (N)-阻挡氧化层4 (O)-多晶硅栅极5 (S)组成,在衬底内包括源极6和漏极7。 [0003] FIG I, a typical SONOS structure of a silicon substrate I (S) - tunneling oxide layer 2 (O) - silicon nitride charge storage layer 3 (N) - a barrier oxide layer 4 (O) - polysilicon gate 5 (S) composition within the substrate including the source 6 and drain 7. SONOS结构的工作原理是:当编译时,在门极加较大的电压,源漏极和衬底接地,由于隧穿效应使电子隧穿过隧穿氧化硅层,存储在氮化硅层中的陷阱能级中。 SONOS structure is the working principle: when compiled, the larger the applied gate voltage, a drain and a source substrate is grounded, since a tunneling effect tunneling electrons tunnel through the silicon oxide layer, stored in the silicon nitride layer the trap level. 当擦除时,门极加负电压,源漏极和衬底接地,氮化硅层中的电子反向隧穿回衬底。 When erased, applying a negative gate voltage, a drain and a source substrate is grounded, the silicon nitride layer reverse tunneling electrons back substrate. 为使编译和擦除的速度提高,需要较薄的隧穿氧化层(3nm左右),然后如此薄的厚度会使电荷的保持能力和编译/擦除过程中的耐久性降低。 In order to improve the speed of programming and erasing, and the compiler need to maintain capacity thin tunneling oxide layer (about 3nm), and then make such a thin thickness of the charge / erase endurance during reduction. 但擦除的速度与电场强度成正比,电场越大,擦除速度越快。 But greater speed and is proportional to erase electric field strength electric field, the faster erase. 在SONOS结构进行擦除过程中有两个隧穿过程:一是电子从氮化硅层中隧穿到衬底;二是电子从栅极经过顶部阻挡氧化硅层进入存储电荷氮化硅层中。 SONOS structure is erased in the course of tunneling has two processes: First, tunneling of electrons from the substrate to the silicon nitride layer; two electrons from the gate through the top of the barrier layer into a silicon oxide layer, a silicon nitride charge storage . 如图I所示,在传统的SONOS结构中,由于各层之间是平行排列的,编译和擦除时的电力线是通过各层平行分布的,在擦除开始时捕获电荷层中电子的数量多,隧穿介质层的电场远大于顶部介质层的电场;但是随着擦除的进行,捕获的电荷层中的电子逐渐减少,因此隧穿介质层中的电场不断减少而顶部介质层中电场不断增加,直到完全擦除时两处电场强度相等。 As shown in FIG. I, in the conventional SONOS structure, since arranged in parallel between the layers, and the compile time of the erasing power line is distributed in parallel through the respective layers, the number of captured electrons in the charge layer at the Wipe Start more tunneling dielectric layer is much larger than the electric field top field dielectric layer; but as erasure, the charge trapping layer of electrons is gradually reduced, and therefore the tunneling electric field in the dielectric layer and the top dielectric layer decreasing electric field increasing the electric field intensity equal to two until completely erased. 因此,氮化硅中电子隧穿到衬底的隧穿速度会随介质层电场的减弱而减弱,而经栅极隧穿到电荷存储氮化硅层中的隧穿会逐渐增强。 Thus, electron tunneling to the silicon nitride substrate with reduced speed tunneling dielectric layer an electric field is weakened, and the gate tunnel through the silicon nitride layer to the charge storage tunneling will gradually increase. 当两个隧穿的速度相等时,电荷存储氮化硅层中的电子失去和注入达到动态的平衡,进入擦除饱和的状态,使擦除不能继续进行,擦除速度降低。 When the two speeds are equal tunneling, charge storage loss of the silicon nitride layer and an electron injection to achieve dynamic balance, entering the erase saturation state, so that erasing can not continue to reduce erase speed.

发明内容 SUMMARY

[0004] 针对目前SONOS结构技术存在的上述问题,本发明提供一种改善SONOS结构器件性能的技术方案。 [0004] The above problems SONOS structure existing techniques, the present invention provides an improved device performance aspect SONOS structure.

[0005] 一种改善SONOS结构器件性能的方法,所述SONOS结构包括衬底,隧穿介质层,电荷存储层,阻挡介质层和导电层,所述衬底内包括一源极和一漏极,所述隧穿介质层、电荷存储层、阻挡介质层和导电层按顺序自下而上设置在所述衬底上,其中, Method [0005] A method of improving the performance of SONOS device structure, the SONOS structure including a substrate, a tunneling dielectric layer, a charge storage layer, the blocking dielectric layer and a conductive layer, which comprises a source and a drain in the substrate , the tunneling dielectric layer, a charge storage layer, the blocking dielectric layer and a conductive layer disposed in this order from bottom to top on the substrate, wherein

采用缓变的氮化硅层组成所述电荷存储层,所述缓变的氮化硅层自下而上由富氮氮化硅的深能级向富硅氮化硅的浅能级渐变。 A silicon nitride layer using a graded composition of the charge storage layer, the graded layer of silicon nitride to silicon-rich bottom up by the deep level of the nitrogen-rich silicon nitride shallow level gradient.

[0006] 优选地,改善SONOS结构器件性能的方法,其中,采用硅材料制成所述衬底。 [0006] Preferably, the method for improving the performance SONOS device structure, wherein the substrate is made of silicon.

[0007] 优选地,改善SONOS结构器件性能的方法,其中,采用氧化硅材料制成所述隧穿介质层和所述阻挡介质层。 [0007] Preferably, the method for improving device performance SONOS structure, wherein a silicon oxide dielectric material of the tunneling barrier layer and the dielectric layer.

[0008] 优选地,改善SONOS结构器件性能的方法,其中,采用多晶硅栅极组成所述导电层。 [0008] Preferably, the method for improving device performance SONOS structure, wherein a polysilicon gate using the composition of the conductive layer.

[0009] 优选地,改善SONOS结构器件性能的方法,其中,将所述隧穿介质层、所述电荷存储层、所述阻挡介质层和所述多晶硅栅极的上表面设置为凸面。 [0009] Preferably, to improve the performance of the structure of the SONOS device, wherein, the tunnel dielectric layer, the charge storage layer, said barrier dielectric layer and the polysilicon gate electrode is provided on a convex surface.

[0010] 优选地,改善SONOS结构器件性能的方法,其中,将所述隧穿介质层、所述电荷存储层、所述阻挡介质层和所述多晶硅栅极的下表面设置为凸面。 [0010] Preferably, to improve the performance of the structure of the SONOS device, wherein, the tunnel dielectric layer, the charge storage layer, said barrier dielectric layer and the lower surface of the polysilicon gate is set to a convex surface.

[0011] 本发明的有益效果: [0011] Advantageous effects of the invention:

1.形成具有凸面的SONOS结构,促使电场强度在不同层的分布不同,靠近隧穿层有较强的电场。 1. SONOS structure is formed having a convex surface, to promote the electric field intensity distribution in different layers of different near the tunneling layer has a stronger electric field. 可以提高编译和擦除的速度,同时可以抑制甚至消除擦除饱和对擦除速度的影响; You can improve the programming and erasing speed, and can inhibit or even eliminate erase saturation on erasing speed;

2.缓变氮化硅层与隧穿氧化硅层之间较接近的杨氏模量可以减少由于隧穿氧化硅层与氮化硅之间由于杨氏模量的差别较大引起的应力对器件的影响; 2. graded Young's modulus of the silicon nitride layer closer to the tunneling between the silicon oxide layer may reduce the stress on the tunneling oxide layer between the silicon and the silicon nitride due to the large difference in Young's modulus caused by affect device;

3.缓变的氮化硅层中注入的电子通过从富硅的氮化硅的浅陷阱能级中水平跳跃到富氮的氮化硅的深陷阱能级中可以实现捕获电子的再分布,使存储的电荷在存储电荷层中更加均匀的分布; 3. graded electrons injected into the silicon nitride layer can be achieved by jumping from the shallow trap levels in the silicon-rich silicon nitride to silicon nitrogen-rich level of the deep trap level of electrons captured redistribution, the accumulated charge in a more uniform distribution of the charge storage layer;

4.制程工艺和CMOS兼容,节约成本。 4. CMOS process technology compatibility and cost savings.

附图说明 BRIEF DESCRIPTION

[0012] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图: [0012] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments the drawings are only some embodiments of the present invention, those of ordinary skill in the art is concerned, without any creative effort, and can obtain other drawings based on these drawings:

图I是典型SONOS结构的电力线及结构示意图; Figure I is a power line and typical structural diagram of a SONOS structure;

图2是本发明中具有凸面和缓变氮化硅层的SONOS结构的电力线及结构示意图;具体实施方式 FIG 2 is a structural diagram of a power line and the SONOS structure of the present invention having a convex surface of the silicon nitride layer and ramping; DETAILED DESCRIPTION

[0013] 下面结合附图和具体实施例对本发明作进一步说明,但不作为本发明的限定。 [0013] The following Examples and specific embodiments of the present invention will be further described in conjunction with the accompanying drawings, are not limitative of the present invention.

[0014] 如图2所示为依本发明一种改善SONOS结构器件性能的方法制成的SONOS结构器件,该SONOS结构包括衬底21,隧穿介质层22,电荷存储层23,阻挡介质层24和导电层25,衬底内包括一源极26和一漏极27,隧穿介质层、电荷存储层、阻挡介质层和导电层按顺序自下而上设置在衬底上;其中衬底由硅材料构成,隧穿介质层和阻挡介质层由氧化硅材料构成,电荷存储层采用氮化硅材料制成,导电层是多晶硅栅极。 [0014] SONOS structure of the device under this invention is a method for improving the performance of SONOS device structure shown in FIG. 2 formed, the SONOS structure comprises a substrate 21, a tunnel dielectric layer 22, the charge storage layer 23, the barrier dielectric layer 24 and conductive layer 25, the substrate 26 includes a source 27 and a drain electrode, the tunneling dielectric layer, a charge storage layer, the blocking dielectric layer and a conductive layer are sequentially disposed from bottom to top on the substrate; wherein the substrate is made of a silicon material, a tunneling barrier dielectric layer and a polysilicon gate dielectric layer made of silicon oxide material, a charge storage layer made of silicon nitride material, the conductive layer Yes.

[0015] 为了防止擦除过程中由于栅极电子隧穿过顶部阻挡氧化层进入电荷存储层造成的擦除饱和,在本发明中采用凸面SONOS结构设计,即隧穿介质层、电荷存储层、阻挡介质层和导电层的上下表面都是凸面,与隧穿介质层接触的衬底的上表面也为凸面。 [0015] In order to prevent erasure process due to electron tunneling through the top of the barrier gate erase saturation oxide layer into the charge storage layer caused by using the SONOS structure of convex design in the present invention, i.e., the tunneling dielectric layer, a charge storage layer, blocking dielectric layer and the conductive layer of the upper and lower surfaces are convex, the upper surface of the substrate in contact with the dielectric layer and the tunneling is also convex. 在该具有凸面的SONOS结构中,由于电力线是垂直于介质层表面分布的,所以凸面的结构中,衬底和栅极之间的电力线不再是如典型SONOS结构中那样平行分布,而是从栅极垂直于ONO层(阻挡介质氧化硅层(0),存储电荷氮化硅层(N)和隧穿介质氧化硅层(O))并集中到衬底。 In the SONOS structure having a convex surface, since the power lines are perpendicular to the surface of the dielectric layer profile, the convex structure, the power lines between the substrate and the gate is no longer distributed in parallel As a typical SONOS structure, but from perpendicular to the ONO gate layer (dielectric silicon oxide barrier layer (0), a silicon nitride charge storage layer (N) and the tunnel dielectric layer is a silicon oxide (O)) and concentrated to a substrate. 如图2所示,电力线的密度代表电场强度的大小,这样的电力线分布使栅极到衬底的电场强度不断增加。 2, the size of the electric field strength representative of the density of the power line, the power line such that the distribution of the electric field strength of the substrate gate to increasing. 在擦除时,可以使电荷存储层到衬底的隧穿大于从门极注入电荷存储层的隧穿,从而可以抑制甚至消除擦除饱和的出现,提高擦除速度。 When erasing, can be made to the charge storage layer tunneling through the substrate is greater than the tunneling electrons injected from the charge storage layer through the door, can be suppressed or even eliminate the presence of the erase saturation, increase the erasing speed.

[0016] 但是只将典型的SONOS结构改进为凸面结构显然是不够的,由于门极通过阻挡氧化硅层的电子注入所引起的擦除饱和,从而提高擦除器件的擦除速度。 [0016] However, only the structure of a typical SONOS convex structure to improve clearly not enough, since the erasing gate electron injection barrier by a silicon oxide layer due to saturation, thereby enhancing the erasing device erasing speed. 但是由于一定的弯曲度,氧化娃层和氮化娃层较大的杨氏模量差别会导致两层之间产生一定的应力。 However, since a certain degree of curvature, baby oxide layer is larger Young's modulus of the difference and the nitride layer may cause a certain baby stress between the two layers. 而且由于电场在下部的场强较强,编译时由于凸面导致顶部的电场强度较大,大量的电子通过凸面的顶部注入电荷存储层,而边缘区域由于电场较弱,通过的电子较少。 And since a strong electric field strength in the lower part of the field, resulting in a convex surface due to compile a top field intensity is large, a large amount of the charge storage layer through the top of the convex surface of the electron injection, and the edge region of the electric field is weak, the electrons less. 顶部区域会有较多的电子聚集在凸面的顶部,那么在擦除时也会有较多的电子或是空穴穿过顶部。 Top area will have more electrons gathered at the top of the convex surface, then erasing will have more electrons or holes through the top. 在编译和擦除的循环中,持续的大量电荷从顶部通过会造成隧穿氧化硅层的退化。 In the programming and erasing cycle, the amount of charge from the top of continuous cause tunneling through the silicon oxide layer is degraded. 应力和隧穿氧化硅层的退化都会影响器件的耐久性和电荷保持能力,从而造成器件可靠性的下降。 Stress and tunneling silicon oxide layer is degraded and the durability of the device will affect the charge retention capability, resulting in decreased reliability of the device. [0017] 如图2所示,在上述改进的基础上,我们使用缓变的氮化硅层23代替普通的氮化硅层组成电荷存储层,缓变的氮化硅层是指硅含量渐变的氮化硅层,这样可以减少富硅的氮化硅和弯曲度大的隧穿氧化硅层之间由于氮化硅和隧穿氧化硅之间大的杨氏模量引起的应力。 [0017] As shown, on the basis of the above improvements, we use two graded silicon nitride layer 23 of silicon nitride layers in place of the ordinary charge storage layer, a silicon nitride layer of graded silicon content refers graded silicon nitride layer, thus reducing the silicon-rich silicon nitride, and a large degree of curvature tunneling oxide layer due to the stress between the silicon nitride and the tunnel oxide between the silicon causes a large Young's modulus. 由于电荷存储层与隧穿介质层的界面对器件的影响明显,而存储氮化硅层与顶部的阻挡氧化硅层之间界面对器件的影响较弱,减少电荷存储层和隧穿介质层之间的应力可以有效的改善器件的性能。 Since the charge storage layer and the tunneling dielectric layer significantly affect the interface of the device, and the interface between the weak influence on the storage device of the silicon nitride layer and a silicon oxide layer on top of the barrier, reducing the charge storage layer and the tunnel dielectric layer between stress can effectively improve performance of the device. 同时缓变的氮化硅层由于富氮的氮化硅较深的能级可以存储更多的电荷,使记忆窗口变化较大,利用富硅的氮化硅的浅陷阱能级可以较容易捕获电子。 Meanwhile graded silicon nitrogen-rich silicon nitride layer since the deep level can store more charge, so that a large change in the window memory, silicon-rich silicon nitride shallow trap levels may be captured more easily electronic. 当电子从富硅氮化硅的浅能级水平跳跃至硅含量逐渐减少的氮化硅中时,可以使存储的电子再次分布,使其较均匀的分布在存储氮化硅层中,改善由于凸面的ONO层引起的电场在隧穿氧化硅层的顶部的增强所导致的注入电子过度集中在顶部的不足。 When the electrons jump from a shallow level to a level of silicon rich silicon nitride of the silicon nitride content decreased, the distribution of electrons can store again, uniformly distributed in the storage layer than the silicon nitride, since the improvement enhanced electric field at the top of the convex surface of the ONO layer through the silicon oxide layer due to the tunneling of electrons caused by excessive concentration in the injected top insufficient.

[0018] 以上所述仅为本发明较佳的实施例,并非因此限制本发明的申请专利范围,所以凡运用本发明说明书及图示内容所做出的等效结构变化,均包含在本发明的保护范围内。 [0018] The foregoing is only preferred embodiments of the present invention, not intended to limit the scope of the present invention patent application, the use of the specification and illustrate where the present invention is made equivalent structural changes are included in the present invention, within the scope of protection.

Claims (6)

1. 一种改善SONOS结构器件性能的方法,所述SONOS结构包括衬底,隧穿介质层,电荷存储层,阻挡介质层和导电层,所述衬底内包括一源极和一漏极,所述隧穿介质层、电荷存储层、阻挡介质层和导电层按顺序自下而上设置在所述衬底上,其特征在于, 采用缓变的氮化硅层组成所述电荷存储层,所述缓变的氮化硅层自下而上由富氮氮化硅的深能级向富硅氮化硅的浅能级渐变。 1. A method of improving the performance of the structure of the SONOS device, the SONOS structure comprises a substrate, a tunnel dielectric layer, a charge storage layer, the blocking dielectric layer and a conductive layer including a source and a drain in the substrate, the tunnel dielectric layer, a charge storage layer, the blocking dielectric layer and a conductive layer are sequentially disposed from bottom to top on the substrate, wherein the silicon nitride layer using a graded composition of the charge storage layer, the graded layer of silicon nitride to silicon-rich bottom up by the deep level of the nitrogen-rich silicon nitride shallow level gradient.
2.如权利要求I所述的改善SONOS结构器件性能的方法,其特征在于,采用硅材料制成所述衬底。 2. A method for improving the performance of the structure of the SONOS device according to claim I, wherein the silicon material of the substrate.
3.如权利要求I所述的改善SONOS结构器件性能的方法,其特征在于,采用氧化硅材料制成所述隧穿介质层和所述阻挡介质层。 A method of improving the performance of the structure I SONOS device according to claim 2, characterized in that the material of the silicon oxide tunneling barrier dielectric layer and the dielectric layer.
4.如权利要求I所述的改善SONOS结构器件性能的方法,其特征在于,采用多晶硅栅极组成所述导电层。 4. A method for improving the performance of the structure of the SONOS device according to claim I, wherein the polysilicon gate using the composition of the conductive layer.
5.如权利要求4所述的改善SONOS结构器件性能的方法,其特征在于,将所述隧穿介质层、所述电荷存储层、所述阻挡介质层和所述多晶硅栅极的上表面设置为凸面。 5. A method for improving the performance of the structure of the SONOS device as claimed in claim 4, wherein the tunnel dielectric layer, the charge storage layer, said barrier dielectric layer and the upper surface of the polysilicon gate is provided convex.
6.如权利要求5所述的改善SONOS结构器件性能的方法,其特征在于,将所述隧穿介质层、所述电荷存储层、所述阻挡介质层和所述多晶硅栅极的下表面设置为凸面。 6. A method for improving the performance of the structure of the SONOS device as claimed in claim 5, wherein the tunnel dielectric layer, the charge storage layer, said barrier dielectric layer and a lower surface of the polysilicon gate convex.
CN2012103337094A 2012-09-11 2012-09-11 Method for improving performance of device of SONOS (silicon-oxide-nitride-oxide-silicon) structure CN102832175A (en)

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