CN102723368B

CN102723368B - BE-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge and forming method of BE-SONOS structural device

Info

Publication number: CN102723368B
Application number: CN201210204452.2A
Authority: CN
Inventors: 田志
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2012-06-20
Filing date: 2012-06-20
Publication date: 2014-11-19
Anticipated expiration: 2032-06-20
Also published as: CN102723368A

Abstract

The invention provides a B E-SONOS (bandgap engineered-SONOS) structural device with low compile voltage and trapping charge. A gate which is in a multiple-layered structure is disposed on the silicon substrate. The gate comprises from bottom to top, a silicon oxide layer (31), a silicon nitride layer (32) containing rich nitrogen, a silicon oxide layer (33), a silicon nitride layer (34), an oxidation resisting layer (35) and a control gate. The silicon oxide layer is contacted with the silicon substrate.

Description

A kind of BE-SONOS structure devices and formation method that there is low compiling voltage and catch electric charge

Technical field

The present invention relates to microelectronics technology, relate in particular to a kind of BE-SONOS structure devices and formation method with low compiling voltage.

Background technology

Flash memory is the one of non-volatile memory device, and traditional flash memory is to utilize the floating boom of polysilicon extremely to store data, because polysilicon is conductor, is continuous distribution so be stored in the electric charge of floating boom utmost point storage.In the time having a leakage path, the electric charge of the extremely upper storage of whole floating boom all can be lost by this leakage path.Therefore the biggest obstacle that limits the scaled ability of flash memory is that its tunnel oxide layer thickness can not continue to reduce.Because in thin tunnel oxide situation, the leakage current that directly tunnelling and stress cause etc. all can propose huge challenge to the electric leakage control of memory.The SONOS structure of latest developments, replace original polysilicon stored charge layer with the silicon nitride layer with charge trap ability, because it uses trapped charge stored charge, so the electric charge of storage is discrete distribution, such leakage path can not cause large leakage current, and therefore reliability improves.

Typical SONOS structure is made up of silicon substrate (S)-tunnel oxide (O)-charge storage layer silicon nitride (N)-barrier oxide layer (O)-polysilicon gate (S).This structure utilizes the tunnelling of electronics to compile, and wiping of data carried out in the injection in hole.For compiling and the speed of wiping are improved, need thinner tunnel oxide (3nm left and right), but so thin thickness can reduce the durability in hold facility and the compiling/erase process of electric charge.If but adopt thicker tunnel oxide, compiling and wiping just needs larger electric field.Large electric field while wiping, can make the electronics of grid arrive silicon nitride accumulation layer by barrier oxide layer.These injected electrons with reach dynamic balance from substrate injected holes, cause the saturated of erase state, if larger voltage can make to wipe and can not carry out, affect the performance of device.How, in the operation of low electric field, promote the usefulness of tunnel dielectric layer, realize that when wiping fast with hold facility and endurance, to realize be a new challenge.

The people such as Lue are at US Patent No. 2006/0198189A1(" Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operation Cells and Arrays ") in a kind of tunnel dielectric layer of BE-SONOS structure of energy band engineering is disclosed.The technical papers about BE-SONOS that the people such as Lue deliver (" BE-SONOS:A Bandgap Engineered SONOS with Excellent Performance and Reliability ". IEEE 2005; " A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory " IEEE 2007) performance of this structure is discussed.The usefulness that can provide has been provided BE-SONOS technology, can realize erasing speed, when hold facility and endurance, promotes.

Hang-Ting Lue utilizes silica and silicon nitride to build U-shaped band structure, replaces the structure of bottom oxidization layer with the ONO layer of the thin silicon nitride of two layers of thin oxide layer folder one deck.Ultra-thin O1/N1/O2 is as a tunneling medium layer that there is no a charge trap, and this is that electronics is not also able to do in time limited, just through this layer because catch the mean free path of electric charge and be greater than the thickness of this ONO layer.N2 is the layer of stored charge, is used for storing the electric charge injecting.O3 is barrier oxide layer, and it can prevent the injection of gate charge.Ultra-thin " O1/N1/O2 " provides one " tunneling barrier of being modulated ", this potential barrier can suppress direct tunnelling under low electric field, under High-Field, because the skew that can be with has the silicon nitride layer of efficient tunneled holes to stored charge, the efficiency of wiping is increased.

Summary of the invention

The present invention is directed to typical BE-SONOS structure in order to make hole only through bottom oxidization layer (O1), intermediate thin silicon nitride layer (N1) and top oxide layer must reach certain can be with skew.Making tunneled holes is not just to be determined for the potential barrier in hole by intermediate layer (thin silicon nitride layer) by the skew of being with of middle dielectric layer (thin silicon nitride).The skew of being with of upper strata oxide layer (O2) also can affect hole while wiping and enters charge storage silicon nitride layer (N2).Reduce the operating voltage while wiping by improving middle dielectric layer, further reduce the injection of gate electron.Make the erasing speed of device, electric charge hold facility and endurance reach synchronous improvement.Middle dielectric layer by the taper band structure of accumulation layer for thin ONO layer.Although ONO layer is enough thin, make its thickness be less than the mean free path of electron capture, the capture ability with regard to electronics when electronics is by this layer like this dies down.But for silicon nitride layer, still have the trap layer that some electronics are nitrided silicon in compiling and catch, these captive electronics may be understood the reliability that affect device in compiling and the circulation of wiping.

To achieve these goals, the invention provides a kind of BE-SONOS structure devices that has low compiling voltage and catch electric charge, silicon substrate is provided with the grid of sandwich construction, and described grid comprises from bottom to up:

Silicon oxide layer (31), containing silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and the control gate (36) of rich nitrogen, described silicon oxide layer contacts with silicon substrate.

In the present invention, in preferred embodiment, described silicon substrate is P type silicon substrate.

The thickness that in the present invention in preferred embodiment, the thickness of described silicon oxide layer (31) is 1.5nm, be 2nm, silicon nitride layer (34) containing silicon nitride layer (32) thickness of rich nitrogen at the thickness of 0 ~ 3.0nm, silicon oxide layer (33) is that the thickness of 7nm, barrier oxide layer (35) is 9nm.

In the present invention, in preferred embodiment, described is 0.05 ~ 0.2 containing the Si/N concentration ratio in the silicon nitride layer (32) of rich nitrogen.

Another object of the present invention is to provide a kind of method that forms above-mentioned BE-SONOS structure devices, on silicon substrate, successively prepare silicon oxide layer (31), silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36) containing rich nitrogen, rear etching is removed redundance formation grid.

In the present invention, in preferred embodiment, the silicon oxide layer of formation (31) thickness is that 1.5nm, the thickness that contains the silicon nitride layer (32) of rich nitrogen are that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm at 0 ~ 3.0nm, silicon oxide layer (33) thickness.

The present invention, by improving thin ONO layer structure in BE-SONOS structure, forms the O1/rich-N/O2 layer of the silicon nitride layer with rich nitrogen.In thin O1/rich-N1/O2 structure, there is the low charge-trapping ability of the silicon nitride layer of the rich nitrogen of deep trap energy level, can reduce electronics catching in thin intermediate in compilation process.Be trapped in the electronics in tunnel layer O1/rich-N1/O2 layer by reduction, can suppress the destabilizing factor in compiling and erase state circulation, the drift of for example threshold voltage, degradation problem under efficiency of erasing.

Brief description of the drawings

Fig. 1 is the structural representation that has low compiling state and catch the BE-SONOS structure devices of electric charge provided by the invention.

Fig. 2 be have O1/TN1/O2 layer BE-SONOS device keep charge state can be with schematic diagram.

Fig. 3 is the BE-SONOS device compiling state energy band diagram with O1/TN1/O2 layer.

Fig. 4 be have O1/TN1/O2 layer BE-SONOS device erase state can be with schematic diagram.

Embodiment

The invention provides and utilize rich nitrogen silicon nitride layer low with deep energy level to catch the one that electric charge ability reduces BE-SONOS structure devices compiling voltage to catch charge storage structure.The ability that reduces ONO layer trapped electrons in the compilation process of BE-SONOS by replace N1 layer in the ONO structure of the O1/N1/O2 in original BE-SONOS with the silicon nitride layer of rich nitrogen, improves the reliability in compiling and erase cycles.What can make that this layer of rich nitrogen do is thicker simultaneously, improves the electric charge hold facility of device.

There is low compiling voltage and catch BE-SONOS structure devices and the formation method of electric charge and be described in further details provided by the invention by the following examples; understand and the invention provides creativity and innovation so that better, but embodiment does not limit the scope of the invention.

embodiment 1

Formation has low compiling voltage, and to catch the process of BE-SONOS structure devices of electric charge as follows:

The thin silicon oxide layer 31(that first prepares a layer thickness and be 1.5nm on P type silicon substrate 1 is designated as O1), then on this silicon oxide layer 31, preparing a layer thickness is that the silicon nitride layer 32(containing rich nitrogen that 2.0nm is thin is designated as rich-N1), the Si/N concentration in the silicon nitride layer of formation is 0.1.Then at this layer containing the silicon nitride layer 32(rich-N1 of rich nitrogen) upper another layer thickness of preparation is that the silicon oxynitride layer 33(that 2.5nm is thin is designated as SiON).Then on silicon oxynitride layer 33, prepare the silicon nitride layer 34(with charge storage that one deck 7nm is thick and be designated as N2), on this layer charge storage nitration case, the thick barrier oxide layer 35(of thermal oxidation one deck 9nm is designated as O3), finally in barrier oxide layer (O3), prepare polysilicon control grid 36.Through above process, prepare the stacked gate architectures of improving tunnel oxide in BE-SONOS structure, the BE-SONOS device architecture of formation is as shown in Figure 1.

Fig. 2 be BE-SONOS device keep charge state can be with schematic diagram.Due to large thickness and the high potential barrier of silica, make the electronics of preservation and the hole of substrate at the low O1/rich-N1/O2 layer that can not pass after the match.Thereby keep good stored charge hold facility.

Fig. 3 is BE-SONOS device compiling state energy band diagram.There are two aspects can ensure that electronics is difficult for being caught by the silicon nitride of rich nitrogen: the mean free path of (1) electron capture is larger than the silicon nitride layer 32 containing rich nitrogen, do not have too many electronics and be nitrided silicon layer 34 and catch.(2) because the deep trap energy level of the silicon nitride layer 32 containing rich nitrogen is difficult for trapped electrons, when electronics passes through this layer of silicon nitride 32, captive probability declines.So the silicon nitride layer 32 containing rich nitrogen can reduce the captive probability of electronics, electronics in compilation process is declined at the probability containing in the silicon nitride layer 32 of rich nitrogen by trap, the capture rate of its silicon nitride layer 34 is raise, improve the reliability in compiling and erase cycles.What can make to do containing the silicon nitride layer 32 of rich nitrogen is thicker simultaneously, improves the electric charge hold facility of device.

Fig. 4 be BE-SONOS device erase state can be with schematic diagram.While wiping, containing the silicon nitride layer 32(rich-N1 of rich nitrogen) consistent with silicon nitride, also there is enough being with skew or offsetting that hole is passed through.Simultaneously top silica (O2) can be with the skew that also reaches certain, affect very little on the tunnelling of electronics.And due to containing not catching electric charge in compiling state in the silicon nitride layer 32 of rich nitrogen, just can there is not electronics and hole in erase state so compound at ONO layer, and affect the problem of erasing speed, further improve the reliability of device.

embodiment 2

The present embodiment and embodiment 1 are slightly different, and by regulating the thickness proportion of rich nitrogen silicon nitride and N1, the N1 layer that is 2-t nm by thickness in original BE-SONOS replaces to the silicon nitride layer 32 containing rich nitrogen that thickness is t nm.

Compare obvious erasing speed and be because silicon and silicon nitride interface are less than silicon and the silicon oxide interface potential barrier (4.6eV) for hole for the potential barrier (<1.9eV) in hole.Under High-Field, this is for the large potential barrier difference in hole, can under electric field, produce large can be with skew, make hole only fast tunnelling cross O1 layer.

Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the amendment done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.

Claims

1. have low compiling voltage and catch a BE-SONOS structure devices for electric charge, it is characterized in that, silicon substrate is provided with the grid of sandwich construction, and described grid comprises from bottom to up:

Silicon oxide layer (31), containing silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and the control gate (36) of rich nitrogen, described silicon oxide layer contacts with silicon substrate;

Described is 0.05～0.2 containing the Si/N concentration ratio in the silicon nitride layer (32) of rich nitrogen.

2. BE-SONOS structure devices according to claim 1, described silicon substrate is P type silicon substrate.

3. BE-SONOS structure devices according to claim 1, the thickness that the thickness of described silicon oxide layer (31) is 1.5nm, the thickness that is 2nm, silicon nitride layer (34) containing silicon nitride layer (32) thickness of rich nitrogen at the thickness of 0～3.0nm, silicon oxide layer (33) is 7nm, barrier oxide layer (35) is 9nm.

4. one kind forms the method that has low compiling voltage described in claim 1 and catch the BE-SONOS structure devices of electric charge, it is characterized in that, on silicon substrate, successively prepare silicon oxide layer (31), silicon nitride layer (32), silicon oxide layer (33), silicon nitride layer (34), barrier oxide layer (35) and control gate (36) containing rich nitrogen, rear etching is removed redundance formation grid.

5. method according to claim 4, it is characterized in that, silicon oxide layer (31) thickness of formation is that 1.5nm, the thickness that contains the silicon nitride layer (32) of rich nitrogen are that 2nm, silicon nitride layer (34) thickness are that 7nm, barrier oxide layer (35) thickness are 9nm at 0～3.0nm, silicon oxide layer (33) thickness.

6. method according to claim 4, described is 0.05～0.2 containing the Si/N concentration ratio in the silicon nitride layer (32) of rich nitrogen.