CN102769032B - Nitride read only memory (NROM) structure device with low operating voltage - Google Patents
Nitride read only memory (NROM) structure device with low operating voltage Download PDFInfo
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- CN102769032B CN102769032B CN201210228272.8A CN201210228272A CN102769032B CN 102769032 B CN102769032 B CN 102769032B CN 201210228272 A CN201210228272 A CN 201210228272A CN 102769032 B CN102769032 B CN 102769032B
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Abstract
The invention provides a nitride read only memory (NROM) structure device with a low operating voltage and a preparation method thereof. A layer with a silicon nitride layer and P+ polycrystalline silicon is inserted between a blocking oxidation silicon layer and a polycrystalline silicon gate, wherein the silicon nitride layer and the P+ polycrystalline silicon are crossed transversely. Speeds of electrons in a channel are adjusted by using difference of regional threshold voltages under a gate voltage, so that the electrons have a large speed before reaching a drain terminal or a source terminal (not at a junction of the source or drain terminal and a substrate), in such a way, more electrons are injected into the charge storage silicon nitride layer, and are not easily collected by a high electric field of the source or drain terminal. The programming efficiency is improved, and the programming voltage is reduced, therefore, influences of a high operating voltage on the performance and the reliability of the device are reduced.
Description
Technical field
The present invention relates to semiconductor microelectronic technology field, particularly relate to a kind of NROM structure devices with low operating voltage.
Background technology
NROM (nitride based read-only memory) technology is owing to can provide higher storage density and low voltage program and become the contenders of nonvolatile storage of future generation fast.NROM and SONOS device has same simple structure, can be compatible with the CMOS Making programme of standard, and can use thicker bottom oxidization layer in the accumulation of gate pole medium, and this can improve the holding time of store electrons and reduce the disturbance of read operation.NROM ONO gate pole media accumulation stores information, and SONOS device FN tunnelling or directly tunnelling is write and wipes difference.NROM utilizes channel hot electron, and (electronics injecting raceway groove from source accelerates under the effect of transverse electric field, higher kinetic energy is provided with near drain terminal, be called as hot electron) local injection mode compile (for P type substrate drain electrode add positive voltage, gate pole adds positive voltage), these injected electrons are stored in the silicon nitride layer utilizing trap level stored charge, make drain terminal store the electronics of some.The silicon nitride layer of source is made also to store the electronics of some by exchange source electrode and drain electrode (source electrode adds positive voltage, and gate pole adds positive voltage).This mode makes each NROM unit near source and drain terminal, can store a data respectively, improves the storage density of unit are chip, becomes the developing direction that flush memory device is new.
Thermionic generation and injection are the cooperative processes of the transverse electric field of drain terminal institute making alive generation and the longitudinal electric field of gate pole institute making alive generation.But there is again certain mutual restriction therebetween: large longitudinal electric field can reduce transverse electric field, thus thermionic quantity is reduced; If reduce longitudinal electric field to obtain more hot electron, the hot electron that can reduce again generation enters probability and the speed of silicon nitride.Balance between longitudinal electric field and transverse electric field needs to consider, need to add a higher voltage (4 ~ 5V) to ensure the drain electrode of enough thermionic sources, and to ensure that these electronics can be injected in the silicon nitride layer of stored charge by the potential barrier (3.1eV) of silicon and silicon dioxide, therefore also need high grid voltage (7 ~ 9V) during programming.Required high operating voltage can cause high power consumption, and also can affect device can contractility.
The main following points of impact that high operation voltage produces: the low (Ig/Id=10e of (a) thermionic programming efficiency
-6left and right), power consumption is large.B () high program voltage makes to have very large leakage current with the unit being programmed unit and having same bit lines, increase power consumption.C () high program voltage is unfavorable for the raising of storage chip density.D () high operating voltage can affect reducing (cross-couplings between polysilicon word line causes the mistake of unit to be programmed) of core memory array.
Summary of the invention
The present invention is directed to the deficiencies in the prior art part, provide a kind of NROM structure of improvement, during the compiling made, in this layer, the threshold voltage of the channel region that the silicon nitride layer at two ends is corresponding reduces, and is conducive to the collection of electronics, middle P
+the work function of type polysilicon is comparatively large, has higher threshold voltage, will weaken the longitudinal electric field of channel region like this, thus be conducive to transverse electric field to thermionic acceleration.Make hot electron obtain larger speed at zone line, and electronics increase in the thermionic region of the collection at two ends.
The invention provides a kind of NROM structure devices with low operating voltage to achieve these goals, the silicon substrate with source-drain electrode is provided with the grid of sandwich construction, described grid comprises from bottom to up: tunnel oxide silicon layer, charge storage nitride silicon layer, barrier oxidation silicon layer, silicon nitride layer and polysilicon control grid, and described tunnel oxide silicon layer contacts with silicon substrate; Described polysilicon control grid has larger top and less bottom, and described bottom embeds silicon nitride layer and silicon nitride layer is divided into disjunct left and right two parts, contacts bottom described polysilicon control grid with barrier oxidation silicon layer; Described grid surrounding is provided with side wall, and described source-drain electrode is located in the silicon substrate of grid both sides respectively.
In a preferred embodiment provided by the invention, wherein said silicon substrate is P-type silicon substrate.
In a preferred embodiment provided by the invention, wherein said polysilicon control grid is P
+polysilicon control grid.
In a preferred embodiment provided by the invention, the thickness of wherein said tunnel oxide silicon layer is 3 ~ 4mm, the thickness of charge storage nitride silicon layer is 6 ~ 8mm, barrier oxidation silicon layer thickness is 4 ~ 6mm.
In a preferred embodiment provided by the invention, wherein, the ratio of the right part bottom section of the left part bottom section of described silicon nitride layer, described polysilicon control grid bottom section, described silicon nitride layer is 1:3:1.
Another object of the present invention is, there is provided a kind of and form the above-mentioned method with the NROM structure devices of low operating voltage, first on a silicon substrate successively tunnel oxide silicon layer, charge storage nitride silicon layer, barrier oxidation silicon layer, silicon nitride layer is prepared, secondly on silicon nitride layer, etch the region of filling polysilicon, deposit spathic silicon make corresponding polysilicon control grid afterwards, then the redundance of etching removing polysilicon, finally makes side wall and source-drain electrode.
In a preferred embodiment provided by the invention, wherein said silicon substrate is P-type silicon substrate.
In a preferred embodiment provided by the invention, wherein said polysilicon control grid is P
+polysilicon control grid.
In a preferred embodiment provided by the invention, the wherein said thickness stating tunnel oxide silicon layer is 3 ~ 4mm, the thickness of charge storage nitride silicon layer is 6 ~ 8mm, barrier oxidation silicon layer thickness is 4 ~ 6mm.
NROM structure devices provided by the invention inserts the layer that one deck has silicon nitride layer and P+ polysilicon lateral cross between barrier oxidation silicon layer and polysilicon gate.Utilize under grid voltage, the difference of zones of different threshold voltage regulates the speed of electronics in raceway groove, a large speed (not being the intersection of source or drain terminal and substrate) has been had just to have more electron injection stored charge silicon nitride layer like this before making electronics arrive drain terminal or source, and not easily collected by source or the high electric field of drain terminal.Improve programming efficiency, reduce program voltage, thus the impact of high operation voltage on device performance and reliability can be reduced.
Accompanying drawing explanation
Fig. 1 is the structural profile schematic diagram with low operating voltage NROM structure devices provided by the invention.
Fig. 2 is the structure schematic top plan view with low operating voltage NROM structure devices provided by the invention.
Fig. 3 is the graph of a relation of electric field strength and channel length under transverse electric field, longitudinal electric field.
Embodiment
For the problem caused by above-mentioned because high operation voltage, thermionic injection efficiency during in order to improve programming further, reduces program voltage.The present invention proposes a kind of new grid structure and is applied to NROM flash memory, by inserting one deck by silicon nitride and P between barrier oxidation silicon layer and polysilicon gate
+the layer (silicon nitride is positioned at the two ends of source-drain electrode, and polysilicon is positioned at centre) of type polysilicon composition.When compiling, there is the middle P of higher work-functions
+channel region corresponding to region, threshold voltage wants high relative to common polysilicon, and the longitudinal electric field being added in the raceway groove corresponding to this section of region is lower, improves the lateral movement velocity of electronics in this section of raceway groove; The positive voltage applied makes the silicon nitride ribbon positive electricity in insert layer, thus causes the threshold voltage of the channel region of its correspondence to reduce, and overall longitudinal electric field increases, and is conducive to the collection of hot electron at drain terminal.In addition, because insert layer polysilicon is different with the impact of silicon nitride on transverse electric field, electronics has had a large speed (not being the intersection of source or drain terminal and substrate) just to have more electron injection stored charge silicon nitride layer like this before arriving drain terminal or source, and not easily collected by source or the high electric field of drain terminal.For erase state, due to grid add negative voltage time, in intercalation, the silicon nitride ribbon negative electricity at two ends, is conducive to the hole collection of source or drain terminal, and erasing speed is increased.
Above-mentioned structure, can by being issued to better compiling and erasing effect at same voltage.Compare the Memory windows of the threshold voltage of same programming and erase state, the operating voltage of needs reduces, thus can reduce the problem of the Performance And Reliability caused because operating voltage is higher.
Be described in further details NROM structure devices provided by the invention by the following examples, better to understand the content that the invention provides, but the content of embodiment does not limit the protection range of the invention.
Embodiment 1
First get out P-type silicon substrate 1, first prepare the bottom oxide silicon layer 31 of one deck 3.5nm thereon, then preparation is thereon used for stored charge and is about 7nm thick stored charge silicon nitride layer 32 (N1).Then the thick barrier oxidation silicon layer 33 (O2) of 5nm is prepared thereon.Deposit silicon nitride layer 34 thereon, and the silicon nitride 34 of centre is removed, the proportional control in the silicon nitride 341,342 at two ends and the region of centre is at 1:3:1.Then utilize in-situ depositing method deposit P type polysilicon 35, remove unnecessary polysilicon 35 by etching.Finally form side wall 41,42 and source-drain electrode 21,22, thus form structure chart as described in Figure 1, Fig. 2 is the schematic top plan view of Fig. 1.
Embodiment 2
First ready P-type silicon substrate 1, first prepares the bottom oxide silicon layer 31 of one deck 3.5nm thereon, and then preparation is thereon used for stored charge and is about 7nm thick stored charge silicon nitride layer 32 (N1).Then about 5nm thick barrier oxidation silicon layer 33 (O2) is prepared thereon.Deposit P type polysilicon 35 thereon, and the polysilicon at two ends is removed, the proportional control between the region at etching removing two ends and remaining area is at 1:3:1.Finally, deposit silicon nitride 341,342, and remove unnecessary silicon nitride, then form side wall 41,42 and source-drain electrode 21,22, thus form structure chart as described in Figure 1, Fig. 2 is the schematic top plan view of Fig. 1.
The transverse electric field along raceway groove that Fig. 3 is NROM structure devices when gate pole malleation and drain electrode malleation and the longitudinal electric field of vertical-channel and the relation schematic diagram of channel length.Analyze qualitatively, at P according to NROM structure devices
+the longitudinal electric field of polysilicon corresponding region low, is conducive to the acceleration of electronics, and at upper silicon nitride and P
+the critical part of polysilicon has larger longitudinal electric field.Due at P
+the longitudinal electric field that corresponding region is less, the transverse direction making electronics be conducive to electronics is in this section accelerated.Transverse electric field is at upper silicon nitride and P
+the channel region that the interface of polysilicon is corresponding comparatively large, instead of previous in drain electrode and region corresponding to polysilicon.The advantage of comprehensive longitudinal electric field and transverse electric field, make it produce more hot electron, and more hot electron enters in the silicon nitride layer of stored charge.And electronics is not obtain maximum speed at drain terminal, the probability of hot electron collected by the drain terminal by high electric field so just can be suppressed.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (9)
1. have a NROM structure devices for low operating voltage, it is characterized in that, the silicon substrate with source-drain electrode is provided with the grid of sandwich construction, described grid comprises from bottom to up:
Tunnel oxide silicon layer, charge storage nitride silicon layer, barrier oxidation silicon layer, silicon nitride layer and polysilicon control grid, described tunnel oxide silicon layer contacts with silicon substrate;
Described polysilicon control grid has larger top and less bottom, and described bottom embeds silicon nitride layer and silicon nitride layer is divided into disjunct left and right two parts, contacts bottom described polysilicon control grid with barrier oxidation silicon layer;
Described grid surrounding is provided with side wall, and described source-drain electrode is located in the silicon substrate of grid both sides respectively.
2. NROM structure devices according to claim 1, is characterized in that, described silicon substrate is P-type silicon substrate.
3. NROM structure devices according to claim 1, is characterized in that, described polysilicon control grid is P
+polysilicon control grid.
4. NROM structure devices according to claim 1, is characterized in that, the thickness of described tunnel oxide silicon layer is 3 ~ 4mm, the thickness of charge storage nitride silicon layer is 6 ~ 8mm, barrier oxidation silicon layer thickness is 4 ~ 6mm.
5. NROM structure devices according to claim 1, is characterized in that, the ratio of the right part bottom section of the left part bottom section of described silicon nitride layer, described polysilicon control grid bottom section, described silicon nitride layer is 1:3:1.
6. form a method as claimed in claim 1 with the NROM structure devices of low operating voltage, it is characterized in that, successively prepare tunnel oxide silicon layer, charge storage nitride silicon layer, barrier oxidation silicon layer, silicon nitride layer first on a silicon substrate; Secondly on silicon nitride layer, etch the region of filling polysilicon, afterwards deposit spathic silicon make corresponding polysilicon control grid, then the redundance of etching removing polysilicon, finally makes side wall and source-drain electrode.
7. method according to claim 6, is characterized in that, described silicon substrate is P-type silicon substrate.
8. method according to claim 6, is characterized in that, described polysilicon control grid is P
+polysilicon control grid.
9. method according to claim 6, is characterized in that, described in state tunnel oxide silicon layer thickness be 3 ~ 4mm, the thickness of charge storage nitride silicon layer is 6 ~ 8mm, barrier oxidation silicon layer thickness is 4 ~ 6mm.
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| CN100468780C (en) * | 2006-06-09 | 2009-03-11 | 北京大学 | Preparation method of NROM flash control grid and flash unit |
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