CN102664844B - Method for timing recovering of chip and removing of carrier frequency offset in demodulator - Google Patents
Method for timing recovering of chip and removing of carrier frequency offset in demodulator Download PDFInfo
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Abstract
The invention discloses a method for timing recovering of a chip and removing of a carrier frequency offset in a demodulator. A phase discriminator for capturing a modulator of a physical layer of an ultra-low power wireless communication system and timing a tracking chip is provided. The phase discriminator samples by using a sampling clock with the at least twice chip rate, is not affected by the signal carrier frequency offset on timing recovery of the chip, is not sensitive to noise, and can utilize a common low-cost crystal oscillator as a clock source. The used method for timing recovering of the chip is relatively low in realization complexity and calculation complexity. The method for removing of the carrier frequency offset is a quite simple method based on phase differential demodulation and is relatively low in realization complexity and calculation complexity. The method disclosed by the invention can achieve the purpose of removing the effect of the frequency offset on the performance without moving a signal centre frequency, so that the performance of a phase differential demodulator at a certain frequency offset and the performance without the frequency offset are kept consistent.
Description
Technical field
The present invention relates to a kind of method that in ultra-low power consumption wireless communication system physical layer demodulator, chip timings is recovered and carrier wave frequency deviation is eliminated, belong to wireless communication technology field.
Background technology
ZigBee be a kind of closely, low complex degree, low-power consumption, low data rate, two-way wireless communication technology cheaply.The basis of ZigBee is IEEE 802.15.4, and this is a standard of IEEE wireless personal local area network (Personal Area Network, PAN) working group, is known as IEEE 802.15.4 (ZigBee) technical standard.ZigBee alliance, when formulating ZigBee standard, has adopted IEEE802.15.4 as its physical layer and media Access Layer standard.On its basis, ZigBee alliance has formulated data link layer (DLL), network layer (NWK) and API (APl) standard, and the work of the aspect such as responsible higher layer applications, test and marketing.ZigBee technology is mainly embedded in the equipment such as consumer electronics device, family and building automation equipment, industrial control device, computer peripheral equipment, medical energy converter, toy and game machine, support the application in the fields such as the control based on radio communication among a small circle and automation, also support geographic positioning functionality simultaneously.ZigBee has very wide application prospect.
In prior art, to the chip timings recovery of the half-sine OQPSK signal of stipulating in 802.15.4 2450MHz PHY and frequency deviation elimination, be to realize by following method:
First use one compared with the analog to digital converter of high sampling rate (ADC), the Low Medium Frequency of Receiver Module or zero intermediate frequency output signal to be sampled, this sample rate need to equal N OQPSK signal spreading rate doubly conventionally, and wherein N is more than or equal to 4 integer.
The low rate data streams that sampled data stream is divided into N out of phase, the speed of each data flow equals 1 times of OQPSK signal spreading rate.During arriving, the chip sequence of leading symbol (preamble) use respectively N parallel correlator (each correlator length is 32 chips) with the leading symbol that N low rate data streams stored respectively at this locality, to carry out related operation simultaneously, then compare the peak value of N correlator Output rusults, Dynamic Selection that sampling phase low rate data streams that wherein degree of correlation is the highest is sent into frequency deviation cancellation module.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix afterwards and use last definite low speed sampled data stream corresponding to sampling phase.
Frequency deviation cancellation module is at leading symbol chip sequence device, the data flow that upper level is sent into is multiplied by respectively the multiple sinusoidal signal of M+1 different frequency, produces the data flow of M+1 different frequency deviations, wherein, the frequency of this M+1 multiple sinusoidal signal is generally { M Δ f,-(M-1) Δ f ... ,-Δ f, 0, Δ f ... (M-1) Δ f, M Δ f }.Then the chip sequence that uses M+1 low rate data streams to store respectively at this locality carries out related operation, and this process needs again to use the correlator that M+1 length is 32 chips to carry out computing.In M+1 correlated results, select the data path of peak value maximum as the data path of final use.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix afterwards and use last definite low speed sampled data stream corresponding to sampling phase.
Existing chip timings method is by being used the over-sampling much larger than Nyquist rate, and with a plurality of parallel correlators, obtain one and approach correct sampling phase initial value most, and this sampling phase cannot be from the correct sampling phase of motion tracking after the chip sequence of leading symbol finishes, so not only increased the complexity (ADC and the more correlator that need higher rate) of equipment, and can cause the sampling clock required precision of equipment very high, greatly increased the cost of equipment.If use common crystals, can produce too high transmitted error rate, make equipment performance be difficult to the requirement (PER<1% when signal to noise ratio snr is 5-6dB) of the standard that reaches.
The sampling clock required precision that existing frequency deviation removing method is used equipment equally in the complexity that has increased equipment is very high, and cannot follow the tracks of correct frequency deviation from using after the chip sequence of leading symbol finishes.This has larger negative interaction to the performance of equipment and stability.
Summary of the invention
Technical problem to be solved by this invention is:
A kind of phase discriminator of catching and following the tracks of sheet timing for ultra-low power consumption wireless communication system physical layer demodulator is provided, this phase discriminator makes to use the sampling clock of minimum 2 times of spreading rates to become possibility, and the impact that not recovered chip timings by signal carrier wave frequency deviation.
A kind of very simple carrier wave frequency deviation removing method for ultra-low power consumption wireless communication system physical layer demodulator phase difference demodulator is provided.The method can reach without moving signal center frequency eliminates the impact of frequency deviation on performance.
For solving the problems of the technologies described above, the invention provides a kind of method that in demodulator, chip timings is recovered and carrier wave frequency deviation is eliminated, a kind of method that in demodulator, chip timings is recovered and carrier wave frequency deviation is eliminated, it is characterized in that, comprise a phase discriminator of catching and follow the tracks of sheet timing for ultra-low power consumption wireless communication system physical layer demodulator, this phase discriminator uses the sampling clock of minimum 2 times of spreading rates to sample.
Described phase discriminator adopts 2 times of any sample rates more than spreading rate to sample to the intermediate frequency receiving or baseband signal,
By controlling the interpolation phase place of interpolation filter, obtain the sample sequence that uniform sampling is spaced apart Tc/2, { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., in this sequence, odd number sampled point corresponds to chip center sampling sample value constantly, and in this sequence, even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value;
Phase discriminator calculates the difference of the phase change amount that in adjacent two 1/2 chip-spaced, signal turns over as sample-timing error signal Te(n),
Ph_dif1(n) = arctan(r(n)/r(n-1/2)) （1）
Ph_dif2(n) = arctan(r(n-1/2)/r(n-1)) （2）
Te(n) = abs(Ph_dif1(n))- abs(Ph_dif2(n)) （3）
Wherein, Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that in two 1/2 chip-spaced, signal turns over, r (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half and the phase change amount of later half time in a chip.
Sample-timing error signal Te (n) is sent into loop filter and promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is returned phase discriminator as the input feedback of described phase discriminator, forms chip timing error closed loop feedback and controls.
When data contain carrier wave frequency deviation, estimate and the step of eliminating frequency deviation is:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained to the change amount of a chip phase as the soft input information ph_dif (n) of differential decoding,
Ph_dif(n) = Ph_dif1(n) + Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip be pi/2+Δ f*Tc and-pi/2+Δ f*Tc, in formula, Tc is chip period;
If the probability of two kinds of phase place variation generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, then from Ph_dif (n), deduct the impact that Δ f*Tc eliminates frequency deviation,
Ph_dif’(n) = Ph_dif(n) - E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
The beneficial effect that the present invention reaches:
The present invention uses feedback loop control to catch and follow the tracks of chip timings recovery, the core of its feedback loop control is chip timings phase discriminator, the present invention proposes a kind of implementation method of phase discriminator, the method is carried out the adjustment of control loop by the change amount of the first half time in same chip and later half time signal phase place, the performance of this phase discriminator is not affected by the carrier wave frequency deviation in signal, to insensitive for noise, and the chip timings of using this phase discriminator recovers very low to the frequency of sampling clock and required precision, only for being more than or equal to the arbitrary velocity of the spreading rate of 2 times, can use common low-cost crystal oscillator as clock source.Chip timings restoration methods used in the present invention has lower implementation complexity and computation complexity.
The carrier wave frequency deviation removing method that the present invention uses is a kind of very simple method based on phase difference demodulation, has lower implementation complexity and computation complexity.The present invention reaches without moving signal center frequency and eliminates the impact of frequency deviation on performance, and the property retention when making performance that phase difference demodulator can be under certain frequency deviation and there is no frequency deviation is consistent.
Accompanying drawing explanation
Fig. 1 is the theory diagram for ultra-low power consumption wireless communication physical layer demodulator;
Fig. 2 is that chip timings in Fig. 1 is recovered and the module frame chart of carrier wave frequency deviation cancellation module;
Fig. 3 is phase discriminator internal structure schematic diagram in Fig. 2;
Fig. 4 is the internal structure schematic diagram of the carrier wave frequency deviation cancellation module in Fig. 2.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.Following examples are only for technical scheme of the present invention is more clearly described, and can not limit the scope of the invention with this.
The present invention uses the circuit of " phase discriminator+feedback control loop+interpolater filter " structure to catch and follow the tracks of and approaches desirable chip samples phase place most, catch and tracking frequency offset simultaneously, by using a new phase discriminator, the impact that makes frequency deviation is in the prerequisite of mobile frequency spectrum not and use the condition of difference phase demodulation method to be issued to minimize.The half-sine OQPSK signal of stipulating in 802.15.4 2450MHz PHY standard of take is example, and the top-level module block diagram of the demodulator that the present invention proposes as shown in Figure 1, has comprised respectively the digital demodulator of rf analog front-end.Wherein in " chip timings is recovered and carrier wave frequency deviation is eliminated " module, phase discriminator of the present invention and carrier wave frequency deviation cancellation module have been comprised, this module frame chart as shown in Figure 2, main design of the present invention is the characteristic of utilizing signal definition itself, be the phase difference of former and later two chips of half-sine OQPSK signal only have pi/2 and-two kinds of pi/2s may, if adopting 2 times of any sample rates more than spreading rate samples to the intermediate frequency receiving or baseband signal, can obtain the sample sequence that uniform sampling is spaced apart Tc/2 by controlling the interpolation phase place of interpolation filter, { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., in this sequence, odd number sampled point corresponds to chip center sampling sample value constantly, and in this sequence, even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value.Phase discriminator can calculate the difference of the phase change amount that in adjacent two 1/2 chip-spaced, signal turns over accordingly as sample-timing error signal Te(n),
Ph_dif1(n) = arctan(r(n)/r(n-1/2))；（1）
Ph_dif2(n) = arctan(r(n-1/2)/r(n-1))；（2）
Te(n) = abs(Ph_dif1(n))- abs(Ph_dif2(n))；（3）
Wherein Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that in two 1/2 chip-spaced, signal turns over, and r (n) is n chip estimated value of interpolation filter output.The phase change amount of the first half and the phase change amount of later half time in chip of Te (n).
This difference is sent into loop filter and promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of reconstruction and is returned phase discriminator as the input feedback of phase discriminator, forms chip timing error closed loop feedback and controls.
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained to the change amount of a chip phase as the soft input information Ph_dif (n) of differential decoding
Ph_dif(n) = Ph_dif1(n) + Ph_dif2(n)；（4）
When the data after ADC contain carrier wave frequency deviation, although demodulation is used the mode of phase difference demodulation can tolerate the existence of frequency deviation, but frequency deviation still can cause certain influence to demodulator performance, in order to make demodulator performance in certain frequency deviation region unanimously must effectively estimate and eliminate the impact of frequency deviation.If be Δ f according to signal definition frequency deviation, phase changing capacity between adjacent chip become pi/2+Δ f*Tc and-pi/2+Δ f*Tc, suppose that it is identical (being also like this in reality) that two kinds of phase places change the probability occurring, just can from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, then from Ph_dif (n), deduct Δ f*Tc to eliminate the impact of frequency deviation.
Ph_dif’(n) = Ph_dif(n) - E(Ph_dif(n))；（5）
E (Ph_dif (n))=Δ f*Tc wherein, in above formula, Tc is chip period.
Frequency deviation is eliminated both can use feed forward architecture, can also use feedback loop control structure.
The reaction type structure of using in the present embodiment, Fig. 3, Fig. 4 have described respectively phase discriminator internal structure in Fig. 2 and the internal structure of carrier wave frequency deviation cancellation module.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.
Claims (4)
1. the method that in a demodulator, chip timings is recovered and carrier wave frequency deviation is eliminated, it is characterized in that, the phase discriminator of catching and follow the tracks of sheet timing that comprises a ultra-low power consumption wireless communication system physical layer demodulator, this phase discriminator uses the sampling clock of minimum 2 times of spreading rates to sample;
Described phase discriminator adopts 2 times of any sample rates more than spreading rate to sample to the intermediate frequency receiving or baseband signal,
By controlling the interpolation phase place of interpolation filter, obtain the sample sequence that uniform sampling is spaced apart Tc/2, { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., in this sequence, odd number sampled point corresponds to chip center sampling sample value constantly, and in this sequence, even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value; Wherein, Tc is chip period;
Phase discriminator calculates the difference of the phase change amount that in adjacent two 1/2 chip-spaced, signal turns over as sample-timing error signal Te(n),
Ph_dif1(n) = arctan(r(n)/r(n-1/2)) （1）
Ph_dif2(n) = arctan(r(n-1/2)/r(n-1)) （2）
Te(n) = abs(Ph_dif1(n))- abs(Ph_dif2(n)) （3）
Wherein, Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that in two 1/2 chip-spaced, signal turns over, r (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half and the phase change amount of later half time in a chip.
2. the method that in demodulator according to claim 1, chip timings is recovered and carrier wave frequency deviation is eliminated, it is characterized in that, sample-timing error signal Te (n) is sent into loop filter and promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is returned phase discriminator as the input feedback of described phase discriminator, forms chip timing error closed loop feedback and controls.
3. in demodulator according to claim 2, chip timings is recovered and the method for carrier wave frequency deviation elimination, it is characterized in that, when data contain carrier wave frequency deviation, estimates and the step of eliminating frequency deviation is:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained to the change amount of a chip phase as the soft input information Ph_dif (n) of differential decoding,
Ph_dif(n) = Ph_dif1(n) + Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip be pi/2+Δ f*Tc and-pi/2+Δ f*Tc, in formula, Tc is chip period;
If the probability of two kinds of phase place variation generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, then from Ph_dif (n), deduct the impact that Δ f*Tc eliminates frequency deviation,
Ph_dif’(n) = Ph_dif(n) - E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
4. in demodulator according to claim 3, chip timings is recovered and the method for carrier wave frequency deviation elimination, it is characterized in that, and the structure of described elimination frequency deviation or be feed forward architecture, or be feedback loop control structure.
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| CN103220246A (en) * | 2012-12-14 | 2013-07-24 | 西安英菲泰尔电子科技有限公司 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
| CN108337011A (en) * | 2018-01-16 | 2018-07-27 | 上海富芮坤微电子有限公司 | The construction method of Symbol Synchronization Circuit in GFSK receivers |
| CN109407121B (en) * | 2018-11-15 | 2022-07-15 | 北京遥感设备研究所 | Configurable navigation signal compatible capturing and tracking device |
| CN111397645B (en) * | 2020-04-06 | 2020-12-18 | 华中科技大学 | Phase difference decomposition and adjustment method and system |
| CN115473775B (en) * | 2022-07-26 | 2024-04-16 | 西安电子科技大学 | Parallel symbol timing recovery method suitable for low-orbit satellite Internet system |
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| CN201328110Y (en) * | 2008-11-10 | 2009-10-14 | 石强 | Phase-locking frequency tracking device |
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