CN103220246A - Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator - Google Patents
Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator Download PDFInfo
- Publication number
- CN103220246A CN103220246A CN2012105444546A CN201210544454A CN103220246A CN 103220246 A CN103220246 A CN 103220246A CN 2012105444546 A CN2012105444546 A CN 2012105444546A CN 201210544454 A CN201210544454 A CN 201210544454A CN 103220246 A CN103220246 A CN 103220246A
- Authority
- CN
- China
- Prior art keywords
- chip
- frequency deviation
- carrier wave
- timing error
- dif
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention discloses a method for timing recovery and combination carrier wave frequency offset elimination of a chip in a frequency shift keying (FSK) demodulator. A timing error generator used for the timing recovery of the chip of the FSK demodulator is included, wherein the timing error generator is used for sampling input with a lowest sampling speed rate being a random speed rate which is twice of a chip speed rate, and the timing error generator recovers regularly, is not affected by the carrier wave frequency offset of a signal, is insensitive to noise and can use a common and low-cost crystal oscillator as a clock source. The method for the timing recovery of the chip is low in complexity. The method for the combination carrier wave frequency offset elimination is a method which is low in complexity and based on phase difference demodulation. The influence to performance by the carrier wave frequency offset can be eliminated without the need of conducting spectrum displacement on the received signal, so that performance of a phase differential demodulator under the certain frequency offset keeps consistent with performance of the phase differential demodulator with no frequency offset.
Description
Technical field
The present invention relates to the method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of fsk demodulator, belong to wireless communication technology field.
Background technology
ZigBee be a kind of closely, low complex degree, low-power consumption, low data rate, two-way wireless communication technology cheaply.The basis of ZigBee is IEEE 802.15.4, and this is that (Personal Area Network, PAN) working group standard is known as IEEE 802.15.4 (ZigBee) technical standard to the IEEE wireless personal local area network.ZigBee alliance has adopted IEEE802.15.4 as its physical layer and medium Access Layer standard when formulating the ZigBee standard.On its basis, ZigBee alliance has formulated data link layer (DLL), network layer (NWK) and API (APl) standard, and the work of aspects such as responsible higher layer applications, test and marketing.The ZigBee technology mainly is embedded in consumer electronics device, family and the equipment such as building automation equipment, industrial control device, computer peripheral equipment, medical energy converter, toy and game machine, support among a small circle based on Application for Field such as the control of radio communication and automations, also support geographic positioning functionality simultaneously.ZigBee has very wide application prospect.
In the prior art chip timings of the half-sine OQPSK signal stipulated among the 802.15.42450MHz PHY recovered and frequency deviation to eliminate be method realization by following:
At first use an analog to digital converter than high sampling rate (ADC) that the Low Medium Frequency or the zero intermediate frequency output signal of Receiver Module are sampled, this sample rate need equal N OQPSK signal spreading rate doubly usually, and wherein N is the integer more than or equal to 4.
Sampled data stream is divided into the low rate data streams of N out of phase, and the speed of each data flow equals 1 times of OQPSK signal spreading rate.During arriving, the chip sequence of leading symbol (preamble) use N parallel correlator (each correlator length is 32 chips) to carry out related operation with the leading symbol that N low rate data streams stored respectively at this locality simultaneously respectively, compare N correlator output result's peak value then, Dynamic Selection that sampling phase low rate data streams that wherein degree of correlation is the highest is sent into the frequency deviation cancellation module.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix the low speed sampled data stream that uses the last sampling phase correspondence of determining afterwards.
The frequency deviation cancellation module is at leading symbol chip sequence device, the data flow that upper level is sent into multiply by the multiple sinusoidal signal of M+1 different frequency respectively, produces the data flow of M+1 different frequency deviations, wherein, the frequency of this M+1 multiple sinusoidal signal is generally { M Δ f,-(M-1) Δ f ... ,-Δ f, 0, Δ f ... (M-1) Δ f, M Δ f}.The chip sequence that uses M+1 low rate data streams to store respectively at this locality then carries out related operation, and the correlator that it is 32 chips that this process needs again to use M+1 length carries out computing.The data path of selecting the peak value maximum in M+1 correlated results is as the final data path that uses.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix the low speed sampled data stream that uses the last sampling phase correspondence of determining afterwards.
Existing chip timings method is by using the over-sampling much larger than Nyquist rate, and use a plurality of parallel correlators to obtain a correct sampling phase initial value the most approaching, and this sampling phase can't be from the correct sampling phase of motion tracking after the chip sequence of leading symbol finishes, so not only increased the complexity (ADC and the more correlator that need higher rate) of equipment, and can cause the sampling clock required precision of equipment very high, increased the cost of equipment greatly.If the use common crystals then can produce too high transmitted error rate, make equipment performance be difficult to the requirement of the standard that reaches (PER when signal to noise ratio snr is 5-6dB＜1%).
The sampling clock required precision that existing frequency deviation removing method uses equipment in the complexity that has increased equipment equally is very high, and can't follow the tracks of correct frequency deviation from using after the chip sequence of leading symbol finishes.This performance and stability to equipment all has bigger negative interaction.
Summary of the invention
Technical problem to be solved by this invention is:
A kind of Timing Error Detector of catching and following the tracks of the sheet timing that is used for fsk demodulator is provided, and this Timing Error Detector makes uses the sampling clock of minimum 2 times of spreading rates to become possibility, and the influence that not chip timings is recovered by the signal carrier wave frequency deviation.
A kind of very simple carrier wave frequency deviation removing method of the FSK of being used for phase difference demodulator is provided.This method can need not to move signal center frequency and reach the elimination frequency deviation to Effect on Performance.
For solving the problems of the technologies described above, the invention provides the method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of demodulator, the method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of demodulator, it is characterized in that, comprise one be used for the FSK physical layer demodulator catch and follow the tracks of sheet Timing Error Detector regularly, this Timing Error Detector uses the sampling clock of minimum 2 times of spreading rates to sample.
Described Timing Error Detector adopts the above any sample rate of 2 times of spreading rates that the intermediate frequency or the baseband signal that receive are sampled,
Interpolation phase place by the control interpolation filter obtains the sample sequence that uniform sampling is spaced apart Tc/2, { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., the odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence;
Timing Error Detector is calculated the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced as sample-timing error signal Te (n),
Ph_dif1(n)＝imag(r(n)*conj(r(n-1/2))) (1)
Ph_dif2(n)＝imag(r(n-1/2)*conj(r(n-1))) (2)
Te(n)＝abs(Ph_dif1(n))-abs(Ph_dif2(n)) (3)
Wherein, Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that signal turns in two 1/2 chip-spaced, r (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half in the chip and the phase change amount of back half the time.
Sample-timing error signal Te (n) is sent into loop filter promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is fed back to Timing Error Detector as the input of described Timing Error Detector, forms chip timing error close-loop feedback control.
When data contained carrier wave frequency deviation, the step of estimation and elimination frequency deviation was:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input ph_dif (n) of the change amount of a chip phase as differential decoding,
Ph_dif(n)＝Ph_dif1(n)+Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip be pi/2+Δ f*Tc and-pi/2+Δ f*Tc, in the formula, Tc is a chip period;
If the probability of two kinds of phase change generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct the influence that Δ f*Tc eliminates frequency deviation then,
Ph_dif’(n)＝Ph_dif(n)-E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
The beneficial effect that the present invention reached:
The present invention uses feedback control loop control to catch and follow the tracks of the chip timings recovery, the core of its feedback control loop control is the chip timings Timing Error Detector, the present invention proposes a kind of implementation method of Timing Error Detector, the adjustment that this method uses the change amount of the first half time in the same chip and back half the time signal phase to come control loop, the performance of this Timing Error Detector is not influenced by the carrier wave frequency deviation in the signal, to insensitive for noise, and the chip timings of using this Timing Error Detector recovers very low to the frequency and the required precision of sampling clock, only be arbitrary velocity, can use common low-cost crystal oscillator as the clock source more than or equal to 2 times spreading rate.Chip timings restoration methods used in the present invention has lower implementation complexity and computation complexity.
The carrier wave frequency deviation removing method that the present invention uses is a kind of very simple method based on the phase difference demodulation, and lower implementation complexity and computation complexity are arranged.The present invention need not to move signal center frequency and reaches and eliminate frequency deviation to Effect on Performance, makes that the phase difference demodulator can be consistent in the property retention of the performance under certain frequency deviation when not having frequency deviation.
Description of drawings
Fig. 1 is the theory diagram that is used for fsk demodulator;
Fig. 2 is that the chip timings among Fig. 1 is recovered and the module frame chart of carrier wave frequency deviation cancellation module;
Fig. 3 is a Timing Error Detector internal structure schematic diagram among Fig. 2;
Fig. 4 is the internal structure schematic diagram of the carrier wave frequency deviation cancellation module among Fig. 2.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.Following examples only are used for technical scheme of the present invention more clearly is described, and can not limit protection scope of the present invention with this.
The present invention uses the circuit of " Timing Error Detector+feedback control loop+interpolater filter " structure to catch and follow the tracks of the most approaching desirable chip samples phase place, catch simultaneously and tracking frequency offset, by using a new Timing Error Detector, the influence that makes frequency deviation is in the prerequisite of mobile frequency spectrum not and use the condition of difference phase demodulation method to be issued to minimize.With the half-sine OQPSK signal stipulated in the 802.15.42450MHz PHY standard is example, and the top-level module block diagram of the demodulator that the present invention proposes has comprised the digital demodulator of rf analog front-end respectively as shown in Figure 1.Wherein Timing Error Detector of the present invention and carrier wave frequency deviation cancellation module have been comprised in " chip timings is recovered and carrier wave frequency deviation is eliminated " module, this module frame chart as shown in Figure 2, main design of the present invention is a characteristic of utilizing signal definition itself, be the phase difference of former and later two chips of half-sine OQPSK signal have only pi/2 and-pi/2 two kinds may, if adopting the above any sample rate of 2 times of spreading rates samples to the intermediate frequency or the baseband signal that receive, can obtain the sample sequence that uniform sampling is spaced apart Tc/2 by the interpolation phase place of control interpolation filter, { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., the odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence.Timing Error Detector can be calculated the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced in view of the above as sample-timing error signal Te (n),
Ph_dif1(n)＝imag(r(n)*conj(r(n-1/2))) (1)
Ph_dif2(n)＝imag(r(n-1/2)*conj(r(n-1))) (2)
Te(n)＝abs(Ph_dif1(n))-abs(Ph_dif2(n)) (3)
Wherein Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that signal turns in two 1/2 chip-spaced, n the chip estimated value that r (n) exports for interpolation filter.The phase change amount of phase change amount of the first half and back half the time in chip of Te (n).
This difference is sent into loop filter promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of reconstruction and is fed back to Timing Error Detector as the input of Timing Error Detector, forms chip timing error close-loop feedback control.
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input Ph_dif (n) of the change amount of a chip phase as differential decoding
Ph_dif(n)＝Ph_dif1(n)+Ph_dif2(n)；(4)
When the data after the ADC contain carrier wave frequency deviation, though demodulation uses the mode of phase difference demodulation can tolerate the existence of frequency deviation, but frequency deviation still can cause certain influence to demodulator performance, in order to make the consistent influence that must effectively estimate and eliminate frequency deviation of demodulator performance in certain frequency deviation region.If according to the signal definition frequency deviation is Δ f, phase changing capacity between adjacent chip become pi/2+Δ f*Tc and-pi/2+Δ f*Tc, suppose that the probability that two kinds of phase change take place is identical (also being like this in the reality), just can from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct Δ f*Tc then to eliminate the influence of frequency deviation.
Ph_dif’(n)＝Ph_dif(n)-E(Ph_dif(n))；(5)
E (Ph_dif (n))=Δ f*Tc wherein, in the following formula, Tc is a chip period.
Frequency deviation is eliminated both can use feed forward architecture, can also use the feedback control loop control structure.
The reaction type structure of using in the present embodiment, Fig. 3, Fig. 4 have described the Timing Error Detector internal structure among Fig. 2 and the internal structure of carrier wave frequency deviation cancellation module respectively.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.
Claims (5)
1. chip timings is recovered and the method for carrier wave frequency deviation elimination in the fsk demodulator, it is characterized in that, comprise one and be used for the Timing Error Detector that the fsk demodulator chip timings is recovered, this Timing Error Detector is carried out the chip timings recovery based on the arbitrary velocity sampling clock of minimum 2 times of spreading rates.
2. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 1 is characterized in that, described Timing Error Detector adopts the above any sample rate of 2 times of spreading rates that the intermediate frequency or the baseband signal that receive are sampled,
Interpolation phase place by the control interpolation filter obtains sample sequence that uniform sampling is spaced apart Tc/2, and (Tc is the signal chip period, down together), { r (n), r (n+1/2), r (n+1), r (n+1+1/2) ..., the odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence;
Timing Error Detector is calculated the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced as sample-timing error signal Te (n),
Ph_dif1(n)＝imag(r(n)*conj(r(n-1/2))) (1)
Ph_dif2(n)＝imag(r(n-1/2)*conj(r(n-1))) (2)
Te(n)＝abs(Ph_dif1(n))-abs(Ph_dif2(n)) (3)
Wherein, the imaginary part that plural number is got in imag () expression, conj () expression plural number is got conjugate operation, the phase place that on behalf of two the 1/2 interior signals of chip-spaced, Ph_dif1 (n) and Ph_dif2 (n) turn over, r (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half in the chip and the phase change amount of back half the time.
3. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 2, it is characterized in that, sample-timing error signal Te (n) is sent into loop filter promote whole timing loop, the timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is fed back to Timing Error Detector as the input of described Timing Error Detector, forms chip timing error close-loop feedback control.
4. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 3 is characterized in that, when data contained carrier wave frequency deviation, the step of estimation and elimination frequency deviation was:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input ph_dif (n) of the change amount of a chip phase as differential decoding,
Ph_dif(n)＝Ph_dif1(n)+Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip be pi/2+Δ f*Tc and-pi/2+Δ f*Tc, in the formula, Tc is a chip period;
If the probability of two kinds of phase change generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct the influence that Δ f*Tc eliminates frequency deviation then,
Ph_dif’(n)＝Ph_dif(n)-E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
5. chip timings is recovered and the method for carrier wave frequency deviation elimination in the demodulator according to claim 4, it is characterized in that, and the structure of described elimination frequency deviation or be feed forward architecture, or be the feedback control loop control structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105444546A CN103220246A (en) | 2012-12-14 | 2012-12-14 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105444546A CN103220246A (en) | 2012-12-14 | 2012-12-14 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103220246A true CN103220246A (en) | 2013-07-24 |
Family
ID=48817720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105444546A Pending CN103220246A (en) | 2012-12-14 | 2012-12-14 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103220246A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330315A (en) * | 2015-06-15 | 2017-01-11 | 深圳市中兴微电子技术有限公司 | Data processing method and device |
| CN108900453A (en) * | 2018-06-13 | 2018-11-27 | 上海晟矽微电子股份有限公司 | DC component acquisition device and method |
| CN115473775A (en) * | 2022-07-26 | 2022-12-13 | 西安电子科技大学 | Parallel symbol timing recovery method suitable for low earth orbit satellite Internet system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201328110Y (en) * | 2008-11-10 | 2009-10-14 | 石强 | Phase-locking frequency tracking device |
| CN102664844A (en) * | 2012-04-11 | 2012-09-12 | 苏州英菲泰尔电子科技有限公司 | Method for timing recovering of chip and removing of carrier frequency offset in demodulator |
| CN102780505A (en) * | 2012-08-16 | 2012-11-14 | 苏州英菲泰尔电子科技有限公司 | Wireless digital FSK (frequency shift keying) transceiver |
-
2012
- 2012-12-14 CN CN2012105444546A patent/CN103220246A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201328110Y (en) * | 2008-11-10 | 2009-10-14 | 石强 | Phase-locking frequency tracking device |
| CN102664844A (en) * | 2012-04-11 | 2012-09-12 | 苏州英菲泰尔电子科技有限公司 | Method for timing recovering of chip and removing of carrier frequency offset in demodulator |
| CN102780505A (en) * | 2012-08-16 | 2012-11-14 | 苏州英菲泰尔电子科技有限公司 | Wireless digital FSK (frequency shift keying) transceiver |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330315A (en) * | 2015-06-15 | 2017-01-11 | 深圳市中兴微电子技术有限公司 | Data processing method and device |
| CN106330315B (en) * | 2015-06-15 | 2019-02-05 | 深圳市中兴微电子技术有限公司 | A kind of data processing method and device |
| CN108900453A (en) * | 2018-06-13 | 2018-11-27 | 上海晟矽微电子股份有限公司 | DC component acquisition device and method |
| CN108900453B (en) * | 2018-06-13 | 2021-02-09 | 上海晟矽微电子股份有限公司 | Direct current component acquisition device and method |
| CN115473775A (en) * | 2022-07-26 | 2022-12-13 | 西安电子科技大学 | Parallel symbol timing recovery method suitable for low earth orbit satellite Internet system |
| CN115473775B (en) * | 2022-07-26 | 2024-04-16 | 西安电子科技大学 | Parallel symbol timing recovery method suitable for low-orbit satellite Internet system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100483963C (en) | Orthogonal lower mixing frequency digital template matching pulse ultra wide band radio signal receiving method | |
| CN108667484B (en) | Instantaneous frequency measurement and demodulation method for incoherent spread spectrum digital transceiver | |
| CN101946474B (en) | Impulse ultra-wideband radio communication system | |
| CN100530992C (en) | Robust non-coherent receiver for pam-ppm signals | |
| CN101032139B (en) | Frame synchronization and initial symbol timing acquisition system and method | |
| Liu et al. | All-digital synchronization for SC/OFDM mode of IEEE 802.15. 3c and IEEE 802.11 ad | |
| CN108234376A (en) | Radio data communication method and device | |
| CN102684744B (en) | Power supply self-synchronizing phase inversion modulator-demodulator for power line communication | |
| US7864880B2 (en) | Blind synchronization and demodulation | |
| CN102664844B (en) | Method for timing recovering of chip and removing of carrier frequency offset in demodulator | |
| CN103248593B (en) | Offset estimation and removing method and system | |
| CN101110602B (en) | Carrier wave catching system and method based on multimode operation | |
| CN104092642B (en) | A kind of carrier phase synchronization method and device being used in non-coherent demodulation circuit | |
| EP2690915A1 (en) | Method for robust downlink timing synchronization of a lte system | |
| WO2009075448A1 (en) | Receiving apparatus and receiving method of impulse-radio uwb wireless system | |
| JP2010510719A (en) | Signal system using transmission reference pulse | |
| CN106998586A (en) | The synchronization acquiring method of wireless communication system in a kind of high dynamic environment | |
| CN103220246A (en) | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator | |
| CN101902425A (en) | Method for synchronizing time and carrier frequency in short-range wireless network | |
| US20120327975A1 (en) | Systems and methods for pulse rotation modulation encoding and decoding | |
| CN105099442A (en) | Apparatus and method for modular signal acquisition and detection | |
| CN109714146A (en) | A kind of secondary related frame synchornization method based on sliding window | |
| KR20160102480A (en) | Using multiple correlators to determine signal sent and frequency offset | |
| KR20060114747A (en) | Baseband transceive of ultra wide band radio communication system | |
| KR101512441B1 (en) | Non coherent demodulation method for LR-WPAN and apparatus thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130724 |