CN102573335A - Method for manufacturing core plate of initial layer - Google Patents
Method for manufacturing core plate of initial layer Download PDFInfo
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- CN102573335A CN102573335A CN2010106203533A CN201010620353A CN102573335A CN 102573335 A CN102573335 A CN 102573335A CN 2010106203533 A CN2010106203533 A CN 2010106203533A CN 201010620353 A CN201010620353 A CN 201010620353A CN 102573335 A CN102573335 A CN 102573335A
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- initial layers
- layers central
- central layer
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 68
- 239000010949 copper Substances 0.000 claims abstract description 68
- 229910052802 copper Inorganic materials 0.000 claims abstract description 68
- 238000003475 lamination Methods 0.000 claims abstract description 45
- 239000010935 stainless steel Substances 0.000 claims abstract description 18
- 229910001220 stainless steel Inorganic materials 0.000 claims abstract description 12
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 9
- 229910001069 Ti alloy Inorganic materials 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims description 15
- 238000002360 preparation method Methods 0.000 claims description 12
- 238000007740 vapor deposition Methods 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 8
- 229910001256 stainless steel alloy Inorganic materials 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 13
- 230000003628 erosive effect Effects 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 233
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000004806 packaging method and process Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
The invention provides a method for manufacturing a core plate of an initial layer. The method comprises the following steps of: preparing at least one seed layer, at least one circuit layer, a copper column layer and a prepreg lamination layer on a support plate so as to obtain the core plate of the initial layer; and separating the core plate of the initial layer from the support plate, wherein the support plate is made of stainless steel, aluminum alloy or titanium alloy. According to the method for manufacturing the core plate of the initial layer, the stainless-steel support plate of which the surface is polished is selected, so that the quality of the circuit layer is prevented from being influenced by high roughness of the surface of a copper support plate, the thickness of the seed layer can be easily reduced, and the manufacturing cost of the core plate of the initial layer can be easily reduced; and the support plate and the core plate of the initial layer are separated through an ultrasonic separation technique, so that lateral erosion of the circuit layer caused by separating the support plate and the core plate of the initial layer by etching is avoided, and then the yield of the core plate of the initial layer is increased.
Description
Technical field
The present invention relates to make the technical field of printed circuit board (PCB), particularly, relate to a kind of method and the support plate that is used for circuit board manufacturing initial layers central layer of initial layers central layer.
Background technology
The fast development of electronic technology makes that the integrated level of semiconductor device is increasingly high, and base plate for packaging is developed to multi-layer sheet by lamina gradually, for example high density PCB (printed circuit board (PCB)) base plate for packaging.In order to improve the integrated level of PCB base plate for packaging, adopt the interlayer interconnection technique that multi-layer sheet is connected, to obtain more available wiring area in limited space.
At present, the method for manufacturing PCB base plate for packaging includes nuclear Layer increasing method and seedless Layer increasing method.Yet, utilize the thickness that the nuclear base plate for packaging is arranged that has the nuclear Layer increasing method to make thicker, be unfavorable for that base plate for packaging is to highly integrated development.And, when needs processing thickness below 60 μ m the nuclear base plate for packaging is arranged the time, its rate of finished products is lower.Therefore, in practical application, extensively adopt seedless Layer increasing method to make base plate for packaging.
Seedless Layer increasing method is to make one or more layers line layer on initial layers central layer surface, thereby forms base plate for packaging.The concrete manufacturing process of initial layers central layer is following: at first adopt electroplating technology to make one deck nickel dam on copper support plate surface as being protective layer; Then in electroplating surface one deck copper film Seed Layer of nickel dam; Utilize the image transfer method on Seed Layer, to electroplate initial line road layer and interlayer copper post layer again; Carrying out lamination, nog plate, Seed Layer sputter coating, Seed Layer plating and nickel protection layer afterwards successively electroplates; Through etching method copper support plate and protective layer are got rid of at last, thereby acquisition is used for the initial layers central layer of seedless base plate for packaging.The main process of image transfer method is: when making semiconductor chip; At first on substrate, cover one deck dry film; Like photoresistance etc., then to dry film make public, developing obtains circuit pattern, on circuit pattern, electroplates metals such as layer of copper, aluminium or gold again; Remove dry film then, just can obtain circuit according to the shape connection of circuit pattern.
Yet, there is following shortcoming when adopting above-mentioned technology to make the initial layers central layer:
First; Because the nickel dam protective layer that copper support plate surface roughness height and electroplating technology are made exists nickel dam to dredge the hole problem, causes the nickel dam protective layer can't cover line layer fully, when last chemical etching copper support plate technology; Cause the line layer breach easily, thereby cause scrapping of initial layers central layer;
The second, need the Seed Layer of plating thicker, greatly about 5-7 μ m, and need the etching number of times more, cause the lateral erosion (Undercut) of line layer easily, cause the width of line layer to be difficult for stripping control, the problem that line layer is peeled off takes place easily;
The 3rd, the cost of manufacture of initial layers central layer is higher, and then causes the cost of manufacture of whole base plate for packaging higher.
Summary of the invention
For addressing the above problem, the present invention provides a kind of manufacture method of initial layers central layer, is used for the problem that rate of finished products is low, cost is high of prior art initial layers central layer.
For this reason, the present invention provides a kind of manufacture method of initial layers central layer, wherein, comprising: on support plate, prepare one deck Seed Layer, at least one layer of line layer, copper post layer and prepreg lamination at least, obtain the initial layers central layer;
Said initial layers central layer is separated with said support plate;
Said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
Preferably, the thickness of said first Seed Layer is 1.8-2.2 μ m, preferred 2.0 μ m; And/or the thickness of said second Seed Layer is at 0.8-1.2 μ m, preferred 1.0 μ m.
Preferably, comprise said said initial layers central layer is separated with said support plate:
Utilize ultrasonic wave that said initial layers central layer is separated with said support plate.
Preferably, on said support plate, also comprise before preparation first Seed Layer, initial line layer, copper post layer, prepreg lamination and second Seed Layer at stainless steel:
Said support plate is carried out polishing, and the roughness that preferably makes said support plate is between 0.01-0.1mm.
Preferably, after being used to make said initial layers central layer, said support plate is reused through cleaning the back.
Preferably, said support plate is used for lamination treatment.
Preferably; Surface coverage prepreg lamination at said Seed Layer, line layer and copper post layer; The height of said prepreg lamination is higher than the height of copper post layer, then the prepreg lamination is ground the plane that obtains said prepreg lamination and copper post layer composition.
Preferably, before the said prepreg lamination of surface coverage of said Seed Layer, line layer and copper post layer, comprise:
Brown is carried out on the surface of said Seed Layer, line layer and copper post layer to be handled.
Preferably, on said support plate, prepare first Seed Layer in the said Seed Layer through flash, heavy copper, splash, plating or vapor deposition mode.
Preferably, the mode through flash, heavy copper, splash, plating or vapor deposition prepares second Seed Layer in the said Seed Layer on the plane of said prepreg lamination and copper post layer composition.
The present invention also provides a kind of support plate that is used for circuit board manufacturing initial layers central layer, and wherein, said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
The present invention has following beneficial effect:
In the manufacture method of initial layers central layer provided by the invention; The support plate of the stainless steel through selecting surface finish for use, avoiding material is the high quality that influences line layer of roughness on the support plate surface of copper, helps reducing the thickness of Seed Layer; Reduce the manufacturing cost of initial layers central layer; Separate support plate and initial layers central layer through the ultrasonic wave isolation technics again, cause lateral erosion when avoiding separating support plate and initial layers central layer, thereby improve the rate of finished products of initial layers central layer line layer through etching.
Description of drawings
Fig. 1 is the flow chart of manufacture method first embodiment of initial layers central layer provided by the invention;
Fig. 2 is the flow chart of manufacture method second embodiment of initial layers central layer provided by the invention;
Fig. 3 a-3j is the generalized section of product in the manufacture method of initial layers central layer provided by the invention.
Embodiment
The present invention provides a kind of manufacture method of initial layers central layer, it is characterized in that, comprising:
On support plate, prepare one deck Seed Layer, at least one layer of line layer, copper post layer and prepreg lamination at least, obtain the initial layers central layer;
Said initial layers central layer is separated with said support plate;
Said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
Preferably, in various embodiments of the present invention,
The thickness of said first Seed Layer is 1.8-2.2 μ m, preferred 2.0 μ m; And/or
The thickness of said second Seed Layer is at 0.8-1.2 μ m, preferred 1.0 μ m.
Preferably, in various embodiments of the present invention, comprise said said initial layers central layer is separated with said support plate: utilize ultrasonic wave that said initial layers central layer is separated with said support plate.
Preferably; In various embodiments of the present invention; On said support plate, also comprise before preparation first Seed Layer, initial line layer, copper post layer, prepreg lamination and second Seed Layer: said support plate is carried out polishing, and the roughness that preferably makes said support plate is between 0.01-0.1mm at stainless steel.
Preferably, in various embodiments of the present invention, after being used to make said initial layers central layer, said support plate is reused through cleaning the back.
Preferably, in various embodiments of the present invention, said support plate is used for lamination treatment.
Preferably; In various embodiments of the present invention; Surface coverage prepreg lamination at said Seed Layer, line layer and copper post layer; The height of said prepreg lamination is higher than the height of copper post layer, then the prepreg lamination is ground the plane that obtains said prepreg lamination and copper post layer composition.
Preferably, in various embodiments of the present invention, before the said prepreg lamination of surface coverage of said Seed Layer, line layer and copper post layer, comprise: brown is carried out on the surface of said Seed Layer, line layer and copper post layer handle.
Preferably, in various embodiments of the present invention, on said support plate, prepare first Seed Layer in the said Seed Layer through flash, heavy copper, splash, plating or vapor deposition mode.
Preferably, in various embodiments of the present invention, through mode second Seed Layer in the said Seed Layer of preparation on the plane of said prepreg lamination and copper post layer composition of flash, heavy copper, splash, plating or vapor deposition.
When embodiment of the present invention,, also can further set gradually more line layer (and Seed Layer) except ground floor line layer (and first Seed Layer), second line layer (and second Seed Layer).
The present invention provides a kind of support plate that is used for circuit board manufacturing initial layers central layer, it is characterized in that, said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
For making those skilled in the art understand technical scheme of the present invention better, be described in detail below in conjunction with the manufacture method of accompanying drawing to initial layers central layer provided by the invention.
Fig. 1 is the flow chart of manufacture method first embodiment of initial layers central layer provided by the invention.As shown in Figure 1, the method for present embodiment initial layers central layer comprises the steps:
In the present embodiment; The support plate 101 of stainless steel is handled through mirror finish; On upper surface of said carrier plate, prepare first Seed Layer in the Seed Layer through modes such as flash, heavy copper, splash, plating or vapor depositions; The material of first Seed Layer can be selected copper for use, and preferably, the thickness of first Seed Layer is about 2 μ m.Through selecting material for use is stainless support plate; And the support plate surface carried out polishing; Make support plate ground roughness between 0.01-0.1mm; Phenomenons such as the generation breach of first line layer that minimizing causes because of the rough surface of support plate or fracture, simultaneously, the support plate of surface finish also helps the initial layers central layer and separates from support plate.
In the present embodiment; Through the initial line layer in the image transfer legal system reserve line layer be used for the copper post layer that interlayer is connected; Then brown is carried out on the surface of first Seed Layer, initial line layer and copper post layer and handle, then cover one deck prepreg lamination on the surface of each line layer of process brown processing again, pass through lamination treatment again; Grind the prepreg lamination then; Lamination treatment is used to improve the tightness between each metal level, avoids metal level to come off, milled processed copper post layer is exposed and guarantee the prepreg lamination and plane that copper post layer upper surface formed smooth; Follow-up line layer can be prepared on the flat surface, improve the rate of finished products of follow-up line layer; Through mode second Seed Layer in the plating sublayer on the plane of prepreg lamination and copper post layer composition of flash, the heavy copper of level, metal splash, plating or vapor deposition, the thickness of second Seed Layer is about 0.8-1.2 μ m, preferably 1.0 μ m again; And then on first Seed Layer, prepare the secondary wire layer in the line layer through the image transfer method, thereby obtain having the initial layers central layer of two-layer line layer.
Repeat above-mentioned step, can obtain the more initial layers central layer of multi-line layer.
Step 102, the initial layers central layer is separated with support plate.
The initial layers central layer is separated with support plate to obtain independently initial layers central layer.In the present embodiment; Can separate initial layers central layer and support plate through non-etching methods such as ultrasonic wave isolation technics; Ultrasonic wave separates initial layers central layer and support plate and helps reducing the etching number of times in the manufacture process of initial layers central layer; Avoid the serious lateral erosion (Undercut) that repeatedly etching causes line layer occurring, thereby can improve the quality and the stability of each line layer.Can repeated use after cleaning with support plate after initial sandwich layer separates, and support plate can also be used for lamination treatment, thereby also provides cost savings.
In practical application, support plate can adopt the high metal material of compactness to prepare, and for example adopts material preparations such as stainless steel, titanium alloy or aluminium alloy, and the material that above-mentioned compactness is high can effectively be avoided the thin hole problem of copper support plate.
The support plate of the stainless steel of present embodiment through selecting surface finish for use; Avoiding material is the high quality that influences line layer of roughness on the support plate surface of copper; Help reducing the thickness of Seed Layer, reduce the cost of manufacture of initial layers central layer, separate support plate and initial layers central layer through the ultrasonic wave isolation technics again; Cause lateral erosion when avoiding separating support plate and initial layers central layer, thereby improve the rate of finished products of initial layers central layer line layer through etching.
Fig. 2 is the flow chart of manufacture method second embodiment of initial layers central layer provided by the invention.Show that like Fig. 2 the method for present embodiment initial layers central layer comprises the steps:
Fig. 3 a-3j is the generalized section of product in the manufacture method of initial layers central layer provided by the invention.Consult Fig. 3 a, in the present embodiment, the support plate 101 of stainless steel is handled smooth surface through mirror finish; Consult Fig. 3 b, what on support plate, prepare first Seed Layer, 201, the first Seed Layer, 201 materials in the Seed Layer in the control of flash on the upper surface of support plate 101, heavy copper, splash, plating or vapor deposition is copper; The thickness of first Seed Layer 201 is between 1.8-2.2 μ m; 2 μ m preferably simultaneously, cover one deck dry film 202 as the anti-plate protective layer at the lower surface of support plate 101; Dry film 202 can be photoresist, gets into step 102 then.
Consult Fig. 3 c; Cover one deck dry film through the image transfer method in first Seed Layer 201; After overexposure, development, obtain having the dry film 302 of initial circuit layer pattern, and then the initial line layer 301 in the layer of plating line road on first Seed Layer 201, step 203 got into then.
Consult Fig. 3 d and Fig. 3 e; On the surface of the initial electric line layer 301 and first Seed Layer 201, cover one deck dry film; Then through obtaining having the dry film 402 of copper post layer pattern after exposure, the development; Electro-coppering obtains copper post layer 401 on copper post layer pattern again, then dry film 302 and dry film 402 etchings is removed, and gets into step 204.
In this step; Consult Fig. 3 f and Fig. 3 g; At first first Seed Layer 201, initial line layer 301 and copper post layer 401 on the support plate being carried out brown handles to improve its surface roughness; When brown is handled, will etch into the copper on first Seed Layer 201, initial line layer 301 and copper post layer 401 surface, the thickness of etch copper should be controlled at 0.7-1.0 μ m; Then on first line layer, cover one deck prepreg lamination 601 and carry out lamination treatment; Grind the prepreg lamination then; Milled processed is exposed copper post layer and is guaranteed that prepreg lamination 601 is smooth with the plane of copper post layer 401 upper surface composition; Wherein, Prepreg lamination 601 had both guaranteed the isolation between Seed Layer 201, initial line layer 301 and the follow-up line layer, follow-up line layer can be prepared on the flat surface and with copper post layer 401 fully contact, and improved the rate of finished products of follow-up line layer.
Consult Fig. 3 h; On the flat surface that prepreg lamination 601 and copper post layer 401 are formed, pass through flash, heavy copper (Plating Through Hole; PTH) or the mode of splash (Sputer), plating or vapor deposition prepare second Seed Layer 801; The thickness of second Seed Layer 801 between 0.8-1.2 μ m, 1.0 μ m preferably.
Consult Fig. 3 i, prepare secondary wire layers 901 through the image transfer method in second Seed Layer 801, thereby on support plate 101, prepare initial layers central layer 111.
Repeat above-mentioned steps, can prepare the more initial layers central layer of multi-line layer.
In the present embodiment, consult Fig. 3 j, can initial layers central layer 111 be separated with support plate 101, thereby reduce the etching number of times in preparation initial layers central layer 111 processes through non-etching modes such as ultrasonic wave isolation technics.
Present embodiment through select for use surface finish for example for the support plate of stainless steel; Prevented thin hole phenomenon, avoiding material is the high quality that influences line layer of roughness on the support plate surface of copper, has reduced the thickness of Seed Layer simultaneously; Reduced cost; Separate support plate and initial layers central layer through the ultrasonic wave isolation technics again, cause serious lateral erosion when avoiding separating support plate and initial layers central layer, thereby improved the quality of initial layers central layer line layer through etching.
The present invention also provides a kind of support plate that is used for circuit board manufacturing initial layers central layer, and the density of support plate is high, can effectively avoid the thin hole problem of support plate, and support plate can be aluminium alloy support plate, titanium alloy support plate and stainless steel support plate etc.Preferably, the roughness of support plate is easy to through non-etching techniques such as ultrasonic technologies support plate separated with the initial layers central layer between 0.01-0.1mm.
It is understandable that above execution mode only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For the one of ordinary skilled in the art, under the situation that does not break away from spirit of the present invention and essence, can make various modification and improvement, these modification also are regarded as protection scope of the present invention with improving.
Claims (11)
1. the manufacture method of an initial layers central layer is characterized in that, comprising:
On support plate, prepare one deck Seed Layer, at least one layer of line layer, copper post layer and prepreg lamination at least, obtain the initial layers central layer;
Said initial layers central layer is separated with said support plate;
Said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
2. the manufacture method of initial layers central layer according to claim 1 is characterized in that,
The thickness of said first Seed Layer is 1.8-2.2 μ m, preferred 2.0 μ m; And/or
The thickness of said second Seed Layer is at 0.8-1.2 μ m, preferred 1.0 μ m.
3. the manufacture method of initial layers central layer according to claim 1 and 2 is characterized in that, comprises said said initial layers central layer is separated with said support plate:
Utilize ultrasonic wave that said initial layers central layer is separated with said support plate.
4. according to the manufacture method of each described initial layers central layer in the aforementioned claim; It is characterized in that, on said support plate, also comprise before preparation first Seed Layer, initial line layer, copper post layer, prepreg lamination and second Seed Layer at stainless steel:
Said support plate is carried out polishing, and the roughness that preferably makes said support plate is between 0.01-0.1mm.
5. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that after being used to make said initial layers central layer, said support plate is reused through cleaning the back.
6. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that,
Said support plate is used for lamination treatment.
7. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that,
At the surface coverage prepreg lamination of said Seed Layer, line layer and copper post layer, the height of said prepreg lamination is higher than the height of copper post layer, then the prepreg lamination is ground the plane that obtains said prepreg lamination and copper post layer composition.
8. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that, before the said prepreg lamination of surface coverage of said Seed Layer, line layer and copper post layer, comprise:
Brown is carried out on the surface of said Seed Layer, line layer and copper post layer to be handled.
9. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that:
On said support plate, prepare first Seed Layer in the said Seed Layer through flash, heavy copper, splash, plating or vapor deposition mode.
10. according to the manufacture method of each described initial layers central layer in the aforementioned claim, it is characterized in that,
Mode second Seed Layer in the said Seed Layer of preparation on the plane of said prepreg lamination and copper post layer composition through flash, heavy copper, splash, plating or vapor deposition.
11. a support plate that is used for circuit board manufacturing initial layers central layer is characterized in that, said support plate is processed by stainless steel or aluminium alloy or titanium alloy.
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| CN201010620353.3A CN102573335B (en) | 2010-12-23 | 2010-12-23 | The method of initial layer core veneer |
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| CN201010620353.3A CN102573335B (en) | 2010-12-23 | 2010-12-23 | The method of initial layer core veneer |
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| CN102573335B CN102573335B (en) | 2016-08-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105530761A (en) * | 2014-09-29 | 2016-04-27 | 深南电路有限公司 | Circuit board manufacturing method |
| CN106028683A (en) * | 2015-03-26 | 2016-10-12 | 住友电木株式会社 | Manufacturing method of organic resin substrate, organic resin substrate and semiconductor device |
| CN106961808A (en) * | 2017-02-20 | 2017-07-18 | 宁波华远电子科技有限公司 | The preparation method of sunk type high density interconnecting board |
| CN109788664A (en) * | 2017-11-14 | 2019-05-21 | 何崇文 | A kind of circuit base plate and preparation method thereof |
| CN109862695A (en) * | 2017-11-30 | 2019-06-07 | 宏启胜精密电子(秦皇岛)有限公司 | Built-in type circuit board and preparation method thereof |
| CN111356309A (en) * | 2020-04-15 | 2020-06-30 | 江苏普诺威电子股份有限公司 | Manufacturing method of multilayer circuit board with high line alignment precision |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0543364A2 (en) * | 1991-11-21 | 1993-05-26 | Nec Corporation | Method for manufacturing polyimide multilayer wiring substrate |
| CN1438686A (en) * | 2002-02-15 | 2003-08-27 | 恩益禧电子股份有限公司 | Semiconductor device and making method |
| CN101146407A (en) * | 2006-09-15 | 2008-03-19 | 李东明 | Graph transfer shaping technology for carrier board circuit of printed circuit board |
| CN101415299A (en) * | 2007-10-16 | 2009-04-22 | 三星Techwin株式会社 | Method of manufacturing multi-layer circuit board |
| CN101541145A (en) * | 2009-03-17 | 2009-09-23 | 上海美维科技有限公司 | Processing method of ultra-thin core board in manufacturing of printed circuit board or integrated circuit package substrate |
| JP2009239188A (en) * | 2008-03-28 | 2009-10-15 | Hitachi Aic Inc | Method of manufacturing printed circuit board |
| CN101594749A (en) * | 2008-05-23 | 2009-12-02 | 株式会社电装 | The manufacture method of electric conductor for interlayer connection |
-
2010
- 2010-12-23 CN CN201010620353.3A patent/CN102573335B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0543364A2 (en) * | 1991-11-21 | 1993-05-26 | Nec Corporation | Method for manufacturing polyimide multilayer wiring substrate |
| CN1438686A (en) * | 2002-02-15 | 2003-08-27 | 恩益禧电子股份有限公司 | Semiconductor device and making method |
| CN101146407A (en) * | 2006-09-15 | 2008-03-19 | 李东明 | Graph transfer shaping technology for carrier board circuit of printed circuit board |
| CN101415299A (en) * | 2007-10-16 | 2009-04-22 | 三星Techwin株式会社 | Method of manufacturing multi-layer circuit board |
| JP2009239188A (en) * | 2008-03-28 | 2009-10-15 | Hitachi Aic Inc | Method of manufacturing printed circuit board |
| CN101594749A (en) * | 2008-05-23 | 2009-12-02 | 株式会社电装 | The manufacture method of electric conductor for interlayer connection |
| CN101541145A (en) * | 2009-03-17 | 2009-09-23 | 上海美维科技有限公司 | Processing method of ultra-thin core board in manufacturing of printed circuit board or integrated circuit package substrate |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105530761A (en) * | 2014-09-29 | 2016-04-27 | 深南电路有限公司 | Circuit board manufacturing method |
| CN106028683A (en) * | 2015-03-26 | 2016-10-12 | 住友电木株式会社 | Manufacturing method of organic resin substrate, organic resin substrate and semiconductor device |
| CN106961808A (en) * | 2017-02-20 | 2017-07-18 | 宁波华远电子科技有限公司 | The preparation method of sunk type high density interconnecting board |
| CN106961808B (en) * | 2017-02-20 | 2019-09-10 | 宁波华远电子科技有限公司 | The production method of sunk type high density interconnecting board |
| CN109788664A (en) * | 2017-11-14 | 2019-05-21 | 何崇文 | A kind of circuit base plate and preparation method thereof |
| CN109788664B (en) * | 2017-11-14 | 2020-07-24 | 何崇文 | Circuit substrate and manufacturing method thereof |
| CN109862695A (en) * | 2017-11-30 | 2019-06-07 | 宏启胜精密电子(秦皇岛)有限公司 | Built-in type circuit board and preparation method thereof |
| CN111356309A (en) * | 2020-04-15 | 2020-06-30 | 江苏普诺威电子股份有限公司 | Manufacturing method of multilayer circuit board with high line alignment precision |
| CN111356309B (en) * | 2020-04-15 | 2021-04-23 | 江苏普诺威电子股份有限公司 | Manufacturing method of multilayer circuit board with high line alignment precision |
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