CN102437107A - Method for manufacturing integrated circuit with super-thick top-layer metal and integrated circuit - Google Patents
Method for manufacturing integrated circuit with super-thick top-layer metal and integrated circuit Download PDFInfo
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- CN102437107A CN102437107A CN2011103883188A CN201110388318A CN102437107A CN 102437107 A CN102437107 A CN 102437107A CN 2011103883188 A CN2011103883188 A CN 2011103883188A CN 201110388318 A CN201110388318 A CN 201110388318A CN 102437107 A CN102437107 A CN 102437107A
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Abstract
The invention discloses a method for manufacturing an integrated circuit with a super-thick top-layer metal and the integrated circuit with the super-thick top-layer metal. The manufacturing method comprises the following steps of: depositing and etching a barrier layer and a dielectric layer on a metal layer of a semiconductor substrate; spin-coating a first photoresist layer, and forming through hole patterns and redundant groove patterns through through-hole optical mask photoetching; etching part of the dielectric layer to form part of through holes and redundant grooves; spin-coating a second photoresist layer, and forming metal groove patterns through metal layer optical mask photoetching; etching the dielectric layer to form metal grooves; etching to open an etching barrier layer at the bottom of the through holes; and depositing a metal barrier layer and a copper seed layer, filling metallic copper, and chemically and mechanically grinding to flatten the metal surface so as to form a dual damascene structure with the super-thick top-layer metal. The integrated circuit is manufactured by the method provided by the invention. The method can be compatible with part of through hole priority dual damascene processes, is simple in manufacturing process, and cannot worsen a grinding process while improving torsional deformation of a base plate induced by the super-thick top-layer metal.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly have ultra thick top-level metallic integrated circuit manufacture method and have the integrated circuit of ultra thick top-level metallic.
Background technology
Along with the semiconductor integrated circuit characteristic size continue reduce, back segment interconnection resistance electric capacity (Resistor Capacitor, be called for short RC) postpones to appear the trend of remarkable increase, and postpones in order to reduce back segment interconnection RC, copper-connection replaces the aluminium interconnection becomes main flow technology.Because the manufacture method of copper interconnecting line can not form through etching sheet metal as aluminum interconnecting, so copper Damascus mosaic technology becomes the standard method of the making of copper interconnecting line.The technology in copper Damascus comprises: deposition one dielectric layer on planar substrates; In dielectric layer, form through hole and the groove of inlaying through photoetching and etching technics; Plated metal barrier layer and copper seed layer; Plated metal copper fills up through hole and groove in the dielectric layer; Excess metal on the dielectric layer is removed in the cmp planarization, forms planar copper interconnect.
Because metallic copper and dielectric layer thermal expansion coefficient difference are big, the stress that forms in the manufacturing process of copper-connection metal level can cause the buckling deformation of substrate, and along with metal layer thickness increases, stress increases, and base plate deformation also increases thereupon.Particularly for the manufacturing of ultra thick top-level metallic (UTM), top-level metallic thickness can reach 3um or more than, substrate can form very serious buckling deformation.The serious buckling deformation of substrate may cause substrate in successive process, to scrap, and for example, the substrate of distortion can influence the accuracy of photoetching; Perhaps substrate can't be written into by follow-up board; Perhaps substrate is written at board that can't adsorbing in the transmission course causes dropping breaks into pieces, perhaps ftractures owing to base plate stress is excessive.In addition, the serious buckling deformation of substrate also can have influence on the encapsulation of substrate.Generally speaking, manufacturing brings sizable difficulty to integrated circuit in the buckling deformation of substrate, has a strong impact on the product yield.
In order to improve ultra thick top-level metallic the influence that substrate warp is out of shape is had dual mode: a kind of mode is the redundant metal of removing in the ultra thick top layer metallic layer; Density through reducing metallic pattern reduces the stress that metallic copper causes; This mode can alleviate the substrate warp distortion to a certain extent, yet this mode can worsen chemical mechanical milling tech; Another kind of mode is to increase an independent redundant metal photomask version to make shallow redundant metal; Improve the substrate warp distortion through reducing redundant metal thickness; Though this kind mode can not worsen chemical mechanical milling tech; But this need increase the chemical wet etching processing step, complex process, and production cost is high.
Therefore; For integrated circuit with ultra thick top-level metallic; Do not influencing cmp (CMP) technology, and do not increasing on the basis of processing step, how improving ultra thick top-level metallic is the technical problem that needs to be resolved hurrily that integrated circuit fields faces to the influence that substrate warp is out of shape.
Summary of the invention
The present invention proposes a kind of manufacture method with integrated circuit of ultra thick top-level metallic, and it is not influencing chemical mechanical milling tech, and does not increase on the basis of processing step, can improve the influence of ultra thick top-level metallic to the substrate warp distortion.
For realizing above-mentioned purpose, the present invention adopts following technical scheme:
Manufacture method with integrated circuit of ultra thick top-level metallic of the present invention comprises the steps:
S1, on the metal level of semiconductor substrate deposition-etch barrier layer and dielectric layer successively;
S2, on said dielectric layer spin coating first photoresist layer, form via hole image and redundant groove figure through the photoetching of through hole photomask, wherein said via hole image is positioned at above the copper interconnecting line of metal level of said semiconductor substrate;
S3, along said via hole image and the said dielectric layer of the downward partial etching of redundant groove figure; Form partial through holes and redundant groove, wherein the etching depth requirement is: said partial through holes bottom just in time places said etching barrier layer upper surface after guaranteeing follow-up metal valley etching; Then, remove the remainder of said first photoresist layer;
S4, on said dielectric layer spin coating second photoresist layer, form the metal valley figure through the photoetching of metal level photomask;
S5, along the said dielectric layer of the downward etching of said metal valley figure, make said partial through holes bottom terminate in said etching barrier layer upper surface; Remove the remainder of said second photoresist layer; Continue etching and open the etching barrier layer of said partial through holes bottom, expose said copper interconnecting line, form metal valley and through hole;
S6, the ultra thick top layer metallic layer of metallization: plated metal barrier layer and copper seed layer on said through hole, said metal valley and said redundant trench wall respectively; In said through hole, metal valley and said redundant groove, electroplate respectively then and fill metallic copper; The said metallic copper of cmp, flattening surface is removed excess metal on the said dielectric layer, the final two big horse scholar structures of the ultra thick top layer metallic layer with ultra thick interconnection line metal, through-hole interconnection and shallow redundant metal that form.
Wherein, the thickness of said ultra thick interconnection line metal is 20,000-40,000A; The height of said through-hole interconnection is 2,000-10,000A.
The 1.2-2 that said shallow redundant metal thickness is said through-hole interconnection height doubly.
The technology of deposition-etch barrier layer and dielectric layer is the CVD sedimentation among the said step S1.
The material of the etching barrier layer among the said step S1 is selected from one or more among SiCN, SiN, SiC, the SiCO.
The material of said dielectric layer is selected from one or both of USG, FSG.
The material of the metal barrier among the said step S6 is selected from one or both of TaN, Ta.
Metal barrier adopts the PVD depositing operation among the said step S6.
Said copper seed crystal layer is selected the PVD depositing operation for use.
The present invention has the integrated circuit of ultra thick top-level metallic, and it uses the manufacture method with integrated circuit of ultra thick top-level metallic of the present invention to process.
Can know by technique scheme; Advantage and good effect that the present invention proposes a kind of manufacture method of the integrated circuit with ultra thick top-level metallic and has an integrated circuit of ultra thick top-level metallic are: in the manufacture method of the present invention; The redundancy structure figure is dosed on the through hole photomask; On the metal level photomask, do not add redundant metal structure, need not add independent redundant metal photomask version yet; And; Adopt the preferential dual damascene process of partial through holes, form shallow redundant groove, and then form the redundant metal of thinner thickness; Therefore; Method of the present invention can the preferential dual damascene process of compatible partial through holes, and not only manufacture craft is simple, and when improving the substrate torsional deformation that ultra thick top-level metallic induces, can not worsen chemical mechanical milling tech.
Description of drawings
Fig. 1 representes in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention the structural representation on deposition-etch barrier layer and dielectric layer on substrate;
Fig. 2 representes in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention on dielectric layer spin coating first photoresist layer and forms via hole image and the structural representation of redundancy structure figure;
Fig. 3 representes that etching dielectric layer in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention forms the structural representation of partial through holes and redundant groove;
Fig. 4 representes in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention on dielectric layer spin coating second photoresist layer and forms the structural representation of metal valley figure;
Fig. 5 representes that etching dielectric layer in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention forms the structural representation of metal valley;
Fig. 6 representes the metallized structural representation of ultra thick top layer metallic layer in the manufacture method of the integrated circuit with ultra thick top-level metallic of the present invention.
Wherein, main description of reference numerals is following:
1 substrate, 5 second photoresist layers
2 etching barrier layers, 6 metal valleys
The 7 ultra thick interconnection line metal of 3 dielectric layers
4 first photoresist layers, 8 shallow redundant metals
Embodiment
To shown in Figure 6, the manufacture method with integrated circuit of ultra thick top-level metallic of the present invention comprises the steps: like Fig. 1
S1, on the metal level of semiconductor substrate 1 deposition-etch barrier layer 2 and dielectric layer 3 successively; In this S1 step, the technology of deposition-etch barrier layer 2 and dielectric layer 3 can be selected the CVD sedimentation, and wherein this etching barrier layer 2 can be chosen one or more among SiCN, SiN, SiC, the SiCO, and dielectric layer 3 can be chosen one or both among USG, the FSG.Has copper interconnecting line 11 in the metal level of semiconductor substrate 1.
S2, on dielectric layer 3 spin coating first photoresist layer 4, form via hole image 41 and redundant groove (Dummy) figure 42 through the photoetching of through hole photomask, wherein via hole image 41 is positioned at copper interconnecting line 11 upper areas of the metal level of semiconductor substrate 1.
S3, along via hole image 41 and redundant groove figure 42 downward etched portions dielectric layers 3, form partial through holes 31 and redundant groove 32, suitably control etching depth; Guarantee that through hole 31 bottoms, follow-up metal valley etching rear section just in time place etching barrier layer 2 upper surfaces, it is insufficient both to be unlikely to etching, and partial through holes 31 not etching arrives etching barrier layer 2; Also be unlikely to take place over etching; Partial through holes 31 is carved too early and is worn etching barrier layer 2, and partial through holes 31 can be 8,000A with redundant groove 32 etching depths; But be not limited to this value; Generally the degree of depth of partial through holes 31 and redundant groove 32 can be in final through hole 61 degree of depth 2, and 000-10 is in the 1.2-2 of the 000A times scope; Then, remove the remainder of first photoresist layer 4.
S4, on dielectric layer 3 spin coating second photoresist layer 5, form metal valley figure 51 through the photoetching of metal level photomask.
S5, along metal valley figure 51 downward etching dielectric layers 3, make partial through holes 31 bottoms terminate in etching barrier layer 2 upper surfaces; Remove the remainder of second photoresist layer 5; Continue etching and open the etching barrier layer 2 of partial through holes 31 bottoms, expose copper interconnecting line 11, forming the degree of depth is 20,000-40, the metal valley 6 and 2 of 000A, 000-10, the through hole 61 of 000A.
S6, the ultra thick top layer metallic layer of metallization: plated metal barrier layer and copper seed layer on through hole 61, metal valley 6 and redundant groove 32 inwalls respectively; In through hole 61, metal valley 6 and redundant groove 32, electroplate respectively and fill metallic copper; The cmp metallic copper, flattening surface is removed excess metal on the dielectric layer 3, the final two big horse scholar structures of ultra thick top layer metallic layer with ultra thick interconnection line metal 7, through-hole interconnection 71 and shallow redundant metal 8 that form.Among the present invention, the degree of depth of shallow redundant metal 8 is superficial with respect to the thickness of ultra thick interconnection line metal 7, therefore is referred to as shallow redundant metal 8; Wherein, the material of metal barrier is selected from one or both of TaN, Ta; Copper seed crystal layer can be selected the PVD depositing operation for use.
In the method for the present invention, method of the present invention can the preferential dual damascene process of compatible partial through holes, and on the metal level photomask, does not add redundant metal structure, also need not add independent redundant metal photomask version, so manufacture craft is simple; Simultaneously, method of the present invention can not worsen chemical mechanical milling tech.
Integrated circuit with ultra thick top-level metallic of the present invention; Process by the manufacture method with integrated circuit of ultra thick top-level metallic of the present invention; It has ultra thick top-level metallic; Therefore and have shallow redundant metal in the ultra thick top-level metallic, can improve ultra thick top-level metallic and induce the substrate distortion that is distorted.
Though described the present invention with reference to several exemplary embodiments, should be appreciated that used term is explanation and exemplary and nonrestrictive term.Because the present invention's practical implementation and do not break away from the spirit or the essence of invention in a variety of forms; So be to be understood that; The foregoing description is not limited to any aforesaid details; And should in enclose spirit that claim limited and scope, explain widely, therefore fall into whole variations and remodeling in claim or its equivalent scope and all should be the claim of enclosing and contain.
Claims (10)
1. have the manufacture method of the integrated circuit of ultra thick top-level metallic, it is characterized in that, comprise the steps:
S1, on the metal level of semiconductor substrate (1) deposition-etch barrier layer (2) and dielectric layer (3) successively;
S2, go up spin coating first photoresist layer (4) at said dielectric layer (3); Form via hole image (41) and redundant groove figure (42) through the photoetching of through hole photomask, wherein said via hole image (41) is positioned at copper interconnecting line (11) top of the metal level of said semiconductor substrate (1);
S3, along said via hole image (41) and redundant groove figure (42) the said dielectric layer of partial etching (3) downwards; Form partial through holes (31) and redundant groove (32), wherein the etching depth requirement is: said partial through holes (31) bottom just in time places said etching barrier layer (2) upper surface after guaranteeing follow-up metal valley etching; Then, remove the remainder of said first photoresist layer (4);
S4, go up spin coating second photoresist layer (5), form metal valley figure (51) through the photoetching of metal level photomask at said dielectric layer (3);
S5, along the downward said dielectric layer of etching (3) of said metal valley figure (51), make said partial through holes (31) bottom terminate in said etching barrier layer (2) upper surface; Remove the remainder of said second photoresist layer (5); Continue etching and open the etching barrier layer (2) of said partial through holes (31) bottom, expose said copper interconnecting line (11), form metal valley (6) and through hole (61);
S6, the ultra thick top layer metallic layer of metallization: plated metal barrier layer and copper seed layer on said through hole (61), said metal valley (6) and said redundant groove (32) inwall respectively; In said through hole (61), said metal valley (6) and said redundant groove (32), electroplate respectively then and fill metallic copper; The said metallic copper of cmp, flattening surface is removed said dielectric layer (3) and is gone up excess metal, the final two big horse scholar structures of the ultra thick top layer metallic layer with ultra thick interconnection line metal (7), through-hole interconnection (71) and shallow redundant metal (8) that form.
2. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, the thickness of said ultra thick interconnection line metal (7) is 20,000-40,000A; The height of said through-hole interconnection (71) is 2,000-10,000A.
3. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, said shallow redundant metal (8) thickness is 1.2-2 times of said through-hole interconnection (71) height.
4. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, the technology of deposition-etch barrier layer (2) and dielectric layer (3) is the CVD sedimentation among the said step S1.
5. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, the material of the etching barrier layer among the said step S1 (2) is selected from one or more among SiCN, SiN, SiC, the SiCO.
6. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, the material of said dielectric layer (3) is selected from one or both of USG, FSG.
7. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that the material of the metal barrier among the said step S6 selects one or both of TaN, Ta.
8. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, metal barrier adopts the PVD depositing operation among the said step S6.
9. the manufacture method with integrated circuit of ultra thick top-level metallic as claimed in claim 1 is characterized in that, copper seed crystal layer adopts the PVD depositing operation among the said step S6.
10. the integrated circuit with ultra thick top-level metallic is characterized in that using each the described manufacture method with integrated circuit of ultra thick top-level metallic like claim 1-9 to process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011103883188A CN102437107A (en) | 2011-11-29 | 2011-11-29 | Method for manufacturing integrated circuit with super-thick top-layer metal and integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103883188A CN102437107A (en) | 2011-11-29 | 2011-11-29 | Method for manufacturing integrated circuit with super-thick top-layer metal and integrated circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738076A (en) * | 2012-07-27 | 2012-10-17 | 上海华力微电子有限公司 | Through hole propriety copper interconnection manufacturing method |
| CN103165412A (en) * | 2013-03-15 | 2013-06-19 | 上海华力微电子有限公司 | Method for treating wafer surface indentation defect |
| CN103268866A (en) * | 2013-05-23 | 2013-08-28 | 上海华力微电子有限公司 | Through-hole-priority dual damascene copper interconnection method for reducing coupling capacitance of redundant metal |
| CN103268864A (en) * | 2013-05-23 | 2013-08-28 | 上海华力微电子有限公司 | Through-hole-priority dual damascene copper interconnection method for reducing coupling capacitance of redundant metal |
| CN104347581A (en) * | 2013-07-23 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor interconnection structure, semiconductor device comprising same, and preparation methods thereof |
| CN105051883A (en) * | 2013-03-15 | 2015-11-11 | 密克罗奇普技术公司 | Forming fence conductors in an integrated circuit |
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| US20070224795A1 (en) * | 2006-03-22 | 2007-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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2011
- 2011-11-29 CN CN2011103883188A patent/CN102437107A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070224795A1 (en) * | 2006-03-22 | 2007-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738076A (en) * | 2012-07-27 | 2012-10-17 | 上海华力微电子有限公司 | Through hole propriety copper interconnection manufacturing method |
| CN102738076B (en) * | 2012-07-27 | 2014-10-22 | 上海华力微电子有限公司 | Through hole propriety copper interconnection manufacturing method |
| CN103165412A (en) * | 2013-03-15 | 2013-06-19 | 上海华力微电子有限公司 | Method for treating wafer surface indentation defect |
| CN105051883A (en) * | 2013-03-15 | 2015-11-11 | 密克罗奇普技术公司 | Forming fence conductors in an integrated circuit |
| CN105051883B (en) * | 2013-03-15 | 2020-06-09 | 密克罗奇普技术公司 | Forming fence conductors in an integrated circuit |
| CN103268866A (en) * | 2013-05-23 | 2013-08-28 | 上海华力微电子有限公司 | Through-hole-priority dual damascene copper interconnection method for reducing coupling capacitance of redundant metal |
| CN103268864A (en) * | 2013-05-23 | 2013-08-28 | 上海华力微电子有限公司 | Through-hole-priority dual damascene copper interconnection method for reducing coupling capacitance of redundant metal |
| CN104347581A (en) * | 2013-07-23 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor interconnection structure, semiconductor device comprising same, and preparation methods thereof |
| CN104347581B (en) * | 2013-07-23 | 2017-04-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor interconnection structure, semiconductor device comprising same, and preparation methods thereof |
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Application publication date: 20120502 |