CN105051883B - Forming fence conductors in an integrated circuit - Google Patents

Forming fence conductors in an integrated circuit Download PDF

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CN105051883B
CN105051883B CN201480014820.4A CN201480014820A CN105051883B CN 105051883 B CN105051883 B CN 105051883B CN 201480014820 A CN201480014820 A CN 201480014820A CN 105051883 B CN105051883 B CN 105051883B
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trench
dielectric
conductive film
nanometers
walls
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CN105051883A (en
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保罗·菲思特
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Microchip Technology Inc
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Microchip Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The spacer etch process produces ultra-narrow conductive lines in a plurality of semiconductor dies. The sub-lithographic patterning of the conductive lines is compatible with existing aluminum and copper back-end processing. A first dielectric (212) is deposited onto the semiconductor die and a trench is formed therein. A conductive film (218) is deposited onto the first dielectric and trench surfaces. All planar conductive films are removed from the face of the semiconductor die and the bottom of the trench, leaving only conductive films (218) on the trench walls, thereby forming "fence conductors" therefrom. Thereafter, the gaps between the conductive films on the trench walls are filled with an insulating material (212 a). Thereafter, a top portion of the insulated gap fill is removed to expose a top portion of the fence conductor. Portions of the fence conductors and surrounding insulating material are removed at appropriate locations to produce the desired conductor pattern comprising isolated fence conductors.

Description

Forming fence conductors in an integrated circuit
Technical Field
The present invention relates to semiconductor Integrated Circuit (IC) fabrication, and more particularly to sub-lithographic patterning of conductive lines therein during fabrication of a semiconductor die, such as an integrated circuit die.
Background
Reduction in the size of patterned conductive lines used for interconnection of active elements (e.g., transistors) in semiconductor dies has been limited by available photolithographic processes. As the number of transistors on a semiconductor die has increased due to improvements in the photolithographic masking process used to form these transistors, the conductive lines that must interconnect these progressively smaller sized transistors have failed to decrease in size in proportion to the progressively smaller transistors.
Disclosure of Invention
Accordingly, there is a need for a way to reduce the size of patterned conductive lines without limiting the photolithographic processes that may be used to fabricate semiconductor integrated circuits.
According to an embodiment, a method for forming fence conductors in a semiconductor integrated circuit die may comprise the steps of: depositing a first dielectric on a face of a semiconductor substrate; forming at least one trench in the first dielectric; depositing a conductive film on the first dielectric, including on walls and bottom of the at least one trench; removing portions of the conductive film from a side of the first dielectric and the bottom of the at least one trench, wherein the conductive film remains only on the walls of the at least one trench; depositing a second dielectric between the conductive films on the walls of the at least one trench; and removing portions of the second dielectric to expose top portions of the conductive film on the walls of the at least one trench.
According to a further embodiment of the method, after the step of removing portions of the second dielectric to expose top portions of the conductive film on the walls of the at least one trench, the method may comprise the step of separating portions of the conductive film on the walls of the at least one trench into independent fence conductors. According to a further embodiment, after the step of removing portions of the conductive film from a face of the first dielectric and the bottom of the at least one trench, the method may comprise the step of separating portions of the conductive film on the walls of the at least one trench into independent fence conductors.
According to a further embodiment, the step of depositing the first dielectric may comprise the step of depositing the first dielectric to a thickness of from about 100 to about 2000 nanometers on the face of the semiconductor substrate. According to a further embodiment, the step of forming the at least one trench may comprise the step of forming the at least one trench to a depth of from about 100 nanometers to about 2000 nanometers in the first dielectric. According to a further embodiment, the step of forming the at least one trench may comprise the step of forming the at least one trench having a width from about 100 nanometers to about 2000 nanometers in the first dielectric. According to a further embodiment, the step of depositing the conductive film may comprise the step of depositing the conductive film to a thickness of from about 10 nanometers to about 1000 nanometers. According to a further embodiment, the step of depositing the second dielectric may comprise the step of depositing the second dielectric to a thickness of from about 100 nanometers to about 2000 nanometers.
According to still another embodiment, the conductive film may include an aluminum film. According to a further embodiment, the conductive film may be selected from the group consisting of: ta, TaN, Ti, TiN, Si, WSi and CoSi. According to a further embodiment, the step of separating portions of the conductive film may comprise the step of separating portions of the conductive film by means of Reactive Ion Etching (RIE). According to a further embodiment, the RIE may be aggressive. According to a further embodiment, the method may comprise the steps of filling gaps formed by the RIE with a dielectric and Chemical Mechanical Planarization (CMP) polishing thereof.
According to a further embodiment, a semiconductor die may comprise: a semiconductor substrate; a first dielectric on a face of the semiconductor substrate; at least one trench in the first dielectric; a conductive film on a wall of the at least one trench; and a second dielectric filling spaces between the conductive films on the walls of the at least one trench, wherein the conductive films can be separated and used as fence conductors to connect active elements of the semiconductor die.
According to a further embodiment, the semiconductor wafer may comprise a plurality of semiconductor dies. According to a further embodiment, the first dielectric may have a thickness from about 100 nanometers to about 2000 nanometers. According to a further embodiment, the at least one trench may have a depth from about 100 to about 2000 nanometers and a width from about 100 to about 2000 nanometers. According to a further embodiment, the conductive film may have a thickness from about 10 nanometers to about 1000 nanometers. According to a further embodiment, the second dielectric may have a thickness from about 100 nanometers to about 2000 nanometers. According to a further embodiment, the conductive film may be selected from the group consisting of: al, Ta, TaN, Ti, TiN, Si, WSi and CoSi.
Drawings
A more complete understanding of the present invention may be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which:
fig. 1 illustrates a schematic plan view of a semiconductor integrated circuit wafer including a plurality of semiconductor dies;
figure 2 illustrates schematic elevational views of semiconductor fabrication steps for forming sub-lithographic patterns of conductive lines in a semiconductor die, according to specific example embodiments of this disclosure;
figure 3 illustrates a schematic elevational view of further semiconductor fabrication steps for forming a sub-lithographic pattern of conductive lines in a semiconductor die, according to a specific example embodiment of this disclosure;
figure 4 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, according to a specific example embodiment of this disclosure;
figure 5 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, according to a specific example embodiment of this disclosure;
FIG. 6 illustrates a schematic plan view of a plurality of sub-lithographic patterns of the conductive lines shown in FIG. 5 in preparation for separating the conductive lines from one another, according to a specific example embodiment of this disclosure;
FIG. 7 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines shown in FIGS. 5 and 6 with portions of the conductive lines removed to separate the conductive lines from one another, according to a specific example embodiment of this disclosure;
figure 8 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths formed in a semiconductor die, according to another specific example embodiment of this disclosure;
figure 9 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths as shown in figure 8, ready to be separated into individual conductors in a semiconductor die, according to another specific example embodiment of this disclosure;
figure 10 illustrates a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths as shown in figures 8 and 9 after separation into independent conductors in a semiconductor die, according to another specific example embodiment of this disclosure;
figure 11 illustrates a schematic process flow diagram for forming a plurality of sub-lithographic patterns of conductive lines in a semiconductor die, according to a specific example embodiment of this disclosure; and
figure 12 illustrates a schematic process flow diagram for forming a plurality of sub-lithographic patterns of conductive lines in a semiconductor die, according to other specific example embodiments of this disclosure.
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
Detailed Description
According to the teachings of this disclosure, a spacer etch process may be used to create ultra-narrow conductive lines in a plurality of semiconductor dies. Sub-lithographic patterning of conductive lines can be produced in a fabrication process that is compatible with existing aluminum and copper back-end processing. A first dielectric may be deposited over each semiconductor die and at least one trench formed therein. A conductive film can be deposited onto the first dielectric and the surface of the at least one trench formed therein. Conductive film can be removed from the top face of the first dielectric and the bottom of the at least one trench, leaving only conductive film on the trench walls, whereby "fence conductors" can be formed therefrom, as described more fully below. Selected portions of the fence conductors may also be selectively "broken" (e.g., removed) during the aforementioned steps. Thereafter, the gaps between the conductive films on the trench walls may be filled with an insulating material. Thereafter, a top portion of the insulated gap fill may be removed (e.g., by polishing) to expose a top of the fence conductor. Portions of the fence conductors and surrounding insulating material may be removed (e.g., severed, connected, disconnected, etc.) at appropriate locations to produce a desired conductor pattern comprising the fence conductors. The trench depth may help determine one dimension (e.g., conductor height) of the fence conductor, and the thickness of the deposited conductive film may determine a second dimension (e.g., conductor width). The length of the fence conductors may be determined by where the continuous fence conductors are "broken" (e.g., the continuous fence conductors are separated from each other, the connection is severed between them, etc.).
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to fig. 1, a schematic plan view of a semiconductor integrated circuit wafer including a plurality of semiconductor dies is illustrated. The silicon wafer 102 may be diced into a plurality of semiconductor dies 104 for further processing to form planar transistors, diodes, and conductors on each of the plurality of semiconductor dies 104. After all of the circuitry has been fabricated on the plurality of semiconductor dies 104, the dies 104 are singulated (separated) and packaged into an integrated circuit (not shown).
Referring to figures 2 and 3, depicted are schematic elevational views of semiconductor fabrication steps for forming sub-lithographic patterns of conductive lines in a semiconductor die, according to specific example embodiments of this disclosure. A first step (a) in forming fence conductors is shown in fig. 2, wherein a first dielectric 212 may be deposited on the surface of the semiconductor substrate 210 for each of the plurality of semiconductor dies 104. In the next step (b), the first dielectric 212 may have at least one trench 214 etched therein to a depth that may help determine the dimensions (e.g., depth or height) of the desired fence conductor. At least one of the trenches 214 has a wall 216. In step (c), a conductive film 218 may be deposited over the exposed surface of the first dielectric 212 and the at least one trench 214. As will be readily apparent to those skilled in the art of semiconductor integrated circuit fabrication and having the benefit of this disclosure, conductive film 218 may be selected from many different types of conductive films, including metals, metal alloys, and non-metallic but conductive compounds that would be suitable for the conductive fences disclosed herein.
Referring now to fig. 3, in step (d), the conductive film 218 may be removed (e.g., etched) from the top surface of the first dielectric 212 and the bottom of the at least one trench 214, leaving only the conductive film 218 "vertical fences" on the vertical walls of the at least one trench 214. Rounding (not shown) may occur at the top portion of the conductive film 218. In step (e), second dielectric 212a may be deposited sufficiently thick over the exposed surfaces of first dielectric 212 and conductive film 218 on the vertical walls of at least one trench 214 to sufficiently fill the gap including at least one trench 214 and the remaining conductive film 218. In step (f), second dielectric 212a may be removed (e.g., polished) sufficiently deep to expose the top of fence conductor conductive film 218, allowing further electrical connection thereto.
The first dielectric layer 212 may be, for example but not limited to, SiN, SiO2、SiOxNyAnd the like. The second dielectric layer 212a may be, for example but not limited to, SiN, SiO2、SiOxNyAnd the like. The conductive film 218 can be, for example but not limited to, Al, Ta, TaN, Ti, TiN, Si, WSi, CoSi, and the like.
The thickness of the first dielectric layer 212 may be from about 100 nanometers to about 2000 nanometers. The thickness of the second dielectric layer 212a may be from about 100 nanometers to about 2000 nanometers. The thickness of the conductive film 218 may be from about 10 nanometers to about 1000 nanometers. The depth of the at least one trench 214 may be from about 100 nanometers to about 2000 nanometers. The width of the at least one trench 214 may be from about 100 nanometers to about 2000 nanometers.
Referring to figures 4 and 5, depicted are schematic plan views of a plurality of sub-lithographic patterns of conductive lines formed in a semiconductor die, according to a specific example embodiment of this disclosure. After removing the second dielectric 212a down to where the top of the fence conductor conductive film 218 is exposed (as shown in step (f) of fig. 3), the continuous conductive film 218 is ready for further processing. Continuous conductive film 218 (hereinafter referred to as "fence conductor" 218 or "conductive film" 218) must be separated in order to form useful independent circuit conductors. The plurality of fence conductors 218 shown in fig. 4 and 5 may represent conductors for an array of semiconductor transistors.
Referring to figure 6, depicted is a schematic plan view of a plurality of sub-lithographic patterns of conductive lines shown in figure 5 in preparation for separating the conductive lines from one another, according to a specific example embodiment of this disclosure. The ends of fence conductors 218, represented by reference numeral 620, will be broken (e.g., the fence conductors are separated, the connection is severed between them, etc.). The end 620 can be routed to a "safe" area on the die 104 and the end 620 can be "severed" (cut) with a removal process, such as, for example, but not limited to, an aggressive Reactive Ion Etch (RIE), wherein the end 620 is exposed and the remainder of the plurality of fence conductors 218 is protected (e.g., shielded) from the RIE.
Referring to figure 7, depicted is a schematic plan view of a plurality of secondary lithographic patterns with portions of the conductive lines removed to separate the conductive lines from one another, according to a specific example embodiment of this disclosure. After the end 620 has been removed, a third dielectric fill (not shown) may be required to fill the gap formed by the RIE process. Once this third dielectric fill has been completed, a Chemical Mechanical Planarization (CMP) process may be performed on the face of the die 104. The RIE mask may also be performed through-hole to selectively break fence conductor 218 at any location on die 104.
Referring to figure 8, depicted is a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths formed in a semiconductor die, according to another specific example embodiment of this disclosure. Fence conductor 218 as shown has been described more fully above. It is contemplated and within the scope of this disclosure that fence conductors 820 may be routed in as many different paths as desired, and fence conductors 820 are configured as conductors between active elements (e.g., transistors) on semiconductor die 104. The trenches used to form this pattern and the steps of forming the fence conductors 820 may be formed by appropriate masking (not shown) and processes the same as or similar to the process steps shown in fig. 2, 2A and 3 and their accompanying description as described more fully above.
Referring to figure 9, depicted is a schematic plan view of a plurality of sub-lithographic patterns of conductive lines having various routing paths as shown in figure 8, ready to be separated into individual conductors in a semiconductor die, according to another specific example embodiment of this disclosure. Fence conductors 820 can be separated (e.g., severed from connection to connection) at various locations on semiconductor die 104, generally represented by numeral 822. These discrete locations 822 may be implemented using a via type process, as is well known to those skilled in the art of semiconductor fabrication and having the benefit of the present disclosure.
Referring to figure 10, depicted is a schematic plan view of a plurality of sub-lithographic patterns of conductive lines with various routing paths as shown in figures 8 and 9 after separation into individual conductors in a semiconductor die, according to another specific example embodiment of this disclosure. The filled via-type fence separation can be deposited with another dielectric process, then the completely separated fence conductors 1020 can be further connected to active elements (e.g., transistors) and other connection nodes (not shown) in the semiconductor die 104.
Referring to figure 11, depicted is a schematic process flow diagram for forming a plurality of sub-lithographic patterns of conductive lines in a semiconductor die, according to a specific example embodiment of this disclosure. In step 1102, a first dielectric 212 may be deposited on a side of a semiconductor substrate (die) 210. In step 1104, at least one trench 214 may be etched into the dielectric 212. In step 1106, conductive film 218 can be deposited to a desired thickness over first dielectric 212 and at least one trench 214. In step 1108, the conductive film 218 may be etched from the top of the first dielectric 212 and the bottom of the at least one trench 214. In step 1110, a second dielectric 212a may be deposited over the first dielectric 212 and the remaining conductive film 218 on the walls of the at least one trench 214 so as to fill the gap therebetween. In step 1112, a portion of second dielectric 212a may be removed (e.g., polished away) until a top of conductive film 218 may be exposed for further processing thereof. In step 1114, portions of conductive film 218 may be separated (e.g., severed connections therebetween) so as to form independent fence conductors 1020 that may be used to interconnect active devices (not shown) in semiconductor die 104.
Referring to figure 12, depicted is a schematic process flow diagram of a plurality of sub-lithographic patterns for forming conductive lines in a semiconductor die, according to other specific example embodiments of this disclosure. In step 1102, a first dielectric 212 may be deposited on a side of a semiconductor substrate (die) 210. In step 1104, at least one trench 214 may be etched into the dielectric 212. In step 1106, conductive film 218 can be deposited to a desired thickness over first dielectric 212 and at least one trench 214. In step 1108, the conductive film 218 may be etched from the top of the first dielectric 212 and the bottom of the at least one trench 214. In step 1209, portions of conductive film 218 may be separated (e.g., severed from connection therebetween) so as to form independent fence conductors 1020 that may be used to interconnect active devices (not shown) in semiconductor die 104. In step 1110, a second dielectric 212a may be deposited over the first dielectric 212 and the remaining conductive film 218 on the walls of the at least one trench 214 so as to fill the gap therebetween. In step 1112, a portion of second dielectric 212a may be removed (e.g., polished away) until a top of conductive film 218 may be exposed for further processing thereof.
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.

Claims (11)

1. A method for forming fence conductors in a semiconductor integrated circuit die, the method comprising the steps of:
depositing a first dielectric on a face of a semiconductor substrate, the first dielectric having a predetermined thickness;
forming at least one trench in the first dielectric, the at least one trench having a depth less than the thickness of the first dielectric, wherein the at least one trench has a depth from 100 nanometers to 2000 nanometers;
depositing a conductive film on the first dielectric, including on walls and bottom of the at least one trench;
removing portions of the conductive film from a side of the first dielectric and the bottom of the at least one trench, wherein the conductive film remains only on the walls of the at least one trench;
depositing a second dielectric between the conductive films on the walls of the at least one trench; and
removing a portion of the second dielectric to expose a top portion of the conductive film on the walls of the at least one trench.
2. The method of claim 1, wherein after the step of removing a portion of the second dielectric to expose a top portion of the conductive film on the walls of the at least one trench, the method further comprises the step of separating portions of the conductive film on the walls of the at least one trench into independent fence conductors.
3. The method of claim 1, wherein after the step of removing portions of the conductive film from a face of the first dielectric and the bottom of the at least one trench, the method further comprises the step of separating portions of the conductive film on the walls of the at least one trench into independent fence conductors.
4. The method according to claim 2, wherein the step of separating portions of the conductive film comprises the step of separating portions of the conductive film by means of Reactive Ion Etching (RIE).
5. The method according to claim 4, further comprising the step of filling gaps formed by the RIE with dielectric and Chemical Mechanical Planarization (CMP) polishing thereof.
6. The method of any of claims 1-5, wherein the first dielectric has a thickness from 100 to 2000 nanometers.
7. The method of any one of claims 1-5, wherein the at least one trench has a width from 100 to 2000 nanometers.
8. The method of any of claims 1-5, wherein the conductive film has a thickness from 10 nanometers to 1000 nanometers.
9. The method of any of claims 1-5, wherein the second dielectric has a thickness from 100 to 2000 nanometers.
10. The method of any of claims 1-5, wherein the conductive film comprises an aluminum film.
11. The method of any of claims 1-5, wherein the conductive film is selected from the group consisting of: ta, TaN, Ti, TiN, Si, WSi and CoSi.
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US13/838,784 US8836128B1 (en) 2013-03-15 2013-03-15 Forming fence conductors in an integrated circuit
PCT/US2014/019729 WO2014149580A1 (en) 2013-03-15 2014-03-01 Forming fence conductors in an integrated circuit

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TWI619202B (en) 2018-03-21
EP2973678A1 (en) 2016-01-20
WO2014149580A1 (en) 2014-09-25
KR20150132213A (en) 2015-11-25
CN105051883A (en) 2015-11-11
US8836128B1 (en) 2014-09-16
EP2973678B1 (en) 2021-04-28
TW201448116A (en) 2014-12-16
US20140264891A1 (en) 2014-09-18

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