US20190229059A1 - Methods of patterning dielectric layers for metallization and related structures - Google Patents
Methods of patterning dielectric layers for metallization and related structures Download PDFInfo
- Publication number
- US20190229059A1 US20190229059A1 US16/369,050 US201916369050A US2019229059A1 US 20190229059 A1 US20190229059 A1 US 20190229059A1 US 201916369050 A US201916369050 A US 201916369050A US 2019229059 A1 US2019229059 A1 US 2019229059A1
- Authority
- US
- United States
- Prior art keywords
- metal
- layer
- spacer
- metal line
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Definitions
- the present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of patterning dielectric layers for metal line formation and fabrication of metallization layers integrated circuits.
- Metallization layers in integrated circuits allow for electrical connection between layers of integrated circuits and external devices.
- circuit sizes have continued to shrink, new methods for patterning metallization layers and forming metallization lines continue to be developed to overcome limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features.
- a method in an embodiment of the invention, includes forming a patterning stack over a dielectric layer, forming a masking layer over the patterning stack and a spacer patterning layer over the masking layer, and etching an opening in the spacer patterning layer to expose a portion of the masking layer overlying a dummy line of the patterning stack.
- the method further includes forming a first spacer and a second spacer on the exposed portion of the masking layer at sidewalls of the opening. The first spacer and the second spacer overlie and traverse respective first portions of the dummy line.
- the method further includes removing the spacer patterning layer and the masking layer selective to the patterning stack, the first spacer, and the second spacer to expose second portions of the dummy line, and removing the second portions of the dummy line selective to the first spacer and the second spacer to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer.
- a metal line is formed in the dielectric layer using the feature in the patterning stack. The metal line includes respective cuts at the first gap and the second gap in the feature in the patterning stack.
- a structure in another embodiment, includes a first metallization layer including a plurality of first metal lines and a metal island, a second metallization layer including a second metal line arranged or disposed below the first metallization layer, and a third metallization layer including a third metal line arranged or disposed above the first metallization layer.
- a first conductive via connects the metal island to the second metal line and a second conductive via connects the metal island to the third metal line.
- the first conductive via, second conductive via, and metal island provide electrical connectivity between the second metal line and third metal line.
- FIGS. 1-10 are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with embodiments of the invention.
- FIG. 1A is a top view of the structure in which FIG. 1 is taken generally along line 1 - 1 .
- FIG. 3A is a top view of the structure in which FIG. 3 is taken generally along line 3 - 3 .
- FIG. 6A is a top view of the structure in which FIG. 6 is taken generally along line 6 - 6 .
- FIG. 7A is a top view of the structure in which FIG. 7 is taken generally along line 7 - 7 .
- FIG. 8A is a top view of the structure in which FIG. 8 is taken generally along line 8 - 8 .
- FIG. 9A is a top view of the structure in which FIG. 9 is taken generally along line 9 - 9 .
- FIG. 10A is a top view of the structure in which FIG. 10 is taken generally along line 10 - 10 .
- FIG. 11 is a cross-sectional view of a structure at an alternative fabrication stage following FIG. 6 of a processing method in accordance with embodiments of the invention.
- FIG. 11A is a top view of the structure in which FIG. 11 is taken generally along line 11 - 11 .
- FIGS. 12 and 13 are cross-sectional views of the structure of FIGS. 1-10 at further fabrication stages of a processing method in accordance with embodiments of the invention.
- a structure 100 includes one or more lower circuit structure layers 105 , a dielectric layer 110 , and a patterning stack 120 that includes a hardmask layer 122 , a dielectric layer 124 , and dummy lines 125 , 126 .
- Dummy lines 125 , 126 may be formed by a lithography and etch process from a deposited layer of its material.
- Dummy lines 125 , 126 which may be composed of a sacrificial material, such as amorphous silicon (a-Si), are embedded in the dielectric layer 124 .
- Dummy lines 126 are patterned with large tip-to-tip spacings.
- Dielectric layer 124 may be composed of, for example, silicon dioxide deposited by plasma-enhanced chemical vapor deposition (PECVD) on the hardmask layer 122 and over the dummy lines 125 , 126 , and then polished to exposed the dummy lines 125 , 126 at the top surface of the dielectric layer 124 .
- Hardmask layer 122 may be composed, for example, of titanium nitride, titanium oxide, or other hardmask material.
- Dielectric layer 110 may be composed of a dielectric material, such as an oxide of silicon or a nitride of silicon, in which metallization lines are to be patterned using patterning stack 120 , as described in part below.
- a masking layer 130 and a spacer patterning layer 135 are formed over the patterning stack 120 .
- Masking layer 130 may be composed of a dielectric material, such as a nitride-based dielectric material, and spacer patterning layer 135 may be composed of a different dielectric material from masking layer 130 , such as an oxide-based dielectric material, so that masking layer 130 and spacer patterning layer 135 have differing etch selectivity properties.
- masking layer 130 may be composed of silicon nitride and spacer patterning layer 135 may be composed of silicon dioxide.
- Spacer patterning layer 135 may be formed to a selected thickness T 1 that may, in part, facilitate formation of spacers as described further below.
- Masking layer 130 may have a thickness T 2 that is less than the thickness T 1 of spacer patterning layer 135 .
- the thickness T 1 of spacer patterning layer 135 may, as described below, partially define a height of spacers 151 and 152 formed on sidewalls of an opening 137 ( FIG. 4 ) patterned in the spacer patterning layer 135 .
- a lithography stack 140 and a resist layer 144 are formed over spacer patterning layer 135 .
- Lithography stack 140 may include an organic spin-on hardmask (SOH) layer, a silicon oxynitride (SiON) hardmask layer, and an anti-reflective coating layer.
- the resist layer 144 is patterned to form an opening 145 , or multiple openings as described below, aligned over portions of dummy line 125 that is designated to be cut to provide small tip-to-tip spacings.
- the opening 145 exposes a portion of spacer patterning layer 135 to be etched and removed as described below.
- an opening 137 is etched in spacer patterning layer 135 .
- Opening 137 may be formed, for example, by a reactive ion etch (ME) process.
- the opening 137 may have a width dimension W that is about equal to twice a selected thickness T 3 of a conformal layer 150 to be formed over spacer patterning layer 135 plus a length L separating a spacer 151 from a spacer 152 (which are formed from conformal layer 150 ) as shown in FIG. 5 .
- selected thickness T 3 of conformal layer 150 may be about 5 nm, and length L separating spacers 151 and 152 may be about 15 nm, so that width W of opening 137 may be about 25 nm.
- the etching may be a selective etch process that is controlled to remove the exposed portion of spacer patterning layer 135 and to terminate on the material of the masking layer 130 .
- the opening 137 exposes a portion of masking layer 130 overlying a portion of dummy line 125 .
- the term “selective” in reference to a material removal process denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process.
- the opening 137 which is a single opening of relatively large dimensions in the spacer patterning layer 135 , may be used to form multiple closely-spaced cuts, as subsequently described, in contrast with conventional techniques that require multiple “colors” or stages of patterning to form closely-spaced cuts of small relative dimensions.
- the spacing between adjacent conventional cuts may be limited due to lithography resolution limits, which is mitigated through the use of spacers as described below.
- a conformal layer 150 is deposited on the spacer patterning layer 135 and over the sidewalls and base of the opening 137 in spacer patterning layer 135 .
- the sections of conformal layer 150 deposited on sidewalls of opening 137 define a spacer 151 and a spacer 152 .
- spacer 151 and spacer 152 may be included among a plurality of spacers that are arranged to form a “spacer ring” 155 on the sidewalls of the opening 137 .
- spacer 151 and spacer 152 may be included among a plurality of spacers that are arranged to form a “spacer ring” 155 on the sidewalls of the opening 137 .
- spacer 151 and spacer 152 overlie and traverse dummy line 125 .
- the thickness T 1 of spacer patterning layer 135 may define, at least in part, a height of spacers 151 and 152 formed on sidewalls of the opening 137 of spacer patterning layer 135 .
- the thickness T 3 of the conformal layer 150 may be selected to determine a thickness T 4 of spacers 151 and 152 and may further define, at least partially, a length L separating spacer 151 and spacer 152 .
- the thickness T 4 of spacer 151 and of spacer 152 may also define a size of gaps separating ends of metal lines formed in dielectric layer 110 , as described further below.
- a conformal layer 150 having a thickness T 3 of 5 nm may form spacers 151 , 152 having thickness T 4 of 5 nm, so that gaps formed between the ends of metal lines in dielectric layer 110 are also 5 nm.
- the length L separating spacer 151 and spacer 152 may be 15 nm or less, so that a resulting metal island 165 formed in dielectric layer 110 , as described further below, may have a length L m of 15 nm or less.
- the conformal layer 150 , and by extension, the spacers 151 and 152 , and masking layer 130 may be composed of the same material, for example a nitride-based dielectric material such as silicon nitride.
- conformal layer 150 is removed from over spacer patterning layer 135 , leaving spacer ring 155 , including spacer 151 and spacer 152 , disposed over the exposed portion of masking layer 130 .
- the conformal layer 150 may be removed, for example, by a selective anisotropic etch process, such as a reactive-ion etch (RIE) process, controlled to terminate when spacer patterning layer 135 is exposed by the etch.
- RIE reactive-ion etch
- a controlled anisotropic etch process allows for removal of the conformal layer 150 with minimal etching of spacers 151 , 152 .
- the conformal layer 150 deposited on sidewalls of the opening 137 in spacer patterning layer 135 may form the spacer ring 155 or ring-like spacer formation, including the spacer 151 and spacer 152 that overlie and traverse dummy line 125 .
- spacer patterning layer 135 and masking layer 130 are removed, which leaves spacers 151 and 152 disposed over different sections of the dummy line 125 .
- spacer 151 and spacer 152 overly and traverse dummy line 125 in a spaced apart fashion.
- Spacer patterning layer 135 may be removed by a selective etch process that selectively removes the material of spacer patterning layer 135 without etching either the masking layer 130 or spacers 151 , 152 .
- Masking layer 130 may be etched by a selective etch process controlled to remove masking layer 130 without fully etching or removing spacer 151 and spacer 152 , such as a reactive ion etching (RIE) process controlled to terminate when the dielectric layer 124 of patterning stack 120 is exposed by the etch process.
- RIE reactive ion etching
- dummy lines 125 and 126 are removed to expose underlying portions of hardmask layer 122 .
- Spacer 151 and spacer 152 protect underlying portions 127 , 128 of dummy line 125 from removal, so that in subsequent fabrication stages, as described below, the portions of hardmask layer 122 underlying the remaining portions 127 , 128 of dummy line 125 will remain unetched and form “cuts” or gaps in a final metallization line to be formed in dielectric layer 110 .
- the exposed portions of hardmask layer 122 are etched to form trenches in the hardmask layer 122 and expose portions of the dielectric layer 110 to be etched. Remaining portions of spacers 151 and 152 are also removed.
- the material of spacers 151 and 152 , as well as other spacers of spacer ring 155 may be removed by, for example, a selective etch process.
- Dielectric layer 124 may be removed via a separate selective etch process, as illustrated in FIG. 9 .
- dielectric layer 124 may remain to be etched during a subsequent etch of dielectric 110 , illustrated in FIG. 10 and further described below.
- Remaining portions 127 , 128 of dummy line 125 protect the underlying portions 122 a, 122 b of hardmask layer 122 and define gaps in the trenches formed in hardmask layer 122 .
- Dummy lines 125 , 126 may be removed, for example, by a selective anisotropic etch process such as a reactive ion etching (RIE) process.
- RIE reactive ion etching
- metallization trenches are formed in dielectric layer 110 using the trenches etched in hardmask layer 122 , and the trenches are filled with a conductive material to form metal lines 160 , 161 . Remaining portions of the hardmask layer 122 are removed, exposing the dielectric layer 110 .
- Metal line 165 resulting from the cuts or gaps defined by the spacers 151 and 152 as described above, may be considered a “metal island” as it is electrically isolated from surrounding metal lines 160 , 161 .
- the metal island 165 may have a length L m of 15 nm or less.
- the conductive material may be any conductive material, such as cobalt or ruthenium or copper or other conductive material used to form metal lines in a circuit structure.
- Cobalt may be a preferred conductive material for forming metal lines 160 , 161 and metal island 165 because cobalt may be used to form very short metal lines, such as metal islands of 15 nm or less, whereas copper metal lines generally must have a minimum length that is greater than 15 nm due to the material properties of copper and due to reliability issues during service and use of an integrated circuit structure.
- multiple sets of spacers 156 , 157 , 158 may be formed over dummy line 125 to define multiple sets of cuts or gaps in the dummy line 125 , and subsequently in metal lines formed in dielectric layer 110 .
- Multiple sets of spacers 156 , 157 , 158 may be formed via a lithographic etch process, as described in part above, in which multiple openings are etched in spacer patterning layer 135 and the conformal layer 150 subsequently deposited over spacer patterning layer 135 forms multiple spacers 156 , 157 , 158 .
- multiple wider openings similar to opening 137 in spacer patterning layer 135 depicted in FIGS. 4-5 , may be formed in spacer patterning layer 135 that result in the formation of multiple spacer rings or ring-like spacers similar to the single spacer ring illustrated in FIGS. 5-6A .
- multiple wider openings similar to opening 137 in spacer patterning layer 135 depicted in FIGS.
- spacer patterning layer 135 may be formed in spacer patterning layer 135 that result in the formation of multiple spacer rings, and an additional narrow opening may be formed in spacer patterning layer 135 that results in spacers 158 .
- the additional narrow opening in spacer patterning layer 135 may have a width dimension W N that is less than twice the thickness T 3 of the conformal layer 150 formed over the spacer patterning layer 135 , resulting in spacers 158 that merge into a single spacer block disposed over dummy line 125 .
- the single spacer block formed by spacers 158 then forms a single cut or gap in dummy line 125 .
- the dielectric layer 110 may be one metallization layer in a circuit structure 100 a and may be disposed above a lower metallization layer 170 having a plurality of metal lines 171 and below an upper metallization layer 175 having a plurality of metal lines 176 .
- a lower metallization layer 170 may be formed first and a via 182 formed to connect to one metal line 171 in lower metallization layer 170 .
- the dielectric layer 110 may then be formed, as described above, with a metal island 165 aligned with the via 182 connected to metal line 171 .
- Conductive via 182 may be formed, for example, by etching a hole through the dielectric material of dielectric layer 110 , prior to formation of metal lines 160 , 161 , and metal island 165 , and subsequently filling the hole with a conductive material such as cobalt, ruthenium, or copper.
- the conductive via 182 may be filled along with metal lines 160 , 161 , and metal island 165 in the same processing step or may be filled prior to forming metal lines 160 , 161 , and metal island 165 as described above. As depicted in FIG.
- another conductive via 184 may then be formed that connects to metal island 165 , and the upper metallization layer 175 may then be formed over dielectric layer 110 with one metal line 176 in upper metallization layer 175 aligned to and connecting with the other conductive via 184 .
- Conductive via 184 may be formed by similar processes as for forming via 182 .
- the circuit structure 100 a formed thus has an interconnection between upper metallization layer 175 and lower metallization layer 170 , wherein dielectric layer 110 separates the upper metallization layer 175 and lower metallization layer 170 .
- Conductive vias 182 and 184 in conjunction with metal island 165 formed in dielectric layer 110 , form an extended via or “super via” that permits interconnection between metal lines of non-adjacent metallization levels in circuit structure 100 a.
- the metal island 165 formed as described herein allows for efficient conductive connection between conductive vias 182 and 184 as metal island 165 may be formed to have a size substantially equal to a size of conductive vias 182 and 184 so as to minimize area losses.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- references herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction.
- Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
- a feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Abstract
Description
- The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of patterning dielectric layers for metal line formation and fabrication of metallization layers integrated circuits.
- Metallization layers in integrated circuits allow for electrical connection between layers of integrated circuits and external devices. As circuit sizes have continued to shrink, new methods for patterning metallization layers and forming metallization lines continue to be developed to overcome limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features.
- In an embodiment of the invention, a method includes forming a patterning stack over a dielectric layer, forming a masking layer over the patterning stack and a spacer patterning layer over the masking layer, and etching an opening in the spacer patterning layer to expose a portion of the masking layer overlying a dummy line of the patterning stack. The method further includes forming a first spacer and a second spacer on the exposed portion of the masking layer at sidewalls of the opening. The first spacer and the second spacer overlie and traverse respective first portions of the dummy line. The method further includes removing the spacer patterning layer and the masking layer selective to the patterning stack, the first spacer, and the second spacer to expose second portions of the dummy line, and removing the second portions of the dummy line selective to the first spacer and the second spacer to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature in the patterning stack. The metal line includes respective cuts at the first gap and the second gap in the feature in the patterning stack.
- In another embodiment of the invention, a structure includes a first metallization layer including a plurality of first metal lines and a metal island, a second metallization layer including a second metal line arranged or disposed below the first metallization layer, and a third metallization layer including a third metal line arranged or disposed above the first metallization layer. A first conductive via connects the metal island to the second metal line and a second conductive via connects the metal island to the third metal line. The first conductive via, second conductive via, and metal island provide electrical connectivity between the second metal line and third metal line.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIGS. 1-10 are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with embodiments of the invention. -
FIG. 1A is a top view of the structure in whichFIG. 1 is taken generally along line 1-1. -
FIG. 3A is a top view of the structure in whichFIG. 3 is taken generally along line 3-3. -
FIG. 6A is a top view of the structure in whichFIG. 6 is taken generally along line 6-6. -
FIG. 7A is a top view of the structure in whichFIG. 7 is taken generally along line 7-7. -
FIG. 8A is a top view of the structure in whichFIG. 8 is taken generally along line 8-8. -
FIG. 9A is a top view of the structure in whichFIG. 9 is taken generally along line 9-9. -
FIG. 10A is a top view of the structure in whichFIG. 10 is taken generally along line 10-10. -
FIG. 11 is a cross-sectional view of a structure at an alternative fabrication stage followingFIG. 6 of a processing method in accordance with embodiments of the invention. -
FIG. 11A is a top view of the structure in whichFIG. 11 is taken generally along line 11-11. -
FIGS. 12 and 13 are cross-sectional views of the structure ofFIGS. 1-10 at further fabrication stages of a processing method in accordance with embodiments of the invention. - With reference to
FIGS. 1 and 1A and in accordance with embodiments of the invention, astructure 100 includes one or more lowercircuit structure layers 105, adielectric layer 110, and apatterning stack 120 that includes ahardmask layer 122, adielectric layer 124, anddummy lines Dummy lines lines dielectric layer 124.Dummy lines 126 are patterned with large tip-to-tip spacings. -
Dielectric layer 124 may be composed of, for example, silicon dioxide deposited by plasma-enhanced chemical vapor deposition (PECVD) on thehardmask layer 122 and over thedummy lines dummy lines dielectric layer 124.Hardmask layer 122 may be composed, for example, of titanium nitride, titanium oxide, or other hardmask material.Dielectric layer 110 may be composed of a dielectric material, such as an oxide of silicon or a nitride of silicon, in which metallization lines are to be patterned usingpatterning stack 120, as described in part below. - With reference to
FIG. 2 in which like reference numerals refer to like features inFIGS. 1 and 1A and at a subsequent fabrication stage of the processing method, amasking layer 130 and aspacer patterning layer 135 are formed over thepatterning stack 120.Masking layer 130 may be composed of a dielectric material, such as a nitride-based dielectric material, andspacer patterning layer 135 may be composed of a different dielectric material frommasking layer 130, such as an oxide-based dielectric material, so thatmasking layer 130 andspacer patterning layer 135 have differing etch selectivity properties. For example,masking layer 130 may be composed of silicon nitride andspacer patterning layer 135 may be composed of silicon dioxide.Spacer patterning layer 135 may be formed to a selected thickness T1 that may, in part, facilitate formation of spacers as described further below.Masking layer 130 may have a thickness T2 that is less than the thickness T1 ofspacer patterning layer 135. The thickness T1 ofspacer patterning layer 135 may, as described below, partially define a height ofspacers FIG. 4 ) patterned in thespacer patterning layer 135. - With reference to
FIGS. 3 and 3A and in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of the processing method, alithography stack 140 and aresist layer 144 are formed overspacer patterning layer 135.Lithography stack 140 may include an organic spin-on hardmask (SOH) layer, a silicon oxynitride (SiON) hardmask layer, and an anti-reflective coating layer. Theresist layer 144 is patterned to form anopening 145, or multiple openings as described below, aligned over portions ofdummy line 125 that is designated to be cut to provide small tip-to-tip spacings. Theopening 145 exposes a portion ofspacer patterning layer 135 to be etched and removed as described below. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIGS. 3 and 3A and at a subsequent fabrication stage of the processing method, anopening 137 is etched inspacer patterning layer 135.Opening 137 may be formed, for example, by a reactive ion etch (ME) process. Theopening 137 may have a width dimension W that is about equal to twice a selected thickness T3 of aconformal layer 150 to be formed overspacer patterning layer 135 plus a length L separating aspacer 151 from a spacer 152 (which are formed from conformal layer 150) as shown inFIG. 5 . For example, selected thickness T3 ofconformal layer 150 may be about 5 nm, and lengthL separating spacers spacer patterning layer 135 and to terminate on the material of themasking layer 130. The opening 137 exposes a portion ofmasking layer 130 overlying a portion ofdummy line 125. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. - The opening 137, which is a single opening of relatively large dimensions in the
spacer patterning layer 135, may be used to form multiple closely-spaced cuts, as subsequently described, in contrast with conventional techniques that require multiple “colors” or stages of patterning to form closely-spaced cuts of small relative dimensions. In addition, the spacing between adjacent conventional cuts may be limited due to lithography resolution limits, which is mitigated through the use of spacers as described below. - With reference to
FIG. 5 in which like reference numerals refer to like features inFIG. 4 and at a subsequent fabrication stage of the processing method, aconformal layer 150 is deposited on thespacer patterning layer 135 and over the sidewalls and base of theopening 137 inspacer patterning layer 135. The sections ofconformal layer 150 deposited on sidewalls of opening 137 define aspacer 151 and aspacer 152. As depicted and described below inFIG. 6A ,spacer 151 andspacer 152 may be included among a plurality of spacers that are arranged to form a “spacer ring” 155 on the sidewalls of theopening 137. As also described and depicted below inFIG. 6A ,spacer 151 andspacer 152 overlie and traversedummy line 125. The thickness T1 ofspacer patterning layer 135 may define, at least in part, a height ofspacers opening 137 ofspacer patterning layer 135. The thickness T3 of theconformal layer 150 may be selected to determine a thickness T4 ofspacers L separating spacer 151 andspacer 152. The thickness T4 ofspacer 151 and ofspacer 152 may also define a size of gaps separating ends of metal lines formed indielectric layer 110, as described further below. For example, aconformal layer 150 having a thickness T3 of 5 nm may formspacers dielectric layer 110 are also 5 nm. The lengthL separating spacer 151 andspacer 152 may be 15 nm or less, so that a resultingmetal island 165 formed indielectric layer 110, as described further below, may have a length Lm of 15 nm or less. Theconformal layer 150, and by extension, thespacers masking layer 130 may be composed of the same material, for example a nitride-based dielectric material such as silicon nitride. - With reference to
FIGS. 6 and 6A in which like reference numerals refer to like features inFIG. 5 and at a subsequent fabrication stage of the processing method,conformal layer 150 is removed from overspacer patterning layer 135, leavingspacer ring 155, includingspacer 151 andspacer 152, disposed over the exposed portion ofmasking layer 130. Theconformal layer 150 may be removed, for example, by a selective anisotropic etch process, such as a reactive-ion etch (RIE) process, controlled to terminate whenspacer patterning layer 135 is exposed by the etch. A controlled anisotropic etch process allows for removal of theconformal layer 150 with minimal etching ofspacers FIG. 6A illustrates, theconformal layer 150 deposited on sidewalls of theopening 137 inspacer patterning layer 135 may form thespacer ring 155 or ring-like spacer formation, including thespacer 151 andspacer 152 that overlie and traversedummy line 125. - With reference to
FIGS. 7 and 7A in which like reference numerals refer to like features inFIGS. 6 and 6A and at a subsequent fabrication stage of the processing method,spacer patterning layer 135 andmasking layer 130 are removed, which leavesspacers dummy line 125. AsFIGS. 7 and 7A show, spacer 151 andspacer 152 overly and traversedummy line 125 in a spaced apart fashion.Spacer patterning layer 135 may be removed by a selective etch process that selectively removes the material ofspacer patterning layer 135 without etching either themasking layer 130 orspacers layer 130 may be etched by a selective etch process controlled to removemasking layer 130 without fully etching or removingspacer 151 andspacer 152, such as a reactive ion etching (RIE) process controlled to terminate when thedielectric layer 124 ofpatterning stack 120 is exposed by the etch process. - With reference to
FIGS. 8 and 8A in which like reference numerals refer to like features inFIGS. 7 and 7A and at a subsequent fabrication stage of the processing method,dummy lines hardmask layer 122.Spacer 151 andspacer 152 protectunderlying portions dummy line 125 from removal, so that in subsequent fabrication stages, as described below, the portions ofhardmask layer 122 underlying the remainingportions dummy line 125 will remain unetched and form “cuts” or gaps in a final metallization line to be formed indielectric layer 110. - With reference to
FIGS. 9 and 9A in which like reference numerals refer to like features inFIGS. 8 and 8A and at a subsequent fabrication stage of the processing method, the exposed portions ofhardmask layer 122 are etched to form trenches in thehardmask layer 122 and expose portions of thedielectric layer 110 to be etched. Remaining portions ofspacers spacers spacer ring 155, may be removed by, for example, a selective etch process.Dielectric layer 124 may be removed via a separate selective etch process, as illustrated inFIG. 9 . Alternatively,dielectric layer 124 may remain to be etched during a subsequent etch ofdielectric 110, illustrated inFIG. 10 and further described below. Remainingportions dummy line 125 protect theunderlying portions 122 a, 122 b ofhardmask layer 122 and define gaps in the trenches formed inhardmask layer 122.Dummy lines - With reference to
FIGS. 10 and 10A in which like reference numerals refer to like features inFIGS. 9 and 9A and at a subsequent fabrication stage of the processing method, metallization trenches are formed indielectric layer 110 using the trenches etched inhardmask layer 122, and the trenches are filled with a conductive material to formmetal lines hardmask layer 122 are removed, exposing thedielectric layer 110.Metal line 165, resulting from the cuts or gaps defined by thespacers metal lines metal island 165 may have a length Lm of 15 nm or less. The conductive material may be any conductive material, such as cobalt or ruthenium or copper or other conductive material used to form metal lines in a circuit structure. Cobalt may be a preferred conductive material for formingmetal lines metal island 165 because cobalt may be used to form very short metal lines, such as metal islands of 15 nm or less, whereas copper metal lines generally must have a minimum length that is greater than 15 nm due to the material properties of copper and due to reliability issues during service and use of an integrated circuit structure. - With reference to
FIGS. 11 and 11A in which like reference numerals refer to like features inFIGS. 7 and 7A in a further embodiment of the processing method, multiple sets ofspacers dummy line 125 to define multiple sets of cuts or gaps in thedummy line 125, and subsequently in metal lines formed indielectric layer 110. Multiple sets ofspacers spacer patterning layer 135 and theconformal layer 150 subsequently deposited overspacer patterning layer 135 formsmultiple spacers dummy line 125, multiple wider openings, similar to opening 137 inspacer patterning layer 135 depicted inFIGS. 4-5 , may be formed inspacer patterning layer 135 that result in the formation of multiple spacer rings or ring-like spacers similar to the single spacer ring illustrated inFIGS. 5-6A . In embodiments in which an odd number of cuts or gaps indummy line 125 are needed, multiple wider openings, similar to opening 137 inspacer patterning layer 135 depicted inFIGS. 4-5 , may be formed inspacer patterning layer 135 that result in the formation of multiple spacer rings, and an additional narrow opening may be formed inspacer patterning layer 135 that results inspacers 158. The additional narrow opening inspacer patterning layer 135 may have a width dimension WN that is less than twice the thickness T3 of theconformal layer 150 formed over thespacer patterning layer 135, resulting inspacers 158 that merge into a single spacer block disposed overdummy line 125. The single spacer block formed byspacers 158 then forms a single cut or gap indummy line 125. - With reference to
FIGS. 12 and 13 in which like reference numerals refer to like features inFIGS. 1-10A and in a further embodiment of the processing method, thedielectric layer 110, includingmetal lines metal island 165, may be one metallization layer in acircuit structure 100a and may be disposed above alower metallization layer 170 having a plurality ofmetal lines 171 and below anupper metallization layer 175 having a plurality ofmetal lines 176. As depicted inFIG. 12 , alower metallization layer 170 may be formed first and a via 182 formed to connect to onemetal line 171 inlower metallization layer 170. Thedielectric layer 110 may then be formed, as described above, with ametal island 165 aligned with the via 182 connected tometal line 171. Conductive via 182 may be formed, for example, by etching a hole through the dielectric material ofdielectric layer 110, prior to formation ofmetal lines metal island 165, and subsequently filling the hole with a conductive material such as cobalt, ruthenium, or copper. The conductive via 182 may be filled along withmetal lines metal island 165 in the same processing step or may be filled prior to formingmetal lines metal island 165 as described above. As depicted inFIG. 13 , another conductive via 184 may then be formed that connects tometal island 165, and theupper metallization layer 175 may then be formed overdielectric layer 110 with onemetal line 176 inupper metallization layer 175 aligned to and connecting with the other conductive via 184. Conductive via 184 may be formed by similar processes as for forming via 182. Thecircuit structure 100a formed thus has an interconnection betweenupper metallization layer 175 andlower metallization layer 170, whereindielectric layer 110 separates theupper metallization layer 175 andlower metallization layer 170.Conductive vias metal island 165 formed indielectric layer 110, form an extended via or “super via” that permits interconnection between metal lines of non-adjacent metallization levels incircuit structure 100a. Themetal island 165 formed as described herein allows for efficient conductive connection betweenconductive vias metal island 165 may be formed to have a size substantially equal to a size ofconductive vias - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
- A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/369,050 US20190229059A1 (en) | 2018-01-02 | 2019-03-29 | Methods of patterning dielectric layers for metallization and related structures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/860,193 US10347583B1 (en) | 2018-01-02 | 2018-01-02 | Methods of patterning dielectric layers for metallization and related structures |
US16/369,050 US20190229059A1 (en) | 2018-01-02 | 2019-03-29 | Methods of patterning dielectric layers for metallization and related structures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/860,193 Division US10347583B1 (en) | 2018-01-02 | 2018-01-02 | Methods of patterning dielectric layers for metallization and related structures |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190229059A1 true US20190229059A1 (en) | 2019-07-25 |
Family
ID=66817060
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/860,193 Expired - Fee Related US10347583B1 (en) | 2018-01-02 | 2018-01-02 | Methods of patterning dielectric layers for metallization and related structures |
US16/369,050 Abandoned US20190229059A1 (en) | 2018-01-02 | 2019-03-29 | Methods of patterning dielectric layers for metallization and related structures |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/860,193 Expired - Fee Related US10347583B1 (en) | 2018-01-02 | 2018-01-02 | Methods of patterning dielectric layers for metallization and related structures |
Country Status (3)
Country | Link |
---|---|
US (2) | US10347583B1 (en) |
DE (1) | DE102019100014B4 (en) |
TW (1) | TWI706511B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11114153B2 (en) * | 2019-12-30 | 2021-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM devices with reduced coupling capacitance |
US20230197609A1 (en) * | 2021-12-17 | 2023-06-22 | Sukru Yemenicioglu | Iso-level vias for advanced integrated circuit structure fabrication |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100467020B1 (en) * | 2002-07-26 | 2005-01-24 | 삼성전자주식회사 | Semiconductor Device With Self-Aligned Junction Contact Hole And Method Of Fabricating The Same |
US9437443B2 (en) | 2013-06-12 | 2016-09-06 | Globalfoundries Inc. | Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides |
US8932955B1 (en) * | 2013-09-04 | 2015-01-13 | Sandisk Technologies Inc. | Triple patterning NAND flash memory with SOC |
US9406511B2 (en) * | 2014-07-10 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double patterning |
US9972603B2 (en) | 2015-12-29 | 2018-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal-ring structure for stacking integrated circuits |
US9607893B1 (en) | 2016-07-06 | 2017-03-28 | Globalfoundries Inc. | Method of forming self-aligned metal lines and vias |
US9818641B1 (en) | 2016-09-21 | 2017-11-14 | Globalfoundries Inc. | Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines |
US9818640B1 (en) | 2016-09-21 | 2017-11-14 | Globalfoundries Inc. | Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines |
-
2018
- 2018-01-02 US US15/860,193 patent/US10347583B1/en not_active Expired - Fee Related
- 2018-11-30 TW TW107142968A patent/TWI706511B/en not_active IP Right Cessation
-
2019
- 2019-01-02 DE DE102019100014.9A patent/DE102019100014B4/en active Active
- 2019-03-29 US US16/369,050 patent/US20190229059A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW201937660A (en) | 2019-09-16 |
DE102019100014B4 (en) | 2023-01-19 |
US10347583B1 (en) | 2019-07-09 |
DE102019100014A1 (en) | 2019-07-04 |
US20190206795A1 (en) | 2019-07-04 |
TWI706511B (en) | 2020-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10192780B1 (en) | Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks | |
US9472690B2 (en) | Deep trench capacitor manufactured by streamlined process | |
US10366917B2 (en) | Methods of patterning variable width metallization lines | |
US10395926B1 (en) | Multiple patterning with mandrel cuts formed using a block mask | |
KR20160122695A (en) | Spacer enabled active isolation for an integrated circuit device | |
US10685874B1 (en) | Self-aligned cuts in an interconnect structure | |
US10446395B1 (en) | Self-aligned multiple patterning processes with layered mandrels | |
US10236256B2 (en) | Pre-spacer self-aligned cut formation | |
US20190229059A1 (en) | Methods of patterning dielectric layers for metallization and related structures | |
CN109411409B (en) | Metallization layer and method for manufacturing same | |
US10566195B2 (en) | Multiple patterning with variable space mandrel cuts | |
US10833149B2 (en) | Capacitors | |
TWI633625B (en) | Forming fence conductors using spacer etched trenches | |
WO2022122294A1 (en) | Self-aligned top via | |
KR100327580B1 (en) | Method for forming metal line of a semiconductor device | |
CN105051883B (en) | Forming fence conductors in an integrated circuit | |
US9583435B2 (en) | Forming fence conductors using spacer etched trenches | |
KR100372817B1 (en) | method of contacting metal lines of semiconductor device | |
KR20010004008A (en) | Method for forming metal wiring of semiconductor device having Air-gap | |
KR20030054745A (en) | Method for Forming Contact Area in Semiconductor Device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BOUCHE, GUILLAUME;REEL/FRAME:048737/0124 Effective date: 20180102 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |