JP2012094840A - Method of manufacturing package substrate for mounting semiconductor element - Google Patents

Method of manufacturing package substrate for mounting semiconductor element Download PDF

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JP2012094840A
JP2012094840A JP2011207249A JP2011207249A JP2012094840A JP 2012094840 A JP2012094840 A JP 2012094840A JP 2011207249 A JP2011207249 A JP 2011207249A JP 2011207249 A JP2011207249 A JP 2011207249A JP 2012094840 A JP2012094840 A JP 2012094840A
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metal foil
carrier
carrier metal
multilayer
plating
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JP5896200B2 (en
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Tadashi Tamura
匡史 田村
Manabu Sugibayashi
学 杉林
Kuniji Suzuki
邦司 鈴木
Kiyoo Hattori
清男 服部
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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Priority to CN201180045417.4A priority patent/CN103119710B/en
Priority to KR1020137005647A priority patent/KR101466524B1/en
Priority to TW100135443A priority patent/TWI601245B/en
Priority to PCT/JP2011/072423 priority patent/WO2012043742A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a package substrate for mounting a semiconductor element in which the yield can be enhanced by reducing adhesion of resin powder, miniaturization and adhesion are ensured by forming an embedded circuit not causing undercut, an outer layer circuit can be formed for an insulation layer on the surface, and various metal structures such as bumps or pillars can be formed.SOLUTION: The method of manufacturing a package substrate for mounting a semiconductor element includes a step for forming a core substrate 17 by laminating a base material 16, a step for physically peeling the first carrier metal foil 10 of a multilayer metal foil 9, a step for performing first pattern plating on a second carrier metal foil 11, a step for forming a laminate by laminating an insulation layer on the first pattern plating, a step for separating the laminate from the core substrate 17 together with the second carrier metal foil 11, and a step for forming an etching resist on the second carrier metal foil 11 of the laminate thus separated and then etching the resist.

Description

本発明は、高密度化が可能な半導体素子搭載用パッケージ基板の製造方法に関する。   The present invention relates to a method of manufacturing a package substrate for mounting a semiconductor element capable of increasing the density.

電子部品の小型化や高密度化に伴い、システム化された半導体素子搭載用パッケージ基板（以下、「パッケージ基板」ということがある。）が求められている。ＳｉＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）に代表されるＰｏＰ（Ｐａｃｋａｇｅ ｏｎ Ｐａｃｋａｇｅ）では、近年、一つのパッケージ基板に半導体素子を複数積み重ねたパッケージが主流となってきている。これに伴い、ＰｏＰ用のパッケージ基板では、半導体素子との接続端子を高密度に配置する必要が生じ、外層回路の微細化が要求されている。   With downsizing and increasing the density of electronic components, a systemized package board for mounting semiconductor elements (hereinafter sometimes referred to as “package board”) is required. In PoP (Package on Package) represented by SiP (System in Package), in recent years, a package in which a plurality of semiconductor elements are stacked on one package substrate has become the mainstream. Along with this, in the PoP package substrate, it is necessary to arrange the connection terminals with the semiconductor elements at high density, and the miniaturization of the outer layer circuit is required.

微細な外層回路を形成する方法としては、厚さが２μｍ程度の薄い銅箔を備えた絶縁基材に層間接続孔を設け、薄い銅箔上及び層間接続孔内に厚さ０．１μｍ程度の薄付け無電解銅めっきを行い、その上にめっきレジストを形成して外層回路となる部分をパターン電気めっきで厚付けした後、めっきレジストを除去し、全面をエッチングすることによって、パターン電気めっきしていない部分のみ（即ち、導体の薄い部分のみ）を除去して外層回路を形成する方法がある（特許文献１）。   As a method for forming a fine outer layer circuit, an interlayer connection hole is provided in an insulating base material provided with a thin copper foil having a thickness of about 2 μm, and a thickness of about 0.1 μm is formed on the thin copper foil and in the interlayer connection hole. Perform thin electroless copper plating, form a plating resist on it, thicken the part that will become the outer layer circuit by pattern electroplating, then remove the plating resist and etch the entire surface to perform pattern electroplating There is a method of forming an outer layer circuit by removing only a portion that is not (that is, only a thin portion of a conductor) (Patent Document 1).

また、物理的に剥離可能なキャリア銅箔付き極薄銅箔（厚さ１〜５μｍ）のキャリア銅箔面に絶縁樹脂を設けて支持基板を形成し、この支持基板の極薄銅箔上にパターン銅めっきにより外層回路となる導体パターンを形成し、その上に絶縁樹脂や層間接続を形成した後、キャリア銅箔を含む支持基板を物理的に剥離し、さらに極薄銅箔をエッチングにより除去することで微細な外層回路を形成する方法がある（特許文献２）。   In addition, a support substrate is formed by providing an insulating resin on the carrier copper foil surface of an ultrathin copper foil (thickness 1 to 5 μm) with a carrier copper foil that can be physically peeled, and on the ultrathin copper foil of the support substrate After forming a conductor pattern to be an outer layer circuit by pattern copper plating, forming an insulating resin and interlayer connection on it, the support substrate including the carrier copper foil is physically peeled off, and the ultrathin copper foil is removed by etching Thus, there is a method of forming a fine outer layer circuit (Patent Document 2).

さらに、キャリア膜の中間膜の表面に所定パターンの配線膜を形成し、配線膜の表面にパターンめっきにより導電性ピラーを形成し、層間絶縁膜を形成した配線部材を２つ用意し、導電性ピラーの先端面同士が接するように積層一体化し、中間膜をエッチングストップ層としてキャリア膜をエッチング除去し、さらに中間膜をエッチングにより除去することで配線を形成する方法がある（特許文献３）。   In addition, a wiring film having a predetermined pattern is formed on the surface of the intermediate film of the carrier film, conductive pillars are formed on the surface of the wiring film by pattern plating, and two wiring members on which an interlayer insulating film is formed are prepared. There is a method in which wiring is formed by stacking and integrating so that the end surfaces of pillars are in contact with each other, removing the carrier film by etching using the intermediate film as an etching stop layer, and further removing the intermediate film by etching (Patent Document 3).

特開２００４−１４０１７６号公報JP 2004-140176 A 特開２００５−１０１１３７号公報JP 2005-101137 A 特開２００６−１３５２７７号公報JP 2006-135277 A

しかしながら、特許文献１の方法では、パターン電気銅めっきの給電層として、絶縁基材上に設けられた薄い銅箔と薄付け無電解銅めっきとを用いるため、パターン電気めっき後に全面をエッチングする際には、給電層（薄い銅箔と薄付け無電解銅めっきとを合わせた層）の厚さ分のエッチングが必要になる。このエッチングによって給電層を除去する際に、アンダーカットが生じる傾向がある。このため、形成される外層回路と絶縁基材との実質的な密着幅が減少し、例えばライン／スペースが１５μｍ／１５μｍ以下レベルの微細な外層回路の形成は難しい問題があった。   However, in the method of Patent Document 1, since the thin copper foil provided on the insulating substrate and the thin electroless copper plating are used as the power feeding layer of the pattern electrolytic copper plating, the entire surface is etched after the pattern electroplating. For this, etching for the thickness of the power feeding layer (a layer obtained by combining a thin copper foil and a thin electroless copper plating) is required. When the power feeding layer is removed by this etching, an undercut tends to occur. For this reason, the substantial adhesion width between the formed outer layer circuit and the insulating substrate is reduced, and there is a problem that it is difficult to form a fine outer layer circuit having a line / space level of 15 μm / 15 μm or less, for example.

また、特許文献２の方法では、キャリア銅箔付きの極薄銅箔（厚さ１〜５μｍ）面に絶縁樹脂を積層して支持基板を形成する際、支持基板の表面側に露出した極薄銅箔の表面に絶縁樹脂の樹脂粉が付着することがあり、この極薄銅箔に付着した樹脂粉が、極薄銅箔を加工して微細な外層回路を形成する際に、歩留まり低下の要因になる可能性がある。   Further, in the method of Patent Document 2, when an insulating resin is laminated on the surface of an ultrathin copper foil (thickness 1 to 5 μm) with a carrier copper foil, the ultrathin exposed on the surface side of the support substrate is formed. Resin powder of insulating resin may adhere to the surface of the copper foil, and the resin powder attached to the ultrathin copper foil may reduce the yield when processing the ultrathin copper foil to form a fine outer layer circuit. It can be a factor.

また、特許文献３の方法は、中間膜をエッチングストップ層としてキャリア膜をエッチング除去し、さらに中間膜をエッチングにより除去するが、エッチングストップ層にピンホール等の欠陥が生じ易いため歩留まりが低下する可能性があり、またエッチングを２段階に行うため、形成された外層回路の表面の凹凸が増大し、半導体素子との接続信頼性が低下する可能性がある。   In the method of Patent Document 3, the carrier film is removed by etching using the intermediate film as an etching stop layer, and further the intermediate film is removed by etching. However, the yield is lowered because defects such as pinholes are likely to occur in the etching stop layer. In addition, since etching is performed in two stages, the unevenness on the surface of the formed outer layer circuit may increase, and the connection reliability with the semiconductor element may decrease.

また、半導体素子とパッケージ基板の接続端子との電気的接続は、フリップチップ接続やワイヤーボンディング接続が用いられるが、接続端子が微細になるほど接続信頼性に対する表面凹凸（絶縁層と接続端子との段差）の影響が増大する傾向がある。このため、接続端子となる外層回路と絶縁層との平坦化が要求されている。一方で、搭載する半導体素子との接続形態によっては、バンプやピラー等の形成が要求される場合もある。   In addition, flip chip connection or wire bonding connection is used for the electrical connection between the semiconductor element and the connection terminal of the package substrate. However, as the connection terminal becomes finer, the surface unevenness with respect to connection reliability (step difference between the insulating layer and the connection terminal). ) Tends to increase. For this reason, flattening of the outer layer circuit to be the connection terminal and the insulating layer is required. On the other hand, depending on the connection form with the semiconductor element to be mounted, formation of bumps, pillars, etc. may be required.

本発明は、上記問題点に鑑みなされたものであり、樹脂粉の付着を抑制することにより歩留まり向上が可能であり、アンダーカットが生じない埋め込み回路を形成することにより微細で密着力があり、表面が絶縁層に対して平坦な外層回路が形成可能であり、また、任意の箇所に立体回路を形成することによりバンプやピラー等の種々の金属構成を形成可能な半導体素子搭載用パッケージ基板の製造方法を提供する。   The present invention has been made in view of the above problems, yield can be improved by suppressing the adhesion of resin powder, there is fine and adhesive force by forming an embedded circuit without undercut, An outer layer circuit whose surface is flat with respect to the insulating layer can be formed, and a package substrate for mounting a semiconductor element capable of forming various metal structures such as bumps and pillars by forming a three-dimensional circuit at an arbitrary position. A manufacturing method is provided.

本発明は、以下のものに関する。
（１） 第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属箔を物理的に剥離する工程と、前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、前記剥離した積層体の第２キャリア金属箔上にエッチングレジストを形成してエッチングを行い、前記第１のパターンめっき上または前記絶縁層上に立体回路を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
（２） 第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属箔を物理的に剥離する工程と、前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、前記剥離した積層体の第２キャリア金属箔上に第２のパターンめっきを行う工程と、前記第２のパターンめっきを行った部分以外の第２キャリア金属箔をエッチングにより除去し、前記第１のパターンめっき上または前記絶縁層上に立体回路を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
（３） 第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属層を物理的に剥離する工程と、前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、前記分離した積層体の第２キャリア金属箔を除去して、前記第１のパターンめっきを前記絶縁層の表面に露出させる工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
（４） 上記（１）から（３）の何れかにおいて、多層金属箔は、第２キャリア金属箔とベース金属箔との間の剥離強度が、第１キャリア金属箔と第２キャリア金属箔との間の剥離強度よりも大きく形成された多層金属箔である半導体素子搭載用パッケージ基板の製造方法。
（５） 上記（１）から（５）の何れかにおいて、多層金属箔は、平均粗さ（Ｒａ）０．３μｍ〜１．２μｍの凹凸を予め設けた第２キャリア銅箔の表面に、第１キャリア銅箔が積層された多層金属箔である半導体素子搭載用パッケージ基板の製造方法。 The present invention relates to the following.
(1) A multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order is prepared, and a base metal foil side of the multilayer metal foil and a base material are laminated to form a core substrate. A step of physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil. A step of physically peeling and separating the laminate from the core substrate together with the second carrier metal foil between the carrier metal foil and the base metal foil, and etching on the second carrier metal foil of the peeled laminate Form resist and etch And a step of forming a three-dimensional circuit on the first pattern plating or on the insulating layer.
(2) A multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order is prepared, and a base metal foil side of the multilayer metal foil and a base material are laminated to form a core substrate. A step of physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil. A step of physically peeling the laminate together with the second carrier metal foil from the core substrate between the carrier metal foil and the base metal foil, and separating the laminate on the second carrier metal foil of the peeled laminate. Step of performing pattern plating of 2 and before A step of removing the second carrier metal foil other than the portion subjected to the second pattern plating by etching and forming a three-dimensional circuit on the first pattern plating or on the insulating layer. A manufacturing method of a package substrate.
(3) A multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order is prepared, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. A step of physically peeling the first carrier metal layer between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil. A step of physically separating the laminate from the core substrate together with the second carrier metal foil between the carrier metal foil and the base metal foil; and removing the second carrier metal foil of the separated laminate. Before the first pattern plating. And a step of exposing the surface of the insulating layer to a semiconductor device mounting package substrate.
(4) In any one of the above (1) to (3), the multilayer metal foil has a peel strength between the second carrier metal foil and the base metal foil, and the first carrier metal foil and the second carrier metal foil A method of manufacturing a package substrate for mounting a semiconductor element, which is a multilayer metal foil formed larger than the peel strength between.
(5) In any one of the above (1) to (5), the multilayer metal foil is formed on the surface of the second carrier copper foil provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance. A manufacturing method of a package substrate for mounting a semiconductor element, which is a multilayer metal foil in which one carrier copper foil is laminated.

本発明によれば、樹脂粉の付着を抑制することにより歩留まり向上が可能であり、アンダーカットが生じない埋め込み回路を形成することにより微細で密着力があり、表面が絶縁層に対して外層回路が形成可能であり、また、任意の箇所に立体回路を形成することによりバンプやピラー等の種々の金属構成を形成可能な半導体素子搭載用パッケージ基板の製造方法を提供することができる。   According to the present invention, it is possible to improve the yield by suppressing the adhesion of resin powder, and by forming an embedded circuit that does not cause an undercut, it has a fine and adhesive force, and the surface is an outer layer circuit with respect to the insulating layer. In addition, it is possible to provide a method of manufacturing a package substrate for mounting a semiconductor element that can form various metal structures such as bumps and pillars by forming a three-dimensional circuit at an arbitrary position.

本発明に用いる多層金属箔の断面図である。It is sectional drawing of the multilayer metal foil used for this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法を用いて作製した半導体パッケージの 断面図である。It is sectional drawing of the semiconductor package produced using the manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention.

本発明のパッケージ基板の製造方法の一例について、図１〜図８を用いて以下に説明する。   An example of the manufacturing method of the package substrate of the present invention will be described below with reference to FIGS.

まず、図１に示すように、第１キャリア金属箔１０と第２キャリア金属箔１１とベース金属箔１２とをこの順に積層して形成した多層金属箔９を準備する。   First, as shown in FIG. 1, a multilayer metal foil 9 formed by laminating a first carrier metal foil 10, a second carrier metal foil 11 and a base metal foil 12 in this order is prepared.

第１キャリア金属箔１０は、第２キャリア金属箔１１の表面（第１キャリア金属箔１０側の表面）を保護するためのものであり、第２キャリア金属箔１１との間で物理的に剥離可能とされる。第２キャリア金属箔１１の表面を保護できれば、特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては１〜３５μｍが好ましい。また、第１キャリア金属箔１０と第２キャリア金属箔１１との間には、これらの金属箔１０、１１の間での剥離強度を安定化するための剥離層１３を設けるのが好ましく、剥離層１３としては、絶縁樹脂と積層する際の加熱・加圧を複数回行っても剥離強度が安定化しているものが好ましい。このような剥離層１３としては、特開２００３−１８１９７０号公報に開示された金属酸化物層と有機剤層を形成したものや、特開２００３−０９４５５３号公報に開示されたＣｕ−Ｎｉ−Ｍｏ合金からなるもの、再公表特許ＷＯ２００６／０１３７３５号公報に示されたＮｉ及びＷの金属酸化物又はＮｉ及びＭｏの金属酸化物を含有するものが挙げられる。なお、この剥離層１３は、第１キャリア金属箔１０を第２キャリア金属箔１１との間で物理的に剥離する際には、第１キャリア金属箔１０側に付着した状態で剥離し、第２キャリア金属箔１１の表面には残留しないものが望ましい。   The first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side), and is physically separated from the second carrier metal foil 11. It is possible. As long as the surface of the second carrier metal foil 11 can be protected, the material and thickness are not particularly limited. However, in terms of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is preferably 1 to 35 μm. Moreover, it is preferable to provide the peeling layer 13 between the 1st carrier metal foil 10 and the 2nd carrier metal foil 11 in order to stabilize the peeling strength between these metal foils 10 and 11, peeling. The layer 13 is preferably one in which the peel strength is stabilized even if the heating and pressurization at the time of laminating with the insulating resin are performed a plurality of times. As such a release layer 13, a metal oxide layer and an organic agent layer disclosed in Japanese Patent Application Laid-Open No. 2003-181970, or Cu—Ni—Mo disclosed in Japanese Patent Application Laid-Open No. 2003-094553 are used. Examples thereof include those made of an alloy and those containing a metal oxide of Ni and W or a metal oxide of Ni and Mo shown in the republished patent WO 2006/013735. When the first carrier metal foil 10 is physically peeled from the second carrier metal foil 11, the release layer 13 is peeled off while being attached to the first carrier metal foil 10 side. What does not remain on the surface of the two-carrier metal foil 11 is desirable.

第２キャリア金属箔１１は、第１キャリア金属箔１０を剥離した後の表面に第１のパターンめっき１８を行うために電流を供給するシード層となるものであり、第１キャリア金属箔１０との間およびベース金属箔１２との間で物理的に剥離可能とされる。ベース金属箔１２とともに給電層として機能すればよく、特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては１から１８μｍのものを使用できる。ただ、後述するように外層回路２を形成する際（図７（１４）、図８（１４）、図１０（１３））にはエッチングで除去されるので、エッチング量のばらつきを極力低減して高精度な微細回路を形成するためには１〜５μｍの極薄金属箔が好ましい。また、第１キャリア金属箔１０との間およびベース金属箔１２との間には、これらの金属箔１０、１２との間での剥離強度を安定化するため、上述したような剥離層１３、１４を設けるのが好ましい。なお、この剥離層１４は、第２キャリア金属箔１１とベース金属箔１２とが一体となってシード層として作用するようにするため、導電性を有するものが望ましい。また、剥離層１４は、第２キャリア金属箔１１とベース金属箔１２との間で物理的に剥離する際には、ベース金属箔１２側に移行するのが望ましい。これにより、ベース金属箔１２を剥離した後の積層体２２側には、第２キャリア金属箔１１の表面が露出するので、後工程で行う第２キャリア金属箔１１のエッチングが、剥離層１４によって阻害されることがない。   The second carrier metal foil 11 serves as a seed layer for supplying a current for performing the first pattern plating 18 on the surface after the first carrier metal foil 10 is peeled off. Between the base metal foil 12 and the base metal foil 12. It only needs to function as a power feeding layer together with the base metal foil 12, and the material and thickness are not particularly limited. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is 1 to 18 μm. Can be used. However, as will be described later, when the outer layer circuit 2 is formed (FIG. 7 (14), FIG. 8 (14), FIG. 10 (13)), it is removed by etching, so variation in etching amount is reduced as much as possible. In order to form a highly accurate fine circuit, an ultrathin metal foil of 1 to 5 μm is preferable. Also, between the first carrier metal foil 10 and the base metal foil 12, in order to stabilize the peel strength between these metal foils 10, 12, the release layer 13, as described above, 14 is preferably provided. The release layer 14 is preferably conductive so that the second carrier metal foil 11 and the base metal foil 12 are integrated to act as a seed layer. Moreover, when the peeling layer 14 physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it is desirable to transfer to the base metal foil 12 side. Thereby, since the surface of the second carrier metal foil 11 is exposed on the side of the laminate 22 after the base metal foil 12 is peeled off, the etching of the second carrier metal foil 11 performed in a later step is performed by the peeling layer 14. There is no hindrance.

ベース金属箔１２は、多層金属箔９を基材１６と積層してコア基板１７を作製する際に、基材１６と積層される側に位置するものであり、第２キャリア金属箔１１との間で物理的に剥離可能とされる。基材１６と積層される際に、基材１６との接着性を有していれば特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては９〜７０μｍが好ましい。また、第２キャリア金属箔１１との間には、この金属箔１１との間での剥離強度を安定化するため、上述したような剥離層１４を設けるのが好ましい。   The base metal foil 12 is positioned on the side laminated with the base material 16 when the multilayer metal foil 9 is laminated with the base material 16 to produce the core substrate 17. It can be physically peeled between. When laminated with the base material 16, the material and the thickness are not particularly limited as long as they have adhesiveness with the base material 16, but the material is copper foil or aluminum foil in terms of versatility and handleability. The thickness is preferably 9 to 70 μm. Further, in order to stabilize the peel strength between the second carrier metal foil 11 and the metal foil 11, it is preferable to provide the peel layer 14 as described above.

多層金属箔９としては、３層以上の金属箔（例えば、上述したように、第１キャリア金属箔１０と第２キャリア金属箔１１とベース金属箔１２）を有する多層金属箔９であって、少なくとも２箇所の間（例えば、上述したように、第１キャリア金属箔１０と第２キャリア金属箔１１との間および第２キャリア金属箔１１とベース金属箔１２との間）が物理的に剥離可能なものを用いる。多層金属箔９のベース金属箔１２側に基材１６を積層してコア基板１７を形成する工程の際には、第１キャリア金属箔１０の表面に樹脂粉等の異物が付着することがあるが、このような異物が付着したとしても、第１キャリア金属箔１０を第２キャリア金属箔１１との間で物理的に剥離することで、樹脂粉等の異物の影響のない第２キャリア金属箔１１の表面が形成されるので、高品質な金属箔表面を確保することができる。したがって、第２キャリア金属箔１１をシード層として使用して第１のパターンめっき１８を行う場合にも、欠陥の発生を抑制することができるので、歩留りの向上を図ることが可能になる。   The multilayer metal foil 9 is a multilayer metal foil 9 having three or more layers of metal foils (for example, as described above, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12), Physical separation between at least two locations (for example, as described above, between the first carrier metal foil 10 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the base metal foil 12) Use what is possible. In the process of laminating the base material 16 on the base metal foil 12 side of the multilayer metal foil 9 to form the core substrate 17, foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10. However, even if such foreign matter adheres, the second carrier metal that is not affected by foreign matters such as resin powder is obtained by physically peeling the first carrier metal foil 10 from the second carrier metal foil 11. Since the surface of the foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the first pattern plating 18 is performed using the second carrier metal foil 11 as a seed layer, the occurrence of defects can be suppressed, so that the yield can be improved.

次に、図２（１）に示すように、多層金属箔９のベース金属箔１２側と基材１６とを積層してコア基板１７を形成する。基材１６は、多層金属箔９と積層一体化してコア基板１７を形成するものであり、基材１６としては、一般的に半導体素子搭載用パッケージ基板１の絶縁層３として使用されるものを用いることができる。このような基材１６として、ガラスエポキシ、ガラスポリイミド等が挙げられる。コア基板１７は、多層金属箔９を用いて、パッケージ基板１を製造する際に支持基板となるものであり、剛性を確保することによって、作業性を向上させること、およびハンドリング時の損傷を防いで歩留りを向上させるのを主な役割とするものである。このため、基材１６としては、ガラス繊維等の補強材を有するものが望ましく、例えば、ガラスエポキシ、ガラスポリイミド等のプリプレグを、多層金属箔９と重ねて、熱プレス等を用いて加熱・加圧して積層一体化することで形成できる。基材１６の両側（図２（１）の上下両側）に多層金属箔９を積層し、この後の工程を行うことで、１回の工程で２つのパッケージ基板１を製造する工程を進めることができるので、工数低減を図ることができる。また、コア基板１７の両側に対称な構成の積層板を構成できるので、反りを抑制することができ、作業性や製造設備への引っ掛かり等による損傷も抑制できる。   Next, as shown in FIG. 2 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 are laminated to form a core substrate 17. The base material 16 is laminated and integrated with the multilayer metal foil 9 to form the core substrate 17. The base material 16 is generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1. Can be used. Examples of the substrate 16 include glass epoxy and glass polyimide. The core substrate 17 serves as a support substrate when the package substrate 1 is manufactured using the multilayer metal foil 9. By ensuring rigidity, workability is improved and damage during handling is prevented. The main role is to improve the yield. For this reason, it is desirable that the substrate 16 has a reinforcing material such as glass fiber. For example, a prepreg such as glass epoxy or glass polyimide is overlapped with the multilayer metal foil 9 and heated / heated using a hot press or the like. It can be formed by pressing and laminating and integrating. The multilayer metal foil 9 is laminated on both sides of the base material 16 (upper and lower sides in FIG. 2 (1)), and the subsequent steps are performed to advance the process of manufacturing the two package substrates 1 in one step. Therefore, man-hours can be reduced. Moreover, since the laminated board of a symmetrical structure can be comprised on both sides of the core board | substrate 17, a curvature can be suppressed and the damage | damage by workability | operativity, a catch to a manufacturing facility, etc. can also be suppressed.

次に、図２（２）に示すように、多層金属箔９の第１キャリア金属箔１０と第２キャリア金属箔１１との間で、第１キャリア金属箔を物理的に剥離する。第１キャリア金属箔１０の表面には、積層時に基材１６の材料となるプリプレグ等からの樹脂粉等の異物が付着する場合がある。このため、この第１キャリア金属箔１０を用いて回路を形成する場合は、表面に付着した樹脂粉等の異物によって、回路に断線や短絡等の欠陥が生じることがあり、歩留りの低下に繋がる可能性がある。しかし、このように、第１キャリア金属箔１０を剥離し除去することにより、樹脂粉等の異物が付着していない第２キャリア金属箔１１を使用して回路を形成することができるので、回路欠陥の発生を抑制することができ、歩留りを改善することが可能になる。また、第１キャリア金属箔１０を物理的に剥離可能であるため、第１キャリア金属箔１０と第２キャリア金属箔１１との間の剥離強度を調整することで、剥離作業を容易に行うことができる。このとき、多層金属箔９の第１キャリア金属箔１０と第２キャリア金属箔１１との間の剥離層１３は、第１キャリア金属箔１０側に移行するのが望ましい。これにより、第１キャリア金属箔１０を剥離した後の第２キャリア金属箔１１側には、第２キャリア金属箔１１の表面が露出するので、後工程で行う第２キャリア金属箔１１上へのめっきレジスト形成や第１のパターンめっき１８の形成が、剥離層１３によって阻害されることがない。   Next, as shown in FIG. 2 (2), the first carrier metal foil is physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9. On the surface of the first carrier metal foil 10, there may be a case where foreign matters such as resin powder from a prepreg or the like that becomes a material of the substrate 16 at the time of lamination adhere. For this reason, when forming a circuit using this first carrier metal foil 10, foreign matter such as resin powder adhered to the surface may cause defects such as disconnection or short circuit in the circuit, leading to a decrease in yield. there is a possibility. However, since the first carrier metal foil 10 is peeled and removed in this way, a circuit can be formed using the second carrier metal foil 11 to which no foreign matter such as resin powder adheres. The occurrence of defects can be suppressed, and the yield can be improved. Further, since the first carrier metal foil 10 can be physically peeled off, the peeling work can be easily performed by adjusting the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. Can do. At this time, it is desirable that the peeling layer 13 between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9 is moved to the first carrier metal foil 10 side. Thereby, since the surface of the 2nd carrier metal foil 11 is exposed to the 2nd carrier metal foil 11 side after peeling the 1st carrier metal foil 10, it is on the 2nd carrier metal foil 11 performed by a post process. The formation of the plating resist and the formation of the first pattern plating 18 are not hindered by the release layer 13.

ここで、多層金属箔９は、第２キャリア金属箔１１とベース金属箔１２との間の剥離強度が、第１キャリア金属箔１０と第２キャリア金属箔１１との間の剥離強度よりも大きく形成された多層金属箔９であるのが望ましい。これにより、第１キャリア金属箔１０と第２キャリア金属箔１１との間で物理的に剥離する際に、第２キャリア金属箔１１とベース金属箔１２との間が同時に剥離するのを抑制することができる。剥離強度としては、加熱・加圧する前（基材１６となるプリプレグを積層してコア基板１７を形成する前）の初期において、第１キャリア金属箔１０と第２キャリア金属箔１１との間では２Ｎ／ｍ〜５０Ｎ／ｍ、第２キャリア金属箔１１とベース金属箔１２との間では１０Ｎ／ｍ〜７０Ｎ／ｍとし、第１キャリア金属箔１０と第２キャリア金属箔１１との間の剥離強度が、第２キャリア金属箔１１とベース金属箔１２との間の剥離強度よりも５Ｎ／ｍ〜２０Ｎ／ｍ小さく、加熱・加圧した後（基材１６となるプリプレグを積層してコア基板１７を形成した後）の剥離強度の変化率が、初期に対して２０％程度以下になるようにすると、製造工程でのハンドリングで剥離することがなく、一方で加熱・加圧した後でも剥離する際は容易であり、しかも第１キャリア金属箔１０を剥離する際に、第２キャリア金属箔１１が同時に剥れるのを抑制することができるので作業性がよい。   Here, in the multilayer metal foil 9, the peel strength between the second carrier metal foil 11 and the base metal foil 12 is greater than the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. It is desirable that the multilayer metal foil 9 be formed. This suppresses simultaneous peeling between the second carrier metal foil 11 and the base metal foil 12 when physically peeling between the first carrier metal foil 10 and the second carrier metal foil 11. be able to. As for the peel strength, between the first carrier metal foil 10 and the second carrier metal foil 11 at the initial stage before heating and pressurization (before the core substrate 17 is formed by laminating the prepreg serving as the base material 16), 2N / m to 50 N / m, 10 N / m to 70 N / m between the second carrier metal foil 11 and the base metal foil 12, and peeling between the first carrier metal foil 10 and the second carrier metal foil 11 The strength is 5 N / m to 20 N / m less than the peel strength between the second carrier metal foil 11 and the base metal foil 12, and after heating and pressurizing (a prepreg serving as a base material 16 is laminated to form a core substrate When the rate of change in peel strength after forming 17 is about 20% or less relative to the initial value, the peel does not peel off due to handling in the manufacturing process, but peels off even after heating and pressurizing. Easy to do, Upon the release of the first carrier metal foil 10 duck, good workability since the second carrier metal foil 11 can be prevented peeling is the same time.

剥離強度の調整は、例えば、特開２００３−１８１９７０号公報や特開２００３−０９４５５３号公報、再公表特許ＷＯ２００６／０１３７３５号公報に示されるように、剥離層の下地となる第２キャリア金属箔１１の表面（第１キャリア金属箔１０側の表面）の粗さを調整したり、剥離層となる金属酸化物や合金めっき層を形成するためのめっき液組成や条件を調整することにより可能となる。   For example, as shown in Japanese Patent Application Laid-Open No. 2003-181970, Japanese Patent Application Laid-Open No. 2003-094553, and Republished Patent WO 2006/013735, the adjustment of the peel strength is performed on the second carrier metal foil 11 serving as the base of the release layer. This can be achieved by adjusting the roughness of the surface (the surface on the first carrier metal foil 10 side) or by adjusting the plating solution composition and conditions for forming a metal oxide or alloy plating layer to be a release layer. .

次に、図２（３）に示すように、コア基板１７に残った第２キャリア金属箔１１上に第１のパターンめっき１８を行う。上述したように、第２キャリア金属箔１１の表面（第１キャリア金属箔１０側の表面）には、積層時に使用するプリプレグ等からの樹脂粉等の異物は付着しないので、これに起因する回路欠陥を抑制可能となる。第１のパターンめっき１８は、第２キャリア金属箔１１上に、めっきレジスト（図示しない。）を形成した後、電気めっきを用いて行うことができる。めっきレジストとしては、一般的なパッケージ基板の製造プロセスで用いられる感光性レジストを使用することができる。電気めっきとしては、一般的なパッケージ基板の製造プロセスで用いられる硫酸銅めっきを用いることができる。   Next, as shown in FIG. 2 (3), the first pattern plating 18 is performed on the second carrier metal foil 11 remaining on the core substrate 17. As described above, the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) does not adhere to foreign matters such as resin powder from the prepreg used at the time of lamination, so the circuit resulting from this Defects can be suppressed. The first pattern plating 18 can be performed using electroplating after forming a plating resist (not shown) on the second carrier metal foil 11. As the plating resist, a photosensitive resist used in a general package substrate manufacturing process can be used. As the electroplating, copper sulfate plating used in a general package substrate manufacturing process can be used.

多層金属箔９は、平均粗さ（Ｒａ）が０．３μｍ〜１．２μｍの凹凸を予め設けた第２キャリア金属箔１１の表面に、剥離層１３を介して第１キャリア金属箔１０が積層された多層金属箔９であるのが望ましい。これにより、第１キャリア金属箔１０を剥離層１３とともに物理的に剥離した後の第２キャリア金属箔１１の表面は、予め設けた平均粗さ（Ｒａ）が０．３μｍ〜１．２μｍの凹凸を有する。このため、第２キャリア金属箔１１の表面（第１キャリア金属箔１０側の表面）に、第１のパターンめっき１８用のめっきレジストを形成する際に、めっきレジストの密着や解像性を向上させることができ、高密度回路の形成に有利となる。また、第２キャリア金属箔１１の表面に予め凹凸を設けておくことで、第１キャリア金属箔１０を剥離した後に、第２キャリア金属箔１１の表面に粗面化処理を行う必要がないため、工数の低減を図ることができる。   In the multilayer metal foil 9, the first carrier metal foil 10 is laminated on the surface of the second carrier metal foil 11 provided with irregularities with an average roughness (Ra) of 0.3 μm to 1.2 μm in advance via a release layer 13. The multilayer metal foil 9 is desirable. As a result, the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is physically peeled together with the peeling layer 13 has irregularities with an average roughness (Ra) provided in advance of 0.3 μm to 1.2 μm. Have Therefore, when the plating resist for the first pattern plating 18 is formed on the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side), the adhesion and resolution of the plating resist are improved. This is advantageous for forming a high-density circuit. In addition, by providing unevenness on the surface of the second carrier metal foil 11 in advance, it is not necessary to roughen the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is peeled off. The man-hour can be reduced.

第２キャリア金属箔１１の表面に設ける凹凸の表面粗さは、平均粗さ（Ｒａ）が０．３〜１．２μｍであるのが、めっきレジストの密着や解像性を改善しつつ、第１のパターンめっき１８後の剥離性を確保できる点で望ましい。平均粗さ（Ｒａ）が０．３μｍ未満の場合、めっきレジストの密着不足が生じる傾向があり、平均粗さ（Ｒａ）が１．２μｍを超える場合、めっきレジストが追従し難くなりやはり密着不足が生じる傾向がある。さらに、めっきレジストのライン／スペースが１５μｍ／１５μｍよりも微細になる場合には、平均粗さ（Ｒａ）が０．５μｍ〜０．９μｍであるのが望ましい。ここで、平均粗さ（Ｒａ）とは、ＪＩＳ Ｂ ０６０１（２００１）で規定される平均粗さ（Ｒａ）であり、触針式表面粗さ計などを用いて測定することが可能である。なお、平均粗さ（Ｒａ）の調整は、第２キャリア金属箔１１が銅箔であれば、第２キャリア金属箔１１としての銅箔を形成する際の電気銅めっきの組成（添加剤等を含む）や条件（電流密度や時間等）を調整することで可能となる。   The surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 has an average roughness (Ra) of 0.3 to 1.2 μm, while improving the adhesion and resolution of the plating resist. It is desirable at the point which can ensure the peelability after 1 pattern plating 18. When the average roughness (Ra) is less than 0.3 μm, the adhesion of the plating resist tends to be insufficient, and when the average roughness (Ra) exceeds 1.2 μm, the plating resist becomes difficult to follow and the adhesion is insufficient. Tend to occur. Further, when the line / space of the plating resist becomes finer than 15 μm / 15 μm, it is desirable that the average roughness (Ra) is 0.5 μm to 0.9 μm. Here, the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like. In addition, adjustment of average roughness (Ra) is the composition (additive etc.) of the electro copper plating at the time of forming the copper foil as the 2nd carrier metal foil 11 if the 2nd carrier metal foil 11 is a copper foil. And the conditions (current density, time, etc.) can be adjusted.

次に、図３（４）に示すように、第１のパターンめっき１８を含む第２キャリア金属箔１１上に絶縁層３を積層して積層体２２を形成する。絶縁層３としては、一般的にパッケージ基板１の絶縁層３として使用されるものを用いることができる。このような絶縁層３として、エポキシ系樹脂、ポリイミド系樹脂等が挙げられ、例えば、エポキシ系やポリイミド系の接着シート、ガラスエポキシやガラスポリイミド等のプリプレグを、熱プレス等を用いて加熱・加圧して積層一体化することで形成できる。ここで、積層体２２とは、このように積層一体化した状態のもののうち、第１のパターンめっき１８を含む第２キャリア金属箔１１上に積層されたものをいう。絶縁層３となるこれらの樹脂の上に、さらに導体層２０となる金属箔とを重ねて同時に加熱・加圧して積層一体化した場合は、この導体層２０も含む。また、後述するように、導体層２０により内層回路６を形成したり、導体層２０を接続する層間接続５を形成した場合は、これらの内層回路６や層間接続５も含む。   Next, as shown in FIG. 3 (4), the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating 18 to form a laminated body 22. As the insulating layer 3, those generally used as the insulating layer 3 of the package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin and a polyimide resin. For example, an epoxy or polyimide adhesive sheet, a glass epoxy or a glass polyimide prepreg is heated and heated using a hot press or the like. It can be formed by pressing and laminating and integrating. Here, the laminated body 22 refers to one laminated on the second carrier metal foil 11 including the first pattern plating 18 among those laminated and integrated. In the case where a metal foil to be the conductor layer 20 is further stacked on these resins to be the insulating layer 3 and simultaneously laminated by heating and pressing, this conductor layer 20 is also included. As will be described later, when the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 for connecting the conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included.

次に、図３（５）、（６）に示すように、層間接続孔２１を形成し、層間接続５や内層回路６を形成してもよい。層間接続５は、例えば、いわゆるコンフォーマル工法を用いて層間接続孔２１を形成した後、この層間接続孔２１内をめっきすることで形成することができる。このめっきには、下地めっきとして薄付け無電解銅めっきを行った後、厚付けめっきとして無電解銅めっきや電気銅めっき、フィルドビアめっき等を用いることができる。エッチングする導体層２０の厚みを薄くして微細回路を形成し易くするためには、薄付けの下地めっきの後、めっきレジストを形成し、厚付けめっきを電気銅めっきやフィルドビアめっきで行うのが望ましい。内層回路６は、例えば、層間接続孔２１へのめっきを行った後、エッチングによって不要部分の導体層２０を除去することにより形成することができる。   Next, as shown in FIGS. 3 (5) and 3 (6), the interlayer connection hole 21 may be formed to form the interlayer connection 5 and the inner layer circuit 6. The interlayer connection 5 can be formed, for example, by forming the interlayer connection hole 21 by using a so-called conformal method and then plating the interlayer connection hole 21. In this plating, electroless copper plating, electrolytic copper plating, filled via plating, or the like can be used as the thick plating after thin electroless copper plating is performed as the base plating. In order to reduce the thickness of the conductor layer 20 to be etched and make it easy to form a fine circuit, it is necessary to form a plating resist after the thin base plating and perform the thick plating by electrolytic copper plating or filled via plating. desirable. The inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary conductor layer 20 by etching.

次に、図４（７）、（８）および図５（９）、（１０）に示すように、内層回路６や層間接続５の上に、さらに絶縁層３と導体層２０を形成し、図３（５）、（６）のときと同様にして、所望の層数となるように、内層回路６や外層回路２、７、層間接続５を形成することもできる。   Next, as shown in FIGS. 4 (7) and (8) and FIGS. 5 (9) and (10), an insulating layer 3 and a conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5, In the same manner as in FIGS. 3 (5) and (6), the inner layer circuit 6, the outer layer circuits 2, 7 and the interlayer connection 5 can be formed so as to have a desired number of layers.

次に、図６（１１）に示すように、多層金属箔９の第２キャリア金属箔１１とベース金属箔１２との間で、積層体２２を第２キャリア金属箔１１とともにコア基板１７から物理的に剥離して分離する。このとき、多層金属箔９の第２キャリア金属箔１１とベース金属箔１２との間の剥離層１４は、ベース金属箔１２側に移行するのが望ましい。これにより、ベース金属箔１２を剥離した後の積層体２２側には、第２キャリア金属箔１１の表面が露出するので、後工程で行う第２キャリア金属箔１１のエッチングが、剥離層１４によって阻害されることがない。   Next, as shown in FIG. 6 (11), between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Exfoliate and separate. At this time, it is desirable that the peeling layer 14 between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9 is moved to the base metal foil 12 side. Thereby, since the surface of the second carrier metal foil 11 is exposed on the side of the laminate 22 after the base metal foil 12 is peeled off, the etching of the second carrier metal foil 11 performed in a later step is performed by the peeling layer 14. There is no hindrance.

次に、図７（１２）〜（１４）に示すように、分離して剥離した積層体２２の第２キャリア金属箔１１上にエッチングレジスト２５を形成して積層体２２の第２キャリア金属箔１１をエッチングして、前記第１のパターンめっき１８を絶縁層３の表面に露出させるとともに、第１のパターンめっき１８上または絶縁層３上に立体回路２４を形成する。また、図８（１２）〜（１４）に示すように、分離して剥離した積層体２２の第２キャリア金属箔１１上に第２のパターンめっき２３を行い、第２のパターンめっき２３を行った部分以外の第２キャリア金属箔１１をエッチングにより除去し、第１のパターンめっき１８を絶縁層３の表面に露出させるとともに、第１のパターンめっき１８上または絶縁層３上に立体回路２４を形成することもできる。また、図１０（１２）〜（１４）に示すように、分離した積層体２２の第２キャリア金属箔１１をエッチング等により除去して、第１のパターンめっき１８を絶縁層３の表面に露出させる。なお、図７（１２）〜（１４）、図８（１２）〜（１４）及び図１０（１２）〜（１４）は、図６（１１）のように分離した積層体２２のうち、下側の部分のみを表している。これにより、外層回路２を形成する際に、外層回路２の側面がエッチングによって侵食されないため、アンダーカットを生じないので、微細な外層回路２を形成することができる。また、本発明で形成される外層回路２は、絶縁層３に埋め込まれた状態となるため、外層回路２の底面だけでなく、両側の側面も絶縁層３と密着しているため、微細回路であっても、十分な密着性を確保することができる。また、第２キャリア金属箔１１として厚さ１μｍ〜５μｍの極薄銅箔を用いた場合は、僅かなエッチング量でも第２キャリア金属箔１１を除去することができるため、絶縁層３に埋め込まれ、絶縁層３から露出した外層回路２の表面は平坦であり、ワイワーボンディングやフリップチップ接続の際の接続信頼性を確保することができ、半導体素子との接続端子として用いられるのに適している。また、半導体素子との接続端子を、層間接続５と平面視において重なる位置の外層回路２に設けることが可能であるため、半導体素子との接続端子を層間接続５の直上または直下に設けることが可能であり、小型化・高密度化にも対応が可能である。さらに、任意の箇所に立体回路２４を形成することによりバンプやピラー等の種々の金属構成を形成可能であり、第２キャリア金属箔１１や第２のパターンめっき２３の厚みを変えることで、任意の高さに形成することも可能であるため、種々の半導体素子（図示しない。）や他のパッケージ基板との接続形態に対応することができる。例えば、図９に示すように、キャビティを設けなくても、ＰｏＰを構成することが可能となる。   Next, as shown in FIGS. 7 (12) to (14), an etching resist 25 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second carrier metal foil of the laminated body 22. 11 is etched to expose the first pattern plating 18 on the surface of the insulating layer 3, and a three-dimensional circuit 24 is formed on the first pattern plating 18 or on the insulating layer 3. Further, as shown in FIGS. 8 (12) to (14), the second pattern plating 23 is performed on the second carrier metal foil 11 of the laminated body 22 which has been separated and peeled, and the second pattern plating 23 is performed. The second carrier metal foil 11 other than the exposed portion is removed by etching so that the first pattern plating 18 is exposed on the surface of the insulating layer 3 and the three-dimensional circuit 24 is formed on the first pattern plating 18 or the insulating layer 3. It can also be formed. Further, as shown in FIGS. 10 (12) to (14), the second carrier metal foil 11 of the separated laminate 22 is removed by etching or the like, and the first pattern plating 18 is exposed on the surface of the insulating layer 3. Let 7 (12) to (14), FIGS. 8 (12) to (14), and FIGS. 10 (12) to (14) are the bottom of the stacked body 22 separated as shown in FIG. 6 (11). Only the side part is shown. As a result, when the outer layer circuit 2 is formed, the side surface of the outer layer circuit 2 is not eroded by etching, so that no undercut occurs, so that the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed in the present invention is embedded in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3, so that the fine circuit Even so, sufficient adhesion can be ensured. In addition, when an ultrathin copper foil having a thickness of 1 μm to 5 μm is used as the second carrier metal foil 11, the second carrier metal foil 11 can be removed even with a slight etching amount, so that it is embedded in the insulating layer 3. The surface of the outer layer circuit 2 exposed from the insulating layer 3 is flat, can ensure connection reliability at the time of wire bonding and flip chip connection, and is suitable for being used as a connection terminal with a semiconductor element. Yes. Further, since the connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in plan view, the connection terminal with the semiconductor element is provided directly above or immediately below the interlayer connection 5. It is possible to cope with downsizing and high density. Furthermore, it is possible to form various metal structures such as bumps and pillars by forming the solid circuit 24 at an arbitrary place, and by changing the thickness of the second carrier metal foil 11 and the second pattern plating 23, any metal structure can be formed. Therefore, it is possible to cope with various semiconductor elements (not shown) and connection forms with other package substrates. For example, as shown in FIG. 9, PoP can be configured without providing a cavity.

次に、必要に応じてソルダーレジスト４や保護めっき８を形成してもよい。保護めっき８としては、一般的にパッケージ基板の接続端子の保護めっきとして用いられるニッケルめっきと金めっきが望ましい。   Next, you may form the soldering resist 4 and the protective plating 8 as needed. As the protective plating 8, nickel plating and gold plating which are generally used as protective plating for connection terminals of the package substrate are desirable.

以上のように、本発明のパッケージ基板の製造方法によれば、層間接続と重なる位置に平坦でかつ微細な埋め込み回路を有するパッケージ基板を形成することができ、ワイヤーボンディングやフリップチップ接続に適したパッケージ基板を形成することができる。また、任意の箇所に立体回路を形成することによりバンプやピラー等の種々の金属構成を備えるパッケージ基板を形成することができる。   As described above, according to the method for manufacturing a package substrate of the present invention, it is possible to form a package substrate having a flat and fine embedded circuit at a position overlapping with an interlayer connection, which is suitable for wire bonding and flip chip connection. A package substrate can be formed. Further, a package substrate having various metal structures such as bumps and pillars can be formed by forming a three-dimensional circuit at an arbitrary location.

以下に、本発明の実施例を説明するが、本発明は本実施例に限定されない。   Examples of the present invention will be described below, but the present invention is not limited to the examples.

（実施例１）
まず、図１に示すように、第１キャリア金属箔１０と第２キャリア金属箔１１とベース金属箔１２とをこの順に積層して形成した多層金属箔９を準備した。第１キャリア金属箔１０は９μｍの銅箔を、第２キャリア金属箔１１は３μｍの極薄銅箔を、ベース金属箔１２は１８μｍの銅箔を用いている。ベース金属箔１２の表面（第２キャリア金属箔１１側の表面）には、物理的な剥離が可能になるように、剥離層１４を設けた。また、第２キャリア金属箔１１の表面（第１キャリア金属箔１０側の表面）には、平均粗さ（Ｒａ）０．７μｍの凹凸を予め設けた。また、この凹凸の上、つまり第１キャリア金属箔１０との間には、物理的な剥離が可能になるように、剥離層１３を設けた。ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離層１３、１４は、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成することで形成した。なお、剥離強度の調整は、電流密度と時間を調整することで、剥離層１３、１４を形成する金属酸化物量を調整して行った。このときの加熱・加圧する前（基材１６となるプリプレグを積層してコア基板１７を形成する前）の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が４７Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が２９Ｎ／ｍであった。なお、加熱・加圧した後（基材１６となるプリプレグを積層してコア基板１７を形成した後）の剥離強度の変化率は、初期に対して約１０％程度上昇した程度であった。 Example 1
First, as shown in FIG. 1, the multilayer metal foil 9 formed by laminating the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12 in this order was prepared. The first carrier metal foil 10 is a 9 μm copper foil, the second carrier metal foil 11 is a 3 μm ultrathin copper foil, and the base metal foil 12 is an 18 μm copper foil. A release layer 14 was provided on the surface of the base metal foil 12 (the surface on the second carrier metal foil 11 side) so that physical peeling was possible. In addition, the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) was provided with unevenness having an average roughness (Ra) of 0.7 μm in advance. In addition, a release layer 13 was provided on the unevenness, that is, between the first carrier metal foil 10 so as to allow physical peeling. The release layers 13 and 14 between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) and Mo (molybdenum). ), And forming a metal oxide layer using a plating bath containing citric acid. The peel strength was adjusted by adjusting the current density and time to adjust the amount of metal oxide forming the peel layers 13 and 14. At this time, the initial peel strength before heating and pressurization (before forming the core substrate 17 by laminating the prepreg serving as the base material 16) is 47 N between the base metal foil 12 and the second carrier metal foil 11. The distance between the second carrier metal foil 11 and the first carrier metal foil 10 was 29 N / m. Note that the rate of change in peel strength after heating and pressing (after forming the core substrate 17 by laminating the prepreg serving as the base material 16) was about 10% higher than the initial level.

図１に示す多層金属箔９の作製は、具体的には以下のように行った。
（１）ベース金属箔１２として、厚さ１８μｍの電解銅箔を用い、硫酸３０ｇ／Ｌに６０秒浸漬して酸洗浄後に流水で３０秒間水洗を行った。
（２）洗浄した電解銅箔を陰極とし、酸化イリジウムコーテイングを施したＴｉ極板を陽極とし、Ｎｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴として、硫酸ニッケル６水和物３０ｇ／Ｌ、モリブデン酸ナトリウム２水和物３．０ｇ／Ｌ、クエン酸３ナトリウム２水和物３０ｇ／Ｌ、ｐＨ６．０、液温度３０℃の浴にて、電解銅箔の光沢面に、電流密度２０Ａ／ｄｍ２で５秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成した。
（３）剥離層１４を形成後の表面に、硫酸銅５水和物２００ｇ／Ｌ、硫酸１００ｇ／Ｌ、液温度４０℃の浴にて、酸化イリジウムコーテイングを施したＴｉ極板を陽極として、電流密度４Ａ／ｄｍ２で２００秒間電解めっきを行い、厚さ３μｍの第２キャリア金属箔１１となる金属層を形成した。
（４）第２キャリア金属箔１１となる金属層を形成した後の表面に、上記（２）と同様の浴を用いて、電流密度１０Ａ／ｄｍ２で１０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。
（５）剥離層１３を形成した後の表面に、上記（３）と同様の浴を用いて、電流密度４Ａ／ｄｍ２で６００秒間電解めっきを行い厚さ９μｍの第１キャリア金属箔１０となる金属層を形成した。
（６）基材１６と接触する面に、硫酸銅めっきにより粒状の粗化粒子を形成し、クロメート処理及びシランカップリング剤処理を施した。また、基材１６と接しない面にはクロメート処理を施した。 Specifically, the multilayer metal foil 9 shown in FIG. 1 was produced as follows.
(1) As the base metal foil 12, an electrolytic copper foil having a thickness of 18 μm was used, immersed in sulfuric acid 30 g / L for 60 seconds, washed with acid and then washed with running water for 30 seconds.
(2) Nickel sulfate hexahydrate as a plating bath containing Ni (nickel), Mo (molybdenum), and citric acid, using the cleaned electrolytic copper foil as a cathode, a Ti electrode plate coated with iridium oxide as an anode, 30 g / L, sodium molybdate dihydrate 3.0 g / L, trisodium citrate dihydrate 30 g / L, pH 6.0, bath temperature of 30 ° C. Electrolytic treatment was performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum.
(3) On the surface after forming the release layer 14, a Ti electrode plate subjected to iridium oxide coating in a bath of copper sulfate pentahydrate 200 g / L, sulfuric acid 100 g / L, liquid temperature 40 ° C., as an anode, Electrolytic plating was performed at a current density of 4 A / dm 2 for 200 seconds to form a metal layer to be the second carrier metal foil 11 having a thickness of 3 μm.
(4) The surface after forming the metal layer to be the second carrier metal foil 11 is subjected to electrolytic treatment at a current density of 10 A / dm 2 for 10 seconds using the same bath as in the above (2), from nickel and molybdenum. A release layer 13 containing a metal oxide was formed.
(5) The surface after forming the release layer 13 is subjected to electrolytic plating at a current density of 4 A / dm 2 for 600 seconds using the same bath as the above (3), and the first carrier metal foil 10 having a thickness of 9 μm A metal layer was formed.
(6) Granular roughened particles were formed on the surface in contact with the substrate 16 by copper sulfate plating, and subjected to chromate treatment and silane coupling agent treatment. Further, the chromate treatment was applied to the surface not in contact with the substrate 16.

次に、図２（１）に示すように、多層金属箔９のベース金属箔１２側と基材１６とを積層してコア基板１７を形成した。基材１６としてガラスエポキシのプリプレグを用い、このプリプレグの上下両側に多層金属箔９を重ねて、熱プレスを用いて加熱・加圧して積層一体化した。   Next, as shown in FIG. 2 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17. A glass epoxy prepreg was used as the substrate 16, and the multilayer metal foils 9 were stacked on both upper and lower sides of the prepreg, and were laminated and integrated by heating and pressing using a hot press.

次に、図２（２）に示すように、多層金属箔９の第１キャリア金属箔１０と第２キャリア金属箔１１との間で、第１キャリア金属箔１０を物理的に剥離した。   Next, as shown in FIG. 2 (2), the first carrier metal foil 10 was physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.

次に、図２（３）に示すように、コア基板１７に残った第２キャリア金属箔１１上に第１のパターンめっき１８を行った。第１のパターンめっき１８は、第２キャリア金属箔１１上に、感光性のめっきレジストを形成した後、硫酸銅電気めっきを用いて形成した。   Next, as shown in FIG. 2 (3), the first pattern plating 18 was performed on the second carrier metal foil 11 remaining on the core substrate 17. The first pattern plating 18 was formed using copper sulfate electroplating after forming a photosensitive plating resist on the second carrier metal foil 11.

次に、図３（４）に示すように、第１のパターンめっき１８を含む第２キャリア金属箔１１上に絶縁層３と導体層２０として銅箔（１２μｍ）を積層して積層体２２を形成した。絶縁層３としては、エポキシ系の接着シートを熱プレスを用い、加熱・加圧して積層一体化することで形成した。   Next, as shown in FIG. 3 (4), a copper foil (12 μm) is laminated as the insulating layer 3 and the conductor layer 20 on the second carrier metal foil 11 including the first pattern plating 18 to form a laminate 22. Formed. The insulating layer 3 was formed by laminating and integrating an epoxy adhesive sheet by heating and pressing using a hot press.

次に、図３（５）、（６）に示すように、層間接続５や内層回路６を形成した。層間接続５は、コンフォーマル工法を用いて層間接続孔２１を形成した後、この層間接続孔２１内をめっきすることで形成した。このめっきには、下地めっきとして薄付け無電解銅めっきを行った後、感光性のめっきレジストを形成し、厚付けめっきを硫酸銅電気めっきで行った。この後、エッチングによって不要部分の導体層２０を除去することにより内層回路６を形成した。   Next, as shown in FIGS. 3 (5) and (6), the interlayer connection 5 and the inner layer circuit 6 were formed. The interlayer connection 5 was formed by forming the interlayer connection hole 21 using a conformal method and then plating the interior of the interlayer connection hole 21. In this plating, thin electroless copper plating was performed as a base plating, a photosensitive plating resist was formed, and thick plating was performed by copper sulfate electroplating. Thereafter, the inner layer circuit 6 was formed by removing the unnecessary conductor layer 20 by etching.

次に、図４（７）、（８）および図５（９）、（１０）に示すように、内層回路６や層間接続５の上に、さらに絶縁層３と導体層２０を形成し、内層回路６や外層回路２、７、層間接続５を形成して、４層の導体層２０を有する積層体２２を形成した。   Next, as shown in FIGS. 4 (7) and (8) and FIGS. 5 (9) and (10), an insulating layer 3 and a conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5, The inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 were formed to form a laminate 22 having four conductor layers 20.

次に、図６（１１）に示すように、多層金属箔９の第２キャリア金属箔１１とベース金属箔１２との間で、積層体２２を第２キャリア金属箔１１とともにコア基板１７から物理的に剥離して分離した。   Next, as shown in FIG. 6 (11), between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Peeled off and separated.

次に、図７（１２）〜（１４）に示すように、分離して剥離した積層体２２の第２キャリア金属箔１１上にエッチングレジストを形成して積層体２２の第２キャリア金属箔１１をエッチングして、前記第１のパターンめっき１８を前記絶縁層３の表面に露出させるとともに、第１のパターンめっき１８上または絶縁層３上に立体回路２４を形成した。   Next, as shown in FIGS. 7 (12) to (14), an etching resist is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and separated, and the second carrier metal foil 11 of the laminated body 22. Was etched to expose the first pattern plating 18 on the surface of the insulating layer 3, and a three-dimensional circuit 24 was formed on the first pattern plating 18 or on the insulating layer 3.

次に、感光性のソルダーレジストを形成し、その後、保護めっきとして、無電解ニッケルめっきと無電解金めっきを行い、パッケージ基板を形成した。   Next, a photosensitive solder resist was formed, and then electroless nickel plating and electroless gold plating were performed as protective plating to form a package substrate.

（実施例２）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流密度や時間を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度１０Ａ／ｄｍ２で１０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度７．５Ａ／ｄｍ２で１５秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が２３Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が１８Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して１０〜２０％程度上昇した程度であった。これ以外は実施例１と同様にしてパッケージ基板を作製した。 (Example 2)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. By changing the current density and time when forming the metal oxide layer using the plating bath containing an acid, the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 7.5 A / dm 2 for 15 seconds. A release layer 13 containing a metal oxide made of nickel and molybdenum was formed. The initial peel strength before heating and pressurization at this time is 23 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 18 N / m. The peel strength after heating and pressurization was about 10 to 20% higher than the initial value. A package substrate was fabricated in the same manner as in Example 1 except for this.

（実施例３）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度５Ａ／ｄｍ２で２０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度２Ａ／ｄｍ２で２０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が１５Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が２Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して１０〜２０％程度上昇した程度であった。これ以外は実施例１と同様にしてパッケージ基板を作製した。 (Example 3)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. The amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 5 A / dm 2 for 20 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 2 A / dm 2 for 20 seconds. And a release layer 13 containing a metal oxide made of molybdenum. The initial peel strength before heating and pressing at this time is 15 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 2 N / m. The peel strength after heating and pressurization was about 10 to 20% higher than the initial value. A package substrate was fabricated in the same manner as in Example 1 except for this.

（実施例４）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度２５Ａ／ｄｍ２で４秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度２０Ａ／ｄｍ２で４秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が６８Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が４８Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して５〜１０％程度上昇した程度であった。 Example 4
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. The amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 25 A / dm 2 for 4 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 20 A / dm 2 for 4 seconds. And a release layer 13 containing a metal oxide made of molybdenum. The initial peel strength before heating and pressurization at this time is 68 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 48 N / m. Note that the peel strength after heating and pressurization was about 5 to 10% higher than the initial value.

上記で準備した多層金属箔９を用い、実施例１の図７（１２）〜（１４）に示す工程の代わりに、図８（１２）〜（１４）に示すように、分離して剥離した積層体２２の第２キャリア金属箔１１上に第２のパターンめっき２３を行い、第２のパターンめっき２３を行った部分以外の第２キャリア金属箔１１をエッチングにより除去し、第１のパターンめっき１８を絶縁層３の表面に露出させるとともに、第１のパターンめっき１８上または絶縁層３上に立体回路２４を形成した。この工程以外は、実施例１と同様にしてパッケージ基板を作製した。   Using the multilayer metal foil 9 prepared above, instead of the steps shown in FIGS. 7 (12) to (14) of Example 1, separation and peeling were performed as shown in FIGS. 8 (12) to (14). The second pattern metal plating 23 is performed on the second carrier metal foil 11 of the laminated body 22, and the second carrier metal foil 11 other than the portion where the second pattern metal plating 23 is performed is removed by etching, and the first pattern metal plating is performed. 18 was exposed on the surface of the insulating layer 3, and the three-dimensional circuit 24 was formed on the first pattern plating 18 or on the insulating layer 3. A package substrate was fabricated in the same manner as in Example 1 except for this step.

（実施例５）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度２０Ａ／ｄｍ２で５秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度１０Ａ／ｄｍ２で１０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が４３Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が２８Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して１０〜１５％程度上昇した程度であった。これ以外は実施例４と同様にしてパッケージ基板を作製した。 (Example 5)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. The amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds. And a release layer 13 containing a metal oxide made of molybdenum. The initial peel strength before heating and pressurization at this time is 43 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 28 N / m. The peel strength after heating / pressurizing was about 10 to 15% higher than the initial value. A package substrate was fabricated in the same manner as in Example 4 except for this.

（実施例６）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度１０Ａ／ｄｍ２で１０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度２．５Ａ／ｄｍ２で４０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が２２Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が４Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して５〜１５％程度上昇した程度であった。これ以外は実施例４と同様にしてパッケージ基板を作製した。 (Example 6)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. The amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 2.5 A / dm 2 for 40 seconds. A release layer 13 containing a metal oxide made of nickel and molybdenum was formed. The initial peel strength before heating and pressurization at this time is 22 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 4 N / m. The peel strength after heating and pressurizing was about 5 to 15% higher than the initial value. A package substrate was fabricated in the same manner as in Example 4 except for this.

（実施例７）
ベース金属箔１２と第２キャリア金属箔１１との間、及び第２キャリア金属箔１１と第１キャリア金属箔１０との間の剥離強度を、何れもＮｉ（ニッケル）、Ｍｏ（モリブデン）、クエン酸を含有するめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層１３、１４を形成する金属酸化物量を調整して変化させた。具体的には、電流密度２０Ａ／ｄｍ２で５秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１４を形成し、電流密度１０Ａ／ｄｍ２で１０秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層１３を形成した。このときの加熱・加圧する前の初期の剥離強度は、ベース金属箔１２と第２キャリア金属箔１１との間が４５Ｎ／ｍ、第２キャリア金属箔１１と第１キャリア金属箔１０との間が２６Ｎ／ｍであった。なお、加熱・加圧した後の剥離強度は、初期に対して１０％程度上昇した程度であった。 (Example 7)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher. The amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds. And a release layer 13 containing a metal oxide made of molybdenum. The initial peel strength before heating and pressurization at this time is 45 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10. Was 26 N / m. Note that the peel strength after heating and pressing was about 10% higher than the initial value.

上記で準備した多層金属箔９を用い、実施例１の図７（１２）〜（１４）に示す工程の代わりに、図１０（１２）〜（１４）に示すように、分離して剥離した積層体２２の第２キャリア金属箔１１をエッチングにより除去し、第１のパターンめっき１８を絶縁層３の表面に露出させ絶縁層３に埋め込まれた外層回路２を形成した。この工程以外は、実施例１と同様にしてパッケージ基板を作製した。   Using the multilayer metal foil 9 prepared above, instead of the steps shown in FIGS. 7 (12) to (14) of Example 1, separation and peeling were performed as shown in FIGS. 10 (12) to (14). The second carrier metal foil 11 of the laminate 22 was removed by etching, and the first pattern plating 18 was exposed on the surface of the insulating layer 3 to form the outer layer circuit 2 embedded in the insulating layer 3. A package substrate was fabricated in the same manner as in Example 1 except for this step.

表１に、実施例１〜７について、絶縁層３に埋め込まれて形成された外層回路２の仕上がり状態、第１キャリア金属箔１０と第２キャリア金属箔１１との間の剥離強度、第２キャリア金属箔１１とベース金属箔１２との間の剥離強度、ハンドリング時のキャリア金属箔の剥れの有無を示す。実施例１〜７の何れもライン／スペースが１０μｍ／１０μｍまでの微細な外層回路２を形成することができた（表１の“○”は、アンダーカットのないことを示す。）。また、断面を観察した結果、何れもアンダーカットは生じていなかった。さらに、断面の観察結果から、第２キャリア金属箔１１は３μｍの極薄銅を用いているため、僅かなエッチング量で均一に除去されており、外層回路２の表面はほぼ平坦であった。また、実施例１〜６の何れも、製造工程でのハンドリングで第１キャリア金属箔１０と第２キャリア金属箔１１との間や、第２キャリア金属箔１１とベース金属箔１２との間が剥離することはなかった（表１の“○”は、剥れがないことを示す。）。また、第１キャリア金属箔１０と第２キャリア金属箔１１との間で剥離する際に、第２キャリア金属箔１１とベース金属箔１２との間が剥離することはなかった。   Table 1 shows the finished state of the outer layer circuit 2 embedded in the insulating layer 3 for Examples 1 to 7, the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11, and the second The peel strength between the carrier metal foil 11 and the base metal foil 12 and the presence or absence of peeling of the carrier metal foil during handling are shown. In each of Examples 1 to 7, the fine outer layer circuit 2 having a line / space of 10 μm / 10 μm could be formed (“◯” in Table 1 indicates no undercut). In addition, as a result of observing the cross section, no undercut had occurred. Furthermore, from the observation result of the cross section, since the second carrier metal foil 11 is made of ultra-thin copper having a thickness of 3 μm, the second carrier metal foil 11 was uniformly removed with a slight etching amount, and the surface of the outer circuit 2 was almost flat. Also, in all of Examples 1 to 6, there is a gap between the first carrier metal foil 10 and the second carrier metal foil 11 or between the second carrier metal foil 11 and the base metal foil 12 due to handling in the manufacturing process. There was no peeling (“◯” in Table 1 indicates no peeling). Further, when peeling between the first carrier metal foil 10 and the second carrier metal foil 11, there was no peeling between the second carrier metal foil 11 and the base metal foil 12.

Figure 2012094840
Figure 2012094840

加熱・加圧する前（基材１６となるプリプレグを積層してコア基板１７を形成する前）の初期の剥離強度（Ｎ／ｍ）の測定は、１０ｍｍ幅にカットした多層金属箔のサンプルを作製し、テンシロンＲＴＭ−１００（株式会社オリエンテック製、商品名、「テンシロン」は登録商標。）を用い、ＪＩＳ Ｚ ０２３７の９０度引き剥がし法に準じて、室温（２５℃）で、まず、第１キャリア金属箔を９０度方向に毎分３００ｍｍの速さで引き剥がして測定し、次に、第２キャリア金属箔を９０度方向に毎分３００ｍｍの速さで引き剥がして測定した。また、加熱・加圧した後（基材１６となるプリプレグを積層してコア基板１７を形成した後）の剥離強度も、初期の剥離強度と同様にして測定し、初期に対する変化率を求めた。なお、多層金属箔９と基材１６となるガラスエポキシプリプレグとを積層してコア基板１７を形成する際の加熱・加圧の条件は、真空プレスを用いて、圧力３ＭＰａ、温度１７５℃、保持時間１．５ｈｒである。   Measurement of the initial peel strength (N / m) before heating / pressurization (before forming the core substrate 17 by laminating the prepreg to be the base material 16) is made of a multilayer metal foil sample cut to a width of 10 mm. Then, using Tensilon RTM-100 (made by Orientec Co., Ltd., trade name, “Tensilon” is a registered trademark), according to JIS Z 0237 90 degree peeling method, One carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction, and then the second carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction. Further, the peel strength after heating and pressurization (after forming the core substrate 17 by laminating the prepreg as the base material 16) was also measured in the same manner as the initial peel strength, and the rate of change relative to the initial value was obtained. . In addition, the conditions of the heating and pressurization when laminating the multilayer metal foil 9 and the glass epoxy prepreg serving as the base material 16 to form the core substrate 17 are as follows: a pressure of 3 MPa, a temperature of 175 ° C. is maintained using a vacuum press. The time is 1.5 hr.

１：半導体素子搭載用パッケージ基板
２：外層回路または埋め込み回路
３：絶縁層
４：ソルダーレジスト
５：層間接続
６：内層回路
７：外層回路
８：保護めっき
９：多層金属箔
１０：第１キャリア金属箔
１１：第２キャリア金属箔
１２：ベース金属箔
１３：剥離層
１４：剥離層
１６：基材
１７：コア基板
１８：第１のパターンめっき
２０：導体層
２１：層間接続孔
２２：積層体
２３：第２のパターンめっき
２４：立体回路
２５：エッチングレジスト
２６：はんだ
２７：半導体素子
２８：半導体パッケージ
２９：封止材 1: Semiconductor device mounting package substrate 2: outer layer circuit or embedded circuit 3: insulating layer 4: solder resist 5: interlayer connection 6: inner layer circuit 7: outer layer circuit 8: protective plating 9: multilayer metal foil 10: first carrier metal Foil 11: second carrier metal foil 12: base metal foil 13: release layer 14: release layer 16: base material 17: core substrate 18: first pattern plating 20: conductor layer 21: interlayer connection hole 22: laminate 23 : Second pattern plating 24: 3D circuit 25: etching resist 26: solder 27: semiconductor element 28: semiconductor package 29: encapsulant

Claims (5)

第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、
前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属箔を物理的に剥離する工程と、
前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、
前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、
前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、
前記剥離した積層体の第２キャリア金属箔上にエッチングレジストを形成してエッチングを行い、前記第１のパターンめっき上または前記絶縁層上に立体回路を形成する工程と、
を有する半導体素子搭載用パッケージ基板の製造方法。 A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Process,
Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
Forming a laminate by laminating an insulating layer on the second carrier metal foil including the first pattern plating;
Between the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating the laminate together with the second carrier metal foil from the core substrate,
Forming an etching resist on the second carrier metal foil of the peeled laminate, performing etching, and forming a three-dimensional circuit on the first pattern plating or on the insulating layer;
Manufacturing method of semiconductor device mounting package substrate having 第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、
前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属箔を物理的に剥離する工程と、
前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、
前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、
前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、
前記剥離した積層体の第２キャリア金属箔上に第２のパターンめっきを行う工程と、
前記第２のパターンめっきを行った部分以外の第２キャリア金属箔をエッチングにより除去し、前記第１のパターンめっき上または前記絶縁層上に立体回路を形成する工程と、
を有する半導体素子搭載用パッケージ基板の製造方法。 A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Process,
Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
Forming a laminate by laminating an insulating layer on the second carrier metal foil including the first pattern plating;
Between the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating the laminate together with the second carrier metal foil from the core substrate,
Performing a second pattern plating on the second carrier metal foil of the peeled laminate;
Removing the second carrier metal foil other than the portion subjected to the second pattern plating by etching, and forming a three-dimensional circuit on the first pattern plating or on the insulating layer;
Manufacturing method of semiconductor device mounting package substrate having 第１キャリア金属箔と第２キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、
前記多層金属箔の第１キャリア金属箔と第２キャリア金属箔との間で、第１キャリア金属層を物理的に剥離する工程と、
前記コア基板に残った第２キャリア金属箔上に第１のパターンめっきを行う工程と、
前記第１のパターンめっきを含む第２キャリア金属箔上に絶縁層を積層して積層体を形成する工程と、
前記多層金属箔の第２キャリア金属箔とベース金属箔との間で、前記積層体を第２キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、
前記分離した積層体の第２キャリア金属箔を除去して、前記第１のパターンめっきを前記絶縁層の表面に露出させる工程と、
を有する半導体素子搭載用パッケージ基板の製造方法。 A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Process,
Physically peeling the first carrier metal layer between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
Forming a laminate by laminating an insulating layer on the second carrier metal foil including the first pattern plating;
Between the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating the laminate together with the second carrier metal foil from the core substrate,
Removing the second carrier metal foil of the separated laminate and exposing the first pattern plating to the surface of the insulating layer;
Manufacturing method of semiconductor device mounting package substrate having 請求項１または２において、
多層金属箔は、第２キャリア金属箔とベース金属箔との間の剥離強度が、第１キャリア金属箔と第２キャリア金属箔との間の剥離強度よりも大きく形成された多層金属箔である半導体素子搭載用パッケージ基板の製造方法。 In claim 1 or 2,
The multilayer metal foil is a multilayer metal foil formed such that the peel strength between the second carrier metal foil and the base metal foil is larger than the peel strength between the first carrier metal foil and the second carrier metal foil. Manufacturing method of semiconductor device mounting package substrate. 請求項１から３の何れかにおいて、
多層金属箔は、平均粗さ（Ｒａ）０．３μｍ〜１．２μｍの凹凸を予め設けた第２キャリア銅箔の表面に、第１キャリア銅箔が積層された多層金属箔である半導体素子搭載用パッケージ基板の製造方法。 In any one of Claim 1 to 3,
The multi-layer metal foil is a multi-layer metal foil in which the first carrier copper foil is laminated on the surface of the second carrier copper foil provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance. Method for manufacturing a package substrate.
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