KR101448529B1 - method of manufacturing PCB by semi-additive process with primer layer - Google Patents

Abstract

Provided is a method of manufacturing a PCB according to a specific embodiment. In the method of manufacturing a PCB, prepared is a unit laminate formed by successively stacking a primer layer, a first copper layer, and a second copper layer. A prepreg layer is prepared. To make both surfaces of the prepreg layer face the primer layer, the unit laminate is bonded to the prepreg layer to form a lamination structure. The first copper layer and the second copper layer of the unit laminate are separated with each other from the lamination structure, thereby manufacturing a base substrate where the primer layer and the first copper layer are stacked on both surfaces of the prepreg layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a printed circuit board using a semi-additive method using a primer layer,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board (PCB), and more particularly, to a method of manufacturing a printed circuit board using a semi-

Generally, a printed circuit board is formed by laminating a copper pattern layer on the base substrate using a copper clad laminate (CCL) in which copper layers are laminated on both surfaces of a core insulating layer as a base substrate. At this time, the printed circuit board is manufactured to have a thickness of about 200 to 230 탆 due to the thickness of the core insulating layer. 1A is a schematic view of a printed circuit board manufactured using a conventional copper-clad laminate. 1A, a printed circuit board 100a includes first circuit pattern layers 120a and 120b, second circuit pattern layers 130a and 130b, first and second circuit pattern layers 130a and 130b sequentially stacked from both sides of a core insulating layer 101, Three circuit pattern layers 140a and 140b. The printed circuit board 100a also includes a via via layer 110, first via layers 112a and 112b and second via layers 114a and 114b in the core insulating layer. A portion of the third circuit pattern layers 140a and 140b may function as a pad layer connecting with an external connection structure such as the bump 150a or the solder ball 150b. In addition, the printed circuit board 100a includes interlayer insulating layers 160a and 160b for insulating a plurality of circuit pattern layers and via layers.

In recent years, there has been a demand for a process technology capable of reducing the thickness of a printed circuit board and making a printed circuit pattern finer in accordance with the tendency of lightness and shortening of packaged products. One such process technique relates to a lamination method using a carrier substrate. Specifically, a carrier substrate is provided, and a plurality of circuit pattern layers and an insulating layer are formed on the carrier substrate to form a laminated structure. Then, a chip is mounted on the stacked structure, and then only the carrier substrate is removed to manufacture a printed circuit board. The carrier substrate may include an insulating core layer, which is present only during manufacture of the printed circuit board by the carrier substrate and is removed with the carrier substrate when the printed circuit board is completed. Thus, a coreless printed circuit board without a core insulating layer can be manufactured. As described above, by applying the technique using the carrier substrate, the final printed circuit board can be formed with a thin thickness of 100 mu m or less. 1B is a view schematically showing a coreless printed circuit board manufactured using a conventional carrier substrate. As shown in the figure, the printed circuit board 100b has a plurality of circuit pattern layers 122, 132, 142, 152, 162, 172 and a plurality of 134, 144, 154, and 164, respectively. The printed circuit board 100b is provided with an interlayer insulating film for insulating between a plurality of circuit pattern layers 122, 132, 142, 152, 162, 172 and a plurality of via layers 124, 134, 144, 154, Layer 180, as shown in FIG. The coreless printed circuit board 100b can omit the through hole passing through the core insulating layer and can realize a fine pattern and a fine size via layer. Thereby, pattern density can be improved. In addition, thermal conductivity and electrical conductivity can be improved by decreasing the thickness and increasing the pattern density, thereby realizing excellent performance.

On the other hand, a semi-additive process (hereinafter referred to as SAP), which is different from the conventional tenting method, has been introduced as a technique for miniaturizing a printed circuit pattern. The tenting method is a method in which a plating layer is formed on a substrate and then the plating layer is patterned by an etching method to form a circuit pattern. On the other hand, the SAP forms a photosensitive pattern layer on the substrate and forms a plating layer so as to fill the space between the photosensitive pattern layers. Then, the photosensitive pattern layer is removed to form a circuit pattern from the plating layer. By not directly etching the plating layer, the SAP can form a more precise and finer pattern than the tenting method.

As described above, conventionally, a commercial ABF (Ajinomoto Build-up Film) material is applied as an insulating layer disposed between the circuit pattern layers in manufacturing a microcircuit pattern using SAP. The ABF material is easy to form roughness on the surface through chemical etching, and is excellent in bonding strength with the chemical plating layer formed on the ABF material when the SAP is advanced. However, the ABF material has a low stiffness and is vulnerable to warpage. In the case of a conventional printed circuit board, ABF having a thick enough thickness to sufficiently compensate for the above-mentioned disadvantages related to stiffness and warping is employed as the insulating layer. In recent years, however, The thickness of the insulating layer is also reduced. Therefore, when the ABF is used as an insulating layer, the rigidity of the printed circuit board may be lowered and the bending phenomenon may occur.

Embodiments of the present invention provide a method of manufacturing a printed circuit board using SAP, which can prevent the rigidity of a printed circuit board and the occurrence of warpage.

A method of manufacturing a printed circuit board according to one aspect is provided. In the method for manufacturing a printed circuit board, a unit laminate in which a primer layer, a first copper layer and a second copper layer are sequentially laminated is prepared. Prepare a prepreg layer. The laminate structure is formed by bonding the unit laminate to the prepreg layer such that both surfaces of the prepreg layer and the primer layer face each other. The base substrate on which the primer layer and the first copper layer are laminated on both surfaces of the prepreg layer is manufactured by separating the first copper layer and the second copper layer of the unit laminate from the laminated structure .

A method of manufacturing a printed circuit board according to another aspect is provided. The method of manufacturing a printed circuit board according to claim 1, wherein the first unit laminate, the first prepreg layer, the second unit laminate, the second prepreg layer, the third unit laminate, the third prepreg layer, The first unit laminate to the fourth unit laminate include a primer layer, a first copper layer and a second copper layer, which are sequentially laminated, respectively. Removing the first copper layer and the second copper layer of the first unit laminate, the first copper layer and the second copper layer of the fourth unit laminate from the first laminated structure, The primer layer of the unit laminate and the primer layer of the fourth unit laminate are exposed. A first circuit pattern layer is formed on the primer layer of the first unit laminate and the fourth unit laminate. The fourth and fifth prepreg layers, the fifth and the sixth unit laminate are laminated on both surfaces of the first laminate structure on which the first circuit pattern layer is formed to form a second laminate structure, And the sixth unit laminate comprise a primer layer, a first copper layer and a second copper layer, which are sequentially stacked. The second laminated structure is separated to produce first and second circuit substrates including the first circuit pattern layer and a base substrate having the second copper layer on both surfaces thereof.

A method of manufacturing a printed circuit board according to another aspect is provided. First, a first unit laminate, a first prepreg layer, a second unit laminate, a second prepreg layer, a third unit laminate, a third prepreg layer, and a fourth unit laminate are stacked from the bottom And the first unit laminate to the fourth unit laminate include a primer layer, a first copper layer and a second copper layer, which are sequentially laminated. Removing the first copper layer and the second copper layer of the first unit laminate, the first copper layer and the second copper layer of the fourth unit laminate from the first laminated structure, The primer layer of the unit laminate and the primer layer of the fourth unit laminate are exposed. A first circuit pattern layer is formed on the primer layer of the first unit laminate and the fourth unit laminate. The fourth and fifth prepreg layers, the fifth and the sixth unit laminate are laminated on both surfaces of the first laminate structure on which the first circuit pattern layer is formed to form a second laminate structure, And the sixth unit laminate comprise a primer layer, a first copper layer and a second copper layer, which are sequentially stacked. The second laminated structure from which the second copper layer is removed is processed to form a via hole exposing the first circuit pattern layer. A via layer filling the via hole and a second circuit pattern layer disposed on the primer layer of the fifth unit laminate and the sixth unit laminate are formed. Forming a third laminated structure by laminating sixth and seventh prepreg layers, seventh and eighth unit laminated bodies on both surfaces of the second laminated structure in which the second circuit pattern layer is formed, And the eighth unit laminate include a primer layer, a first copper layer and a second copper layer, which are sequentially stacked. The third laminated structure is separated to form first and second circuit substrates including the first circuit pattern layer and the second circuit pattern layer and a base substrate having the second copper layer on both surfaces thereof.

According to one embodiment, the copper pattern layer can be reliably formed on the insulating layer through the SAP process. Specifically, a prepreg having excellent resistance to bending is easily adopted as an insulating layer of a printed circuit board by interposing a primer layer between the prepreg layer and the chemical plating layer to improve the bonding force between the prepreg layer and the chemical plating layer .

According to one embodiment, a plurality of unit stacks including a primer layer and a copper layer are bonded to a plurality of prepreg layers, and the copper layer is removed or separated, thereby forming the primer layer on the prepreg layer The base substrate and the circuit board can be manufactured at the same time.

As described above, according to the embodiment of the present invention, it is possible to reduce the thickness of the insulating layer and to miniaturize the circuit pattern, thereby making it possible to manufacture a thin printed circuit board having a fine pattern.

1A and 1B are sectional views schematically showing a conventional printed circuit board.
2A to 2C are cross-sectional views schematically showing a method of manufacturing a base substrate of a printed circuit board according to an embodiment of the present invention.
3A to 3D are cross-sectional views schematically showing a method of manufacturing a printed circuit board using a base substrate according to an embodiment of the present invention.
4A to 4D are sectional views schematically showing a method of manufacturing a printed circuit board using a base substrate according to another embodiment of the present invention.
5A to 5E are sectional views schematically showing a method of manufacturing a circuit board or a base board of a printed circuit board according to another embodiment of the present invention.
6A to 6D are cross-sectional views schematically showing a method of manufacturing a printed circuit board using a circuit board according to another embodiment of the present invention.
7A to 7E are views schematically showing a method of manufacturing a printed substrate or a base substrate according to still another embodiment of the present invention.

Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the techniques disclosed in this disclosure are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements .

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Further, in carrying out the method or the manufacturing method, the respective steps of the method may take place differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, and may not be excluded in some cases in the reverse order.

As described above, when ABF is used as an insulating layer, there is a possibility that a bending phenomenon occurs when the thickness of ABF is reduced. In order to overcome this difficulty, attempts have been made to apply a prepreg material having a stiffness higher than that of ABF as an insulating layer by providing glass fibers therein. However, since such a prepreg layer is difficult to form roughness on the surface, the adhesion to the chemical plating layer may not be good during the SAP process. Therefore, there is a difficulty in forming the copper pattern layer by the SAP process reliably on the prepreg layer. Accordingly, the inventors propose a method of arranging a primer layer on the prepreg layer in order to ensure the reliability of the SAP process proceeding on the prepreg layer as follows.

2A to 2C are cross-sectional views schematically showing a method of manufacturing a base substrate of a printed circuit board according to an embodiment of the present invention. Referring to FIG. 2A, the primer layers 222a, 222b, 222c and 222d, the first copper layers 224a, 224b, 224c and 224d and the second copper layers 226a, 226b, 226c and 226d are sequentially stacked Unit stacks 220a, 220b, 220c and 220d are prepared.

The primer layers 222a, 222b, 222c and 222d are formed on the prepreg layers 210a, 210b, 210c and 210d to be described later by the prepreg layers 210a, 210b, 210c and 210d ) And the copper plating layer. The primer layers 222a, 222b, 222c, and 222d may include, for example, a polyurethane resin, an acrylic resin, a silicone resin, or the like. The primer layers 222a, 222b, 222c, and 222d may be formed by, for example, a vapor deposition method, a coating method, or a printing method.

The first copper layers 224a, 224b, 224c, 224d and the second copper layers 226a, 226b, 226c, 226d may have different thicknesses. In one embodiment, the first copper layers 224a, 224b, 224c, and 224d may have a thickness that is thinner than the second copper layers 226a, 226b, 226c, and 226d. In one example, the first copper layers 224a, 224b, 224c, 224d may have a thickness of about 1 to 5 um and the second copper layers 226a, 226b, 226c, 226d may have a thickness of about 10 to 25 um You can have two systems. However, the thicknesses of the first copper layers 224a, 224b, 224c, and 224d and the second copper layers 226a, 226b, 226c, and 226d may be variously selected. Although not shown, a release layer may be disposed between the first copper layers 224a, 224b, 224c, 224d and the second copper layers 226a, 226b, 226c, 226d. The release layer may function to separate the first copper layers 224a, 224b, 224c, and 224d and the second copper layers 226a, 226b, 226c, and 226d from each other in a subsequent process.

Referring to the drawing, prepreg layers 210a, 210b, and 210c are prepared. The prepreg layers 210a, 210b, and 210c may include epoxy resin and glass fiber. Due to the glass fiber, the prepreg layers 210a, 210b, and 210c may have greater rigidity and flexural resistance than the insulating layer of the ABF material.

Referring again to the drawings, the prepreg layers 210a, 210b and 210c and the unit stacks 220a, 220b and 220c are stacked so that the prepreg layers 210a, 210b and 210c are positioned between the unit stacks 220a, 220b, 220c and 220d. 220b, 220c, and 220d. As shown in the figure, the arrangement includes a first unit laminate 220a, a first prepreg layer 210a, a second unit laminate body 220b, a second prepreg layer 210b, The second prepreg layer 220c, the third prepreg layer 210c, and the fourth unit laminate 220d. Although three prepreg layers and four unit laminated bodies are shown in the drawing, the present invention is not limited thereto. As another example, it may be arranged so as to be located between one prepreg layer and two unit laminate bodies.

Referring to FIG. 2B, the unit stacks 220a, 220b, 220c, and 220d are connected to prepregs 220a, 220b, 220c, and 220d so that both surfaces of the prepreg layers 210a, 210b, and 210c and the primer layers 222a, The laminated structure 200 is formed by bonding to the leg layers 210a, 210b, and 210c. In a specific embodiment, the first unit laminate 220a, the first prepreg layer 210a, the second unit laminate body 220b, the second prepreg layer 210b, the third unit laminate body 220b The second prepreg layer 220c, the third prepreg layer 210c, and the fourth unit laminate 220d are stacked to form a laminated structure 200 having three prepreg layers.

Although not shown, as another embodiment, a laminated structure having one prepreg layer may be formed by joining a pair of unit laminate bodies to both surfaces of one prepreg layer. As such, the number of the prepreg layers included in the laminated structure 200 is not limited and may be composed of various numbers.

Referring to FIG. 2C, the first copper layers 224a, 224b, 224c and 224d of the unit stacks 220a, 220b, 220c and 220d and the second copper layers 226a, 226b and 226c 222b, 222c, and 222d and the first copper layers 224a, 224b, 224c, and 224d are stacked on both surfaces of the prepreg layers 210a and 210c by separating the first copper layers 222a, 222b, 222c, The base substrates 20 and 22 can be manufactured. In addition, the second base substrate 24 in which the second copper layers 226b and 226c are laminated on both surfaces of the prepreg layer 210b can be manufactured.

Specifically, in the method of manufacturing the first base substrate 20, 22 and the second base substrate 24, the second copper layer 226a exposed to the outside from the first unit laminate body 220a is removed , And the second copper layer 226d exposed to the outside from the fourth unit laminate 220d is removed. At the same time, the first copper layer 224b and the second copper layer 226b of the second unit laminate body 220b are separated from each other, and the first copper layer 224c and the second copper layer 224b of the third unit laminate body 220c Copper layer 226c are separated from each other.

Through the above-described processes, the first base substrate 20, 22 and the second base substrate 24 for manufacturing a printed circuit board can be manufactured.

In some other embodiments, the first copper layers 224a, 224b, 224c, 224d may be further removed from the first base substrate 20, 22. According to this, the primer layers 222a, 222b, 222c, 222d can be exposed on the surfaces of the first base substrates 20, 22.

3A to 3D are cross-sectional views schematically showing a method of manufacturing a printed circuit board using a base substrate according to an embodiment of the present invention. Referring to FIG. 3A, first base substrates 20 and 22 manufactured through the processes of FIGS. 2A to 2C are prepared. In the drawings, any one of the pair of first base substrates 20 and 24 is illustrated for convenience of explanation, but it is obvious that the same process can be performed for the other base substrates 20 and 24 as well.

Referring to FIG. 3B, holes 310 are formed through both surfaces of the first base substrate 20. As a method of forming the hole 310, a mechanical drilling method or a laser drilling method can be applied. The laser drilling may be performed using a carbon dioxide (CO2) laser, an ultraviolet (UV) laser, an excimer laser, or the like. The first copper layers 224c and 224d may then be removed from the first base substrate 20 to expose the primer layers 222c and 222d.

Alternatively, after removing the first copper layers 224c and 224d from the first base substrate 20, holes 310 may be formed through the first base substrate 20. [

Referring to FIG. 3C, a semimetric process is performed on the inside of the hole and the primer layers 222c and 222d to form copper pattern layers 320a, 320b and 320c. In the concrete process, first, a chemical plating layer is formed as a plating seed layer on the inside of the hole and on the primer layers 222c and 222d. Next, a photosensitive pattern layer (not shown) is formed on the primer layers 222c and 222d. Then, an electroplating method using the photosensitive pattern layer is performed to form a copper plating layer on the chemical plating layer. Subsequently, the copper pattern layers 320a, 320b and 320c may be formed from the copper plating layer by removing the photosensitive pattern layer. The copper pattern layers 320a, 320b, and 320c may form the circuit pattern layers 320a and 320b and the via layer 320c. The primer layers 222c and 222d improve the bonding force between the prepreg layer 210c and the chemical plating layer so that the circuit pattern layers 320a and 320b are stably formed in the upper portion or the lower portion of the prepreg layer 210c .

Referring to FIG. 3D, solder mask patterns 330a and 330b are formed on a base substrate 20 on which circuit pattern layers 320a and 320b are formed. The solder mask patterns 330a and 330b may expose portions of the circuit pattern layers 320a and 320b. The surface treatment layers 340a and 340b are formed on the exposed circuit pattern layers 320a and 320b. The surface treatment layers 340a and 340b can function to protect the exposed circuit pattern layers 320a and 320b from the external environment of the oxidizing atmosphere. The circuit pattern layers 320a and 320b on which the surface treatment layers 340a and 340b are formed can function as connection pads connected to connection structures such as solder balls or bumps. Examples of the surface treatment layers 340a and 340b include NiAu, NiPdAu, Au, Ag, Sn, Organic Solderability Preservative (OSP), Electrolytic Nickel Electroless Palladium Immersion Gold (ENEPIG), and Electroless Nickel Electroless Palladium can do.

As described above, by applying the base substrate on which the primer layer is disposed on the prepreg layer, the copper plating layer can be stably formed on the upper or lower portion of the prepreg layer. Thus, the first base substrates 20 and 22 manufactured through the processes of FIGS. 2A to 2C can be applied to the manufacture of printed circuit boards to which SAP is applied.

4A to 4D are sectional views schematically showing a method of manufacturing a printed circuit board using a base substrate according to another embodiment of the present invention. Referring to FIG. 4A, a second base substrate 24 manufactured through the processes of FIGS. 2A to 2C is prepared. The second base substrate 24 has a structure in which the second copper layers 226b and 226c are laminated on both surfaces of the prepreg layer 210b.

Referring to FIG. 4B, the second copper layers 226b and 226c are half-etched to reduce the thickness to a predetermined thickness. The half-etching may mean an etching process that removes a portion of the copper layer through dry or wet etching to reduce the thickness. A second copper layer 227b, 227c of reduced thickness may be formed by the half-etching. Subsequently, holes (400) penetrating both surfaces of the second base substrate (24) are formed. As a method of forming the holes 400, a mechanical drilling method or a laser drilling method can be applied. The laser drilling may be performed using a carbon dioxide (CO2) laser, an ultraviolet (UV) laser, an excimer laser, or the like.

Referring to FIG. 4C, a copper plating layer is formed in the second copper layers 227b and 227c and the holes 400 having a reduced thickness. Then, the circuit pattern layers 410b and 410c and the via layer 410a can be formed by patterning the copper plating layer by a tenting method. In the concrete process, the circuit pattern layers 410b and 410c can be formed by forming a photosensitive pattern on the copper plating layer and etching the copper plating layer using the photosensitive pattern.

4D, a solder mask pattern 420 is formed on the second base substrate 24 on which the circuit pattern layers 410b and 410c and the via layer 410a are formed. A surface treatment layer is formed on the circuit pattern layers 410b and 410c exposed by the solder mask pattern 420. The circuit pattern layers 410b and 410c on which the surface treatment layer is formed are connection pads for connection to the outside Function.

In the case of the second base substrate 24 described above, since the second copper layers 226b and 226c are provided on the prepreg layer 210b in a joined state, the electroplating or electroplating process is performed by the second copper layer 226b , 226c. That is, the plating process does not proceed directly on the prepreg layer 210b except inside the hole 400. [ Therefore, the circuit pattern layers 410b and 410c can be stably formed on the second base substrate 24. [ Thus, the second base substrate 24 manufactured through the processes of FIGS. 2A to 2C can be applied to the manufacture of a printed circuit board to which the tenting method is applied.

5A to 5E are cross-sectional views schematically showing a method of manufacturing a circuit board or a base board of a printed circuit board according to another embodiment of the present invention. Referring to FIG. 5A, a stacked structure 200 manufactured through the processes of FIGS. 2A to 2C is prepared. Hereinafter, the laminated structure 200 will be referred to as a first laminated structure 200 for convenience of explanation.

Referring to FIG. 5B, the first copper layer 224a and the second copper layer 226a of the first unit laminate body 220a are removed from the first laminate structure 200. Referring to FIG. Then, the first copper layer 224d and the second copper layer 226d of the fourth unit laminate body 220d are removed from the first laminate structure 200. Then, As a result, the primer layer 222a of the first unit laminate 220a and the primer layer 222d of the fourth unit laminate 220d are exposed to the outside.

Referring to FIG. 5C, the first circuit pattern layers 510a and 510b are formed on the primer layers 222a and 222d of the first unit laminate 220a and the fourth unit laminate 220d. The method of forming the first circuit pattern layers 510a and 510b can be performed by the SAP described above. In this case, the first circuit pattern layers 510a and 510b can be stably formed by disposing the primer layers 222a and 222d on the first prepreg layer 210a and the third prepreg layer 210c .

5D, a fourth prepreg layer 530a and a fifth prepreg layer 530b are formed on both surfaces of the first laminated structure 200 in which the first circuit pattern layers 510a and 510b are formed, The laminate body 540a and the sixth unit laminate body 540b are laminated to form a second laminate structure 500. [ At this time, the fifth unit stack body 540a and the sixth unit stack body 540b include primer layers 542a and 542b, first copper layers 544a and 544b, and second copper layers 546a and 546b . The primer layers 542a and 542b, the first copper layers 544a and 544b and the second copper layers 546a and 546b may be formed of the primer layers 222a, 222b, 222c, and 222d, 224b, 224c, 224d and the second copper layers 226a, 226b, 226c, 226d.

5E, the second stacked structure 500 is separated to form first and second circuit boards 50 and 52 each including first circuit pattern layers 510a and 510b, A base substrate 54 having layers 226b and 226c is fabricated. Specifically, in the process of separating the second laminated structure 500, first, the second copper layers 546a and 546b of the fifth and sixth unit laminate bodies 540a and 540b exposed to the outside are removed. The first copper layer 224b and the second copper layer 226b of the second unit laminate 220b are separated from each other and the first copper layer 224c and the second copper layer 226b of the third unit laminate 220c are separated, (226c) are separated from each other.

The first circuit substrate 50 includes the primer layer 222d of the fourth unit laminate body 220d disposed between the third prepreg layer 210c and the first circuit pattern layer 510a, And a primer layer 542b of the sixth unit laminate body 540b disposed on the first prepreg layer 530a. The second circuit substrate 52 includes a primer layer 222a of the first unit laminate body 220a disposed between the first prepreg layer 210a and the first circuit pattern layer 510b, And a primer layer 210b of the fifth unit laminate body 540b disposed on the leg layer 530b.

The first circuit pattern layers 510a and 510b of the first and second circuit boards 50 and 52 are formed on the prepreg layers 210a and 210c via the primer layers 222a and 222d, As shown in FIG.

6A to 6D are cross-sectional views schematically showing a method of manufacturing a printed circuit board using a circuit board according to another embodiment of the present invention. Referring to FIG. 6A, a first circuit board 50 or a second circuit board 52 manufactured through the processes of FIGS. 5A to 5E is prepared. Since the first and second circuit boards 50 and 52 have the same configuration, the first circuit board 50 will be described below for convenience of explanation.

Referring again to FIG. 6A, the first circuit substrate 50 is processed to form via holes 610a and 610b for exposing the first circuit pattern layer 510a. Although the via holes 610a and 610b are formed from both surfaces of the first circuit substrate 50 in the drawing, the present invention is not limited to this, and a via hole may be formed from one surface of the first circuit substrate 50 .

Referring to FIG. 6B, the first copper layers 544a and 544b of the first circuit board 50 are removed. 6C, a via layer 620c filling the via holes 610a and 610b, and second circuit pattern layers 620a and 620b disposed on the primer layers 542a and 542b of the first circuit substrate 50 It can be formed by SAP. The SAP may be performed in substantially the same manner as the SAP in the above-described embodiment with reference to FIG. 3C.

6D, solder mask patterns 630a and 630b are formed on the first circuit substrate 50 on which the first circuit pattern layer 510a and the second circuit pattern layers 620a and 620b are formed. The surface treatment layers 640a and 640b are formed on the second circuit pattern layers 620a and 620b exposed by the solder mask patterns 630a and 630b. The second circuit pattern layers 620a and 620b on which the surface treatment layers 640a and 640b are formed can function as connection pads for external connection.

Although not shown, in other embodiments, after the second circuit pattern layers 620a and 620b are formed, a further insulating layer and a circuit pattern layer may be laminated. As an example of a method of further forming the insulating layer and the circuit pattern layer, an insulating interlayer substrate is prepared and laminated on the second circuit pattern layers 620a and 620b, By carrying out the process, it can be achieved. The number of the insulating layers and circuit pattern layers to be laminated is not limited.

Although not shown, a circuit pattern layer can be formed on the base substrate 54 manufactured through the processes of FIGS. 5A to 5E through the tantalum method described above with reference to FIGS. 4A to 4D. As a result, the printed circuit board can be easily manufactured using the base substrate 54.

7A to 7E are views schematically showing a method of manufacturing a printed substrate or a base substrate according to still another embodiment of the present invention. Referring to FIG. 7A, a second stacked structure 500 manufactured through the processes of FIGS. 5A to 5D is prepared.

Referring to FIG. 7B, the second copper layers 546a and 546b of the fifth and sixth unit stacks 540a and 540b are removed from the second stacked structure 500. Next, the second stacked structure 500 is processed to form via holes 710a and 710b for exposing the first circuit pattern layer 510a. Then, the first copper layers 544a and 544b are removed.

In some other embodiments, the process of forming the above-described via holes 710a and 710b may be performed in a different order. That is, the second stacked structure 500 may be processed to form the via holes 710a and 710b first, and the second copper layers 546a and 546b and the first copper layers 544a and 544b may be sequentially removed. Alternatively, after removing the second copper layers 546a and 546b and the first copper layers 544a and 544b, the second stacked structure 500 may be processed to form the via holes 710a and 710b.

7C, a via layer 720c, 720d filling the via holes 710a, 710b and a second circuit (not shown) disposed on the primer layers 542a, 542b of the fifth and sixth unit stack 540a, Pattern layers 720a and 720b are formed. The method of forming the second circuit pattern layers 720a and 720b may be performed by the SAP. The SAP may be performed in substantially the same manner as the SAP in the above-described embodiment with reference to FIG. 3C.

7D, sixth and seventh prepreg layers 730a and 730b are formed on both surfaces of the second stacked structure 500 in which the second circuit pattern layers 720a and 720b are formed, 740a and 740b are laminated to form a third laminated structure 700. [ The seventh and eighth unit laminates 740a and 740b respectively include primer layers 742a and 742b, first copper layers 744a and 744b and second copper layers 746a and 746b that are sequentially stacked can do.

7E, the third stacked structure 700 is separated and the first and second circuit boards 70a and 70b including the first circuit pattern layers 510a and 510b and the second circuit pattern layers 710a and 710b , 72 and a second copper layer 226b, 226c on both surfaces. Specifically, in the process of separating the third stacked structure 700, first, the second copper layers 746a and 746b of the seventh and eighth unit stack bodies 740a and 740b exposed to the outside are removed. The first copper layer 224b and the second copper layer 226b of the second unit laminate 220b are separated from each other and the first copper layer 224c and the second copper layer 226b of the third unit laminate 220c are separated, (226c) are separated from each other.

The first circuit board 70 thus has the primer layer 222d of the fourth unit laminate body 220d disposed between the third prepreg layer 210c and the first circuit pattern layer 510a, And a primer layer 542a of a sixth unit laminate body 540a disposed between the prepreg layer 530a and the second circuit pattern layer 720a. The second circuit board 72 includes a primer layer 222a of the first unit laminate body 220a disposed between the first prepreg layer 210a and the first circuit pattern layer 510b, And a primer layer 542b of the fifth unit laminate body 540b disposed between the leg layer 530b and the second circuit pattern layer 720b. The base substrate 74 may have second copper layers 226b and 226c stacked on both surfaces of the second prepreg layer 210b.

The first circuit pattern layers 510a and 510b and the second circuit pattern layers 710a and 710b of the first and second circuit boards 70 and 72 are electrically connected to the primer layers 222a, 222d, 542a, and 542b And can be stably formed on the prepreg layers 210a, 210c, 530a, and 530b by the SAP.

In the case of the first and second circuit boards 70 and 72, the circuit pattern layer, the solder mask pattern, and the surface treatment layer formation process by the SAP in the embodiment described above with reference to FIGS. 6A to 6D can be performed. At this time, the number of circuit pattern layers formed by the SAP is not limited. That is, by repeating the above-described step of laminating the insulating interlayer substrate and the step of forming the circuit pattern layer by SAP, an intended number of circuit pattern layers can be formed.

In the case of the base substrate 74, the circuit pattern layer forming process by the tenting method in the embodiment described above with reference to Figs. 4A to 4D can be performed.

As described above, according to the embodiments, the prepreg can be easily adopted as the insulating layer, which can prevent the occurrence of warpage even though the thickness is reduced due to the large rigidity. That is, the bonding force between the prepreg layer and the chemical plating layer can be improved by interposing the primer layer between the prepreg layer and the chemical plating layer. Thereby, the copper pattern layer through the SAP process can be reliably formed on the insulating layer.

According to one embodiment, a plurality of unit laminate layers including a primer layer and a copper layer are bonded to a plurality of prepreg layers, and the copper layer is removed or separated, thereby forming the primer layer on the prepreg layer The base substrate and the circuit board can be manufactured at the same time.

As described above, according to the embodiment of the present invention, it is possible to reduce the thickness of the insulating layer and to miniaturize the circuit pattern, thereby making it possible to manufacture a thin printed circuit board having a fine pattern.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

100a, 100b: printed circuit board, 110: through via layer, 112a 112b: first via layer
114a 114b: second via layer, 120a 120b: first circuit pattern layer,
122 132 142 152 162 172: circuit pattern layer, 124 134 144 154 164: via layer
130a 130b: second circuit pattern layer, 140a 140b: third circuit pattern layer,
150a: bump, 150b: solder ball, 160a 160b: interlayer insulating layer, 180: interlayer insulating layer
170a 170b: third insulating layer, 200: laminated structure,
20 22: a first base substrate, 24: a second base substrate,
210a 210b 210c: first to third prepreg layers,
220a 220b 220c 220d: first to fourth unit laminations,
222a 222b 222c 222d: primer layer,
224a 224b 224c 224d: a first copper layer,
226a 226b 226c 226d: a second copper layer,
227b 227c: a second copper layer of reduced thickness,
310: hole, 320a 320b 320c: copper pattern layer,
330a, 330b: solder mask pattern, 340a 340b: surface treatment layer,
400: hole, 410a: via layer, 410b 410c: circuit pattern layer,
420: solder mask pattern,
50 52: first and second circuit substrates, 54: base substrate, 500: second stacked structure,
510a 510b: a first circuit pattern layer,
540a 540b: fifth and sixth unit laminate,
542a 542b: primer layer, 544a 544b: primary copper layer,
546a 546b: secondary copper layer,
610a 610b: via hole, 620a 620b: second circuit pattern layer, 620c: via layer,
630a 630b: solder mask pattern, 640a 640b: surface treatment layer,
700: third stack structure, 70 72: first and second circuit substrates, 74: base substrate,
710a 710b: via hole, 720a 720b: second circuit pattern layer,
720c 720d: via layer,
730a 730b: prepreg layer,
740a 740b: seventh and eighth unit laminate,
742a 742b: primer layer,
744a 744b: primary copper layer, 746a 746b: secondary copper layer.

Claims (18)

(a) preparing a unit laminate in which a primer layer, a first copper layer and a second copper layer are sequentially laminated;
(b) preparing a prepreg layer;
(c) forming a laminated structure by bonding the unit laminate to the prepreg layer such that both surfaces of the prepreg layer and the primer layer face each other; And
(d) separating the first copper layer and the second copper layer of the unit laminate from the laminated structure so that the primer layer and the first copper layer are laminated on both surfaces of the prepreg layer, Lt; RTI ID = 0.0 >
A method of manufacturing a printed circuit board. The method according to claim 1,
(d) further removing the first copper layer of the unit laminate to expose the primer layer
A method of manufacturing a printed circuit board. (a) preparing first to fourth unit stacks in which a primer layer, a first copper layer and a second copper layer are sequentially laminated;
(b) preparing first to third prepreg layers;
(c) a step of stacking the first unit laminate, the first prepreg layer, the second unit laminate, the second prepreg layer, the third unit laminate, the third prepreg layer, The first unit laminate and the second unit laminate are arranged such that the primer layers of the first unit laminate and the second unit laminate are in contact with both surfaces of the first prepreg layer, Placing the primer layers of the third unit laminate and the fourth unit laminate in contact with both surfaces of the third prepreg layer; And
(d) separating the first copper layer and the second copper layer of the first through fourth unit stacks from each other to produce a base substrate,
A method of manufacturing a printed circuit board. The method of claim 3,
(d)
Removing the exposed second copper layer from the first unit stack;
Separating the first copper layer and the second copper layer of the second unit laminate from each other;
Separating the first copper layer and the second copper layer of the third unit laminate from each other; And
Removing the second copper layer exposed outward from the fourth unit laminate
A method of manufacturing a printed circuit board. The method of claim 3,
The base substrate
A pair of first base substrates on which the primer layer and the first copper layer are sequentially laminated on both surfaces of the first and third prepreg layers; And
And a second base substrate on which the second copper layer is laminated on both surfaces of the second prepreg layer
A method of manufacturing a printed circuit board. 6. The method of claim 5,
Removing the first copper layer from the first base substrate;
Further comprising forming a circuit pattern layer on the primer layer of the first base substrate
A method of manufacturing a printed circuit board. The method according to claim 6,
The step of forming the circuit pattern layer
Forming a hole through the first base substrate;
Removing the first copper layer from the first base substrate; And
Forming a plating pattern layer by performing a semi-additive process (SAP) on the inside of the hole and on the primer layer from which the first copper layer has been removed
A method of manufacturing a printed circuit board. 6. The method of claim 5,
And forming a circuit pattern layer on the second base substrate
A method of manufacturing a printed circuit board. 9. The method of claim 8,
The step of forming the circuit pattern layer
Forming a hole through the second base substrate;
Half-etching the second copper layer;
Forming a copper plating layer on the inside of the hole and on the half-etched second copper layer; And
And patterning the copper plating layer by tenting.
A method of manufacturing a printed circuit board. (a) preparing first to fourth unit stacks in which a primer layer, a first copper layer and a second copper layer are sequentially laminated;
(b) preparing first to third prepreg layers;
(c) a step of stacking the first unit laminate, the first prepreg layer, the second unit laminate, the second prepreg layer, the third unit laminate, the third prepreg layer, The first unit laminate and the second unit laminate are arranged so that the primer layers of the first unit laminate and the second unit laminate are in contact with both surfaces of the first prepreg layer, Placing the primer layers of the third unit laminate and the fourth unit laminate in contact with both surfaces of the third prepreg layer;
(d) removing the first copper layer and the second copper layer of the first unit laminate, the first copper layer and the second copper layer of the fourth unit laminate from the first laminate structure Exposing the primer layer of the first unit laminate and the primer layer of the fourth unit laminate;
(e) forming a first circuit pattern layer on the primer layer of the first unit laminate and the fourth unit laminate;
(f) a fourth prepreg layer and a fifth unit laminate are sequentially laminated on one surface of the first laminate structure on which the first circuit pattern layer is formed, and on the other surface of the first laminate structure, a fifth prepreg layer And the sixth unit laminate are sequentially laminated to form a second laminated structure, wherein the fifth unit laminate and the sixth unit laminate are formed by sequentially laminating a primer layer, a first copper layer, and a second copper layer, And allowing the primer layer of the fifth unit laminate and the sixth unit laminate to contact the both surfaces of the first laminate structure, respectively; And
(g) removing the first copper layer and the second copper layer of the second unit laminate, the third unit laminate, the fifth unit laminate and the sixth unit laminate from the second laminate structure, And separating the first circuit pattern layer and the second circuit pattern layer from each other to manufacture a base substrate having first and second circuit boards including the first circuit pattern layer and the second copper layer on both surfaces
A method of manufacturing a printed circuit board. 11. The method of claim 10,
The step of forming the first circuit pattern layer on the primer layer of the first unit laminate and the fourth unit laminate includes
And a step of forming a plating pattern layer by performing a semi-specific method on the primer layer
A method of manufacturing a printed circuit board. 11. The method of claim 10,
The step of separating the second stacked structure
Removing the second copper layer of the fifth and sixth unit stacks exposed to the outside;
Separating the first copper layer and the second copper layer of the second unit laminate from each other;
And separating the first copper layer and the second copper layer of the third unit stack from each other
A method of manufacturing a printed circuit board. 11. The method of claim 10,
Wherein the first circuit board includes:
And the primer layer of the fourth unit laminate disposed between the third prepreg layer and the first circuit pattern layer, and the primer layer of the fifth unit laminate disposed on the fourth prepreg layer, And,
Wherein the second circuit board comprises:
The primer layer of the first unit laminate disposed between the first prepreg layer and the first circuit pattern layer, and the primer layer of the sixth unit laminate disposed on the fifth prepreg layer, having a
A method of manufacturing a printed circuit board. 11. The method of claim 10,
Forming a via hole for exposing the first circuit pattern layer by processing the first or second circuit board;
Removing the first copper layer from the first or second circuit board; And
Further comprising the step of forming a via layer filling the via hole and a second circuit pattern layer disposed on the primer layer of the first or second circuit board by semi-
A method of manufacturing a printed circuit board. (a) preparing first to fourth unit stacks in which a primer layer, a first copper layer and a second copper layer are sequentially laminated;
(b) preparing first to third prepreg layers;
(c) a step of stacking the first unit laminate, the first prepreg layer, the second unit laminate, the second prepreg layer, the third unit laminate, the third prepreg layer, The first unit laminate and the second unit laminate are arranged so that the primer layers of the first unit laminate and the second unit laminate are in contact with both surfaces of the first prepreg layer, Placing the primer layers of the third unit laminate and the fourth unit laminate in contact with both surfaces of the third prepreg layer;
(d) removing the first copper layer and the second copper layer of the first unit laminate, the first copper layer and the second copper layer of the fourth unit laminate from the first laminate structure Exposing the primer layer of the first unit laminate and the primer layer of the fourth unit laminate;
(e) forming a first circuit pattern layer on the primer layer of the first unit laminate and the fourth unit laminate;
(f) a fourth prepreg layer and a fifth unit laminate are sequentially laminated on one surface of the first laminate structure on which the first circuit pattern layer is formed, and on the other surface of the first laminate structure, a fifth prepreg layer And the sixth unit laminate are sequentially laminated to form a second laminated structure, wherein the fifth unit laminate and the sixth unit laminate are formed by sequentially laminating a primer layer, a first copper layer, and a second copper layer, And allowing the primer layer of the fifth unit laminate and the sixth unit laminate to contact the both surfaces of the first laminate structure, respectively;
(g) In the second laminated structure, after removing the second copper layer of the fifth unit laminate and the second copper layer of the sixth unit laminate, the second laminate structure is processed to form the first Forming a via hole for exposing the circuit pattern layer and removing the first copper layer;
(h) forming a via layer filling the via hole, and a second circuit pattern layer disposed on the primer layer of the fifth unit laminate and the sixth unit laminate;
(i) a sixth prepreg layer and a seventh unit laminate are laminated on one surface of the second laminate structure on which the second circuit patter layer is formed, and a seventh prepreg layer and a sixth prepreg layer are laminated on the other surface of the second laminate structure, 8 unit laminate are laminated to form a third laminate structure, wherein the seventh unit laminate and the eighth unit laminate include a primer layer, a first copper layer and a second copper layer which are sequentially laminated ;
(j) removing the first copper layer and the second copper layer of the eighth unit laminate from the third laminate structure, wherein the second unit laminate, the third unit laminate, the seventh unit laminate, Forming first and second circuit boards including the first circuit pattern layer and the second circuit pattern layer and a base substrate having the second copper layer on both surfaces thereof,
A method of manufacturing a printed circuit board. 16. The method of claim 15,
Wherein forming the first circuit pattern layer and the second circuit pattern layer comprises:
A step of forming a plating pattern layer by performing a semi-
A method of manufacturing a printed circuit board. 16. The method of claim 15,
The step of separating the third stack structure
Removing the second copper layer of the seventh and eighth unit laminate exposed to the outside;
Separating the first copper layer and the second copper layer of the second unit laminate from each other;
And separating the first copper layer and the second copper layer of the third unit stack from each other
A method of manufacturing a printed circuit board. 16. The method of claim 15,
Wherein the first circuit board includes:
And the primer layer of the fourth unit laminate disposed between the third prepreg layer and the first circuit pattern layer, and the fifth prepreg layer and the second circuit pattern layer, And the primer layer of the unit laminate,
Wherein the second circuit board comprises:
And the primer layer of the first unit laminate disposed between the first prepreg layer and the first circuit pattern layer, and the primer layer of the sixth prepreg layer and the second circuit pattern layer, And the primer layer of the unit laminate
A method of manufacturing a printed circuit board.

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