KR101466524B1 - Method for manufacturing package substrate for semiconductor element mounting - Google Patents

Method for manufacturing package substrate for semiconductor element mounting Download PDF

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KR101466524B1
KR101466524B1 KR1020137005647A KR20137005647A KR101466524B1 KR 101466524 B1 KR101466524 B1 KR 101466524B1 KR 1020137005647 A KR1020137005647 A KR 1020137005647A KR 20137005647 A KR20137005647 A KR 20137005647A KR 101466524 B1 KR101466524 B1 KR 101466524B1
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South Korea
Prior art keywords
metal foil
carrier
foil
carrier metal
step
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KR1020137005647A
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Korean (ko)
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KR20130043684A (en
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타다시 타무라
마나부 스기바야시
쿠니지 스즈키
키요오 핫토리
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히타치가세이가부시끼가이샤
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Priority to JPJP-P-2010-218898 priority Critical
Priority to JP2010218898 priority
Priority to JP2011207249A priority patent/JP5896200B2/en
Priority to JPJP-P-2011-207249 priority
Application filed by 히타치가세이가부시끼가이샤 filed Critical 히타치가세이가부시끼가이샤
Priority to PCT/JP2011/072423 priority patent/WO2012043742A1/en
Publication of KR20130043684A publication Critical patent/KR20130043684A/en
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Publication of KR101466524B1 publication Critical patent/KR101466524B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0147Carriers and holders
    • H05K2203/0152Temporary metallic carrier, e.g. for transferring material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1536Temporarily stacked PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Abstract

It is possible to improve the yield of the product by suppressing the adhesion of the resin powder and to form an embedding circuit which does not cause undercut so that an adhesive layer can be formed which has fine adhesion and can form an outer layer circuit on the surface of the insulating layer, A method for manufacturing a package substrate for mounting a semiconductor element capable of forming various metal structures such as a bump or a filler by forming a three-dimensional circuit at a location. A step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated and laminating them with a base material to form a core substrate, a step of physically peeling the first carrier metal foil of the multilayer metal foil, A step of forming a laminate by laminating an insulating layer on the first pattern plating; a step of separating the laminate from the core substrate together with the second carrier metal foil; And a step of forming an etching resist on the second carrier metal foil of one stack and etching the same.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a package substrate for mounting a semiconductor element,

The present invention relates to a method of manufacturing a package substrate for mounting a semiconductor element capable of high density.

As electronic components become smaller and higher in density, a systemized package substrate for mounting semiconductor elements (hereinafter also referred to as " package substrate ") is required. In a package on package (PoP) represented by a SiP (System in Package), in recent years, a package in which a plurality of semiconductor elements are stacked on one package substrate has become mainstream. Accordingly, in the package substrate for PoP, it is necessary to dispose the connection terminals with the semiconductor elements at a high density, and it is required to make the outer layer circuit (outer layer circuit) finer.

As a method of forming a fine outer layer circuit, an interlayer connection hole (interlayer connection hole) is provided in an insulating substrate (thin substrate) having a thin copper foil of about 2 mu m in thickness, and a thickness of 0.1 A plating resist is formed thereon, and a part to be an outer layer circuit is thickened by pattern electroplating. Then, the plating resist is removed, and the entire surface is etched. Thus, (That is, only a thin portion of the conductor) is removed to form an outer layer circuit (Patent Document 1).

In addition, a supporting substrate is provided with an insulating resin on the copper copper foil of the carrier of the ultra-thin copper foil (ultra-thin copper foil having a thickness of 1 to 5 占 퐉) with a physically peelable carrier copper foil, The support substrate including the carrier copper foil is physically peeled off and further the ultra thin copper foil is removed by etching to form a fine outer layer circuit (Patent Document 2).

In addition, a wiring film of a predetermined pattern is formed on the surface of the intermediate film of the carrier film, an electrically conductive filler is formed by pattern plating on the surface of the wiring film, and two wiring members each having an interlayer insulating film formed thereon are prepared, And the interlayer is etched to remove the carrier film as an etch stop layer, and furthermore, the interlayer is removed by etching to form the interconnection (Patent Document 3).

[Patent Literature]

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-140176

Patent Document 2: JP-A-2005-101137

Patent Document 3: JP-A-2006-135277

However, in the method of Patent Document 1, a thin copper foil provided on an insulating substrate and a thinly-attached electroless (electroless) copper plating are used as a power supply layer for patterned electroplating. Therefore, when the entire surface is etched after pattern electroplating, The etching is required to a thickness equal to the thickness of the layer (the feeder layer, the thin copper foil and the thinned electroless copper plating). When the feed layer is removed by this etching, an undercut tends to occur. For this reason, the substantial contact width between the outer layer circuit to be formed and the insulating substrate is reduced, and it is difficult to form a fine outer layer circuit having a line / space of 15 mu m / 15 mu m or less. Further, since the surface of the patterned electroplated copper becomes the surface of the outer layer circuit, surface irregularities are likely to be generated in the outer layer circuit, and the surface irregularities are further increased at the time of etching.

In addition, in the method of Patent Document 2, when the support substrate is formed by laminating the insulating resin on the surface of the ultra-thin copper foil having the carrier copper (thickness of 1 to 5 mu m), the surface of the ultra- There is a case where the resin powder of the resin is adhered to the copper foil and the resin powder adhered to the ultra-thin copper foil may cause a decrease in the product yield when the ultra-thin copper foil is processed to form a fine outer layer circuit.

Further, in the method of Patent Document 3, the intermediate film is etched away as an etching stop layer, and the intermediate film is removed by etching, but defects such as pinholes are liable to be generated in the etching stop layer, And etching is performed in two steps. Therefore, the unevenness of the surface of the formed outer layer circuit is increased, and there is a possibility that the reliability of connection with the semiconductor element is lowered.

In addition, flip chip connection or wire bonding connection is used for electrical connection between the semiconductor element and the connection terminal of the package substrate. However, since the connection terminal becomes finer, the influence of the surface irregularities on the connection reliability tends to increase. For this reason, it is required to planarize the surface of the outer layer circuit to be a connection terminal. On the other hand, depending on the connection form with the mounted semiconductor element, it may be required to form a bump or a filler.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide an embedded circuitry capable of improving product yield by suppressing the adhesion of resin powder and not causing undercut, A method for manufacturing a package substrate for mounting a semiconductor element capable of forming a flat outer layer circuit and forming a variety of metal structures such as a bump or a pillar by forming a solid circuit at an arbitrary location is provided do.

The present invention relates to the following contents.

(1) A multilayer metal foil in which a first carrier metal foil, a second carrier foil and a base metal foil are laminated in this order is prepared, and a base metal foil side of the multilayer foil is laminated with a base material to form a core board A step of physically peeling off a first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil; A step of forming a laminate by laminating an insulating layer on a second carrier metal foil including the first pattern plating; and a step of forming a laminate by laminating an insulating layer between the second carrier metal foil and the base metal foil of the multilayer metal foil, Separating and physically separating the second carrier metal foil from the core substrate together with the second carrier metal foil, and forming an etching resist on the second carrier metal foil of the peeled laminate W subjected to the etching, the first pattern or the plating method for manufacturing a package substrate for mounting a semiconductor device having a step of forming a three-dimensional circuit by the rest of the second carrier foil on the insulating layer.

(2) a step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated in this order, forming a core substrate by laminating a base metal foil side of the multilayer metal foil and a base material, A step of physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the first carrier metal foil of the core metal foil, A step of forming a laminate by laminating an insulating layer on a second carrier metal foil including plating; and a step of laminating the second carrier metal foil and the base metal foil of the multilayer metal foil from the core substrate A step of performing second pattern plating on the second carrier metal foil of the peeled laminate, A step of removing the second carrier metal foil other than the portion where the two-pattern plating is performed by etching to form the second pattern plating remaining on the first patterned plating layer or the insulating layer and the three- Wherein the package substrate is provided with a semiconductor substrate.

(3) a step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated in this order, forming a core substrate by laminating a base metal foil side of the multilayer metal foil and a base material, A step of physically peeling the first carrier metal layer between the first carrier metal foil and the second carrier metal foil of the first carrier metal foil of the first carrier metal foil, A step of forming a laminate by laminating an insulating layer on a second carrier metal foil including plating; and a step of laminating the second carrier metal foil and the base metal foil of the multilayer metal foil from the core substrate And removing the second carrier metal foil of the separated laminate to remove the first pattern plating from the first pattern plating, Method for manufacturing a package substrate for mounting a semiconductor device having a step of exposing the surface of the layer.

(4) The multilayer metal foil according to any one of (1) to (3), wherein the peeling strength between the second carrier metal foil and the base metal foil is larger than the peeling strength between the first carrier metal foil and the second carrier metal foil Wherein the multi-layer metal foil is a formed multi-layer metal foil.

(5) The multilayered metal foil according to any one of (1) to (5), wherein the first carrier copper foil is laminated on the surface of the second carrier copper foil provided with unevenness having an average roughness (Ra) Wherein the multilayer metal foil is a multilayer metal foil.

According to the present invention, it is possible to form an outer layer circuit having a fine adhesion and a smooth surface by forming an embedding circuit which can improve product yield by suppressing adhesion of resin powder and does not cause undercut, It is possible to provide a method of manufacturing a package substrate for mounting a semiconductor element capable of forming various metal structures such as a bump or a filler by forming a solid circuit at an arbitrary position.

1 is a cross-sectional view of a multilayer metal foil used in the present invention.
2 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
3 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention.
4 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
5 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
6 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
7 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
8 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.
9 is a cross-sectional view of a semiconductor package manufactured by using the method for manufacturing a package substrate of the present invention.
10 is a flowchart showing a part of a method of manufacturing a package substrate of the present invention.

An example of a method of manufacturing a package substrate of the present invention will be described below with reference to Figs. 1 to 8. Fig.

First, as shown in Fig. 1, a multilayer metal foil 9 is prepared by laminating a first carrier foil 10, a second carrier foil 11, and a base foil 12 in this order.

The first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) and is physically peeled off from the second carrier foil 11 . The material and thickness of the second carrier metal foil 11 are not particularly limited as long as the surface of the second carrier metal foil 11 can be protected. However, copper foil or aluminum foil is preferable as the material in terms of versatility and handleability. desirable. It is preferable to provide a peeling layer 13 between the first carrier metal foil 10 and the second carrier metal foil 11 for stabilizing the peeling strength between the metal foils 10 and 11, As for the layer 13, it is preferable that the peeling strength is stabilized even when heating and pressing are repeated a plurality of times when laminated with the insulating resin. As the release layer 13, there can be used those having a metal oxide layer and an organic agent layer disclosed in Japanese Patent Application Laid-Open No. 2003-181970, those made of a Cu-Ni-Mo alloy disclosed in Japanese Patent Application Laid-Open No. 2003-094553, Those containing Ni and W metal oxides or Ni and Mo metal oxides as disclosed in WO2006 / 013735. When the first carrier metal foil 10 is physically peeled off between the second carrier metal foil 11, the peeling layer 13 is peeled in a state of being attached to the first carrier metal foil 10 side, But does not remain on the surface of the second carrier metal foil 11.

The second carrier metal foil 11 is a seed layer for supplying a current to perform a first pattern plating 18 on the surface of the first carrier foil 10 after peeling off the first carrier metal foil 10, So that it can be physically peeled off between the metal foil 10 and the base metal foil 12. The base metal foil 12 may function as a power supply layer. Particularly, the material and the thickness are not limited. However, copper foil or aluminum foil is preferable as the material in terms of versatility and handleability, and a thickness of 1 to 18 μm can be used. 7 (n), 8 (n), and 10 (m)) when the outer layer circuit 2 is formed as described later, In order to form a high-precision fine circuit, an ultra-thin metal foil of 1 to 5 m is preferable. In order to stabilize the peeling strength between the first carrier metal foil 10 and the base metal foil 12 and between the first and second carrier foils 10 and 12, 13, and 14, respectively. It is preferable that the release layer 14 has conductivity so that the second carrier metal foil 11 and the base metal foil 12 become integral with each other to function as a seed layer. The release layer 14 is preferably transferred to the base metal foil 12 when the second carrier metal foil 11 and the base metal foil 12 are physically peeled off. As a result, since the surface of the second carrier metal foil 11 is exposed on the side of the laminate 22 after the base metal foil 12 is peeled off, the etching of the second carrier metal foil 11, (14).

The base metal foil 12 is located on the side where the multilayer metal foil 9 is laminated with the base material 16 when the core substrate 17 is manufactured by laminating the multilayer metal foil 9 with the base material 16, As shown in Fig. When it is laminated with the base material 16, the material and the thickness are not particularly limited as long as the base material 16 has adhesion with the base material 16, but a copper foil or an aluminum foil is preferable as the material in terms of versatility and handling properties. desirable. In order to stabilize the peeling strength between the metal foil 11 and the second carrier metal foil 11, it is preferable to provide the peeling layer 14 as described above.

The multilayer metal foil 9 is a multilayer metal foil 9 having three or more metal foils (for example, the first carrier metal foil 10 and the second carrier foil 11 and the base metal foil 12 as described above) (Between the first carrier metallic foil 10 and the second carrier metallic foil 11 and between the second carrier metallic foil 11 and the base metallic foil 12, for example, as described above) Use the peelable one. In the step of forming the core substrate 17 by laminating the base material 16 on the base metal foil 12 side of the multilayer metal foil 9, the surface of the first carrier metal foil 10 is coated with a resin powder or the like The first carrier metallic foil 10 is physically peeled off from the second carrier metallic foil 11 to prevent foreign matter such as resin powder from adversely affecting the foreign matter. Since the surface of the two-carrier metal foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the first patterned plating 18 is performed by using the second carrier metal foil 11 as a seed layer, generation of defects can be suppressed, so that it is possible to improve the product yield.

Next, as shown in Fig. 2 (a), the core metal foil 9 side of the base metal foil 12 and the base material 16 are laminated to form a core substrate 17. The base material 16 is used as the insulating layer 3 of the package substrate 1 for mounting a semiconductor element as the base material 16 Can be used. Examples of the substrate 16 include glass epoxy, glass polyimide and the like. The core substrate 17 serves as a support substrate when the package substrate 1 is manufactured by using the multilayer metal foil 9 and it is possible to improve the workability by securing the rigidity, The main role is to prevent the damage of the city and improve the product yield. For this purpose, it is preferable that the base material 16 has a reinforcing material such as glass fiber. For example, a prepreg such as glass epoxy or glass polyimide is superimposed on the multilayer metal foil 9, And then heating and pressing them to form a laminated body. Layer metal foil 9 is laminated on both sides of the base material 16 (both upper and lower sides in Fig. 2 (a)), and the subsequent steps are carried out to carry out a step of manufacturing two package substrates 1 in a single step Therefore, the number of process steps can be reduced. Further, since the laminated board having a configuration symmetrical to both sides of the core substrate 17 can be formed, warpage can be suppressed, and damage due to workability and contact with manufacturing facilities can be suppressed.

Next, as shown in Fig. 2 (b), the first carrier metallic foil is physically peeled off between the first carrier metallic foil 10 and the second carrier metallic foil 11 of the multilayer metallic foil 9. Foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10 from a prepreg or the like serving as a material of the base material 16 during lamination. Therefore, in the case of forming a circuit using the first carrier metal foil 10, defects such as disconnection or short circuit may occur due to foreign matters such as resin powder attached to the surface, There is a possibility that it is connected to the degradation. However, by peeling off the first carrier metal foil 10 in this way, a circuit can be formed by using the second carrier foil 11 to which no foreign matter such as resin powder is adhered, Can be suppressed and the yield of the product can be improved. In addition, since the first carrier metal foil 10 can be physically peeled off, the peeling strength between the first carrier metal foil 10 and the second carrier foil 11 can be adjusted, have. At this time, the peeling layer 13 between the first carrier metallic foil 10 and the second carrier metallic foil 11 of the multilayer metallic foil 9 is shifted to the first carrier metallic foil 10 side desirable. As a result, since the surface of the second carrier metal foil 11 is exposed on the second carrier metal foil 11 side after the first carrier metal foil 10 is peeled off, the surface of the second carrier foil 11 on the second carrier foil 11 The formation of the plating resist and the formation of the first pattern plating 18 on the release layer 13 are not inhibited by the release layer 13.

The peeling strength between the second carrier metal foil 11 and the base metal foil 12 is greater than the peeling strength between the first carrier foil 10 and the second carrier foil 11 It is preferable that the multilayer metal foil 9 is formed largely. As a result, when the first carrier metallic foil 10 and the second carrier metallic foil 11 are physically peeled off, separation between the second carrier metallic foil 11 and the base metallic foil 12 can be suppressed at the same time . As the peeling strength, the first carrier metal foil 10 and the second carrier metal foil 11 (before the heating and pressurization (before the core substrate 17 is formed by laminating the prepregs as the base material 16) The first carrier metal foil 10 and the second carrier metal foil 11 are disposed at a ratio of 2 N / m to 50 N / m between the first carrier metal foil 11 and the base metal foil 12, The peel strength between the second carrier metal foil 11 and the base metal foil 12 is smaller than the peel strength between the second carrier metal foil 11 and the base metal foil 12 by 5 N / m to 20 N / (After the core substrate 17 is formed by laminating prepregs to be the base material 16) is set to be about 20% or less of the initial peeling strength, peeling is not caused in handling in the manufacturing process . On the other hand, when the first carrier metal foil 10 is peeled off, the second carrier metal foil 11 is easily peeled off even after heating and pressing, It can be suppressed from peeling off at the time of good workability.

The adjustment of the peel strength can be carried out, for example, as shown in Japanese Patent Laid-open Publication No. 2003-181970, Japanese Patent Application Laid-Open No. 2003-094553 and Japanese Patent Application Laid-Open No. WO2006 / 013735, (The surface on the side of the first carrier metal foil 10) of the first carrier metal foil 10, or adjusting the plating liquid composition and conditions for forming the metal oxide or the alloy plating layer to be the release layer.

Next, as shown in Fig. 2 (c), the first pattern plating 18 is performed on the second carrier metal foil 11 remaining on the core substrate 17. Then, as shown in Fig. As described above, no foreign matters such as resin powder are adhered to the surface of the second carrier metal foil 11 (the surface of the first carrier foil 10 side) from the prepreg or the like used in the lamination, Thereby making it possible to suppress a circuit defect caused thereby. The first pattern plating 18 can be performed using electroplating after a plating resist (not shown) is formed on the second carrier metal foil 11. As the plating resist, a photosensitive resist used in a manufacturing process of a general package substrate can be used. As electroplating, copper sulfate plating used in a general package substrate manufacturing process can be used.

The multilayer metal foil 9 is formed by laminating the first carrier metal foil 10 on the surface of the second carrier metal foil 11 having the roughness Ra of 0.3 to 1.2 탆, Layered metal foil (9). Thereby, the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is physically peeled off together with the release layer 13 has an average roughness (Ra) of 0.3 to 1.2 m . Therefore, when the plating resist for the first patterned plating 18 is formed on the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) The resolution can be improved, which is advantageous for forming a high-density circuit. The surface of the second carrier metallic foil 11 is previously roughened so that the surface of the second carrier metallic foil 11 is roughened after the first carrier metallic foil 10 is peeled off The number of process steps can be reduced.

The surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 has an average roughness Ra of 0.3 to 1.2 占 퐉 so that the peeling after the first pattern plating 18 It is preferable from the viewpoint of securing the property. If the average roughness (Ra) is less than 0.3 탆, insufficient adhesion of the plating resist tends to occur. If the average roughness (Ra) exceeds 1.2 탆, the plating resist tends to follow and tends to lack adhesion . In addition, when the line / space of the plating resist becomes finer than 15 탆 / 15 탆, the average roughness (Ra) is preferably 0.5 탆 to 0.9 탆. Here, the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001) and can be measured using a touch-type surface roughness machine or the like. The adjustment of the average roughness Ra can be made by adjusting the composition (including additives and the like) of the copper electroplating when forming the copper foil as the second carrier metal foil 11 and the conditions Current density, time, etc.).

3 (d), the insulating layer 3 is laminated on the second carrier metal foil 11 including the first patterned plating 18 to form the laminated body 22. Next, as shown in Fig. As the insulating layer 3, those generally used as the insulating layer 3 of the package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin and a polyimide resin. Examples of the insulating layer 3 include epoxy-based or polyimide-based adhesive sheets, prepregs such as glass epoxy and glass polyimide, And heating and pressurizing them to form a laminated body. Here, the laminate 22 refers to a laminate formed on the second carrier metal foil 11 including the first pattern plating 18 among the laminated and integrated states. In the case where the metal foil to be the conductor layer 20 is further superimposed on such a resin as the insulating layer 3 and heated and pressed at the same time to form a laminated body, this conductor layer 20 is also included. In the case of forming the inner layer circuit 6 by the conductor layer 20 or forming the interlayer connection 5 for connecting the conductor layer 20 as will be described later, the inner layer circuit 6 and the interlayer connection (5).

Next, as shown in Figs. 3 (e) and 3 (f), an interlayer connection hole (layer interconnection hole) 21 may be formed to form the interlayer connection 5 and the inner layer circuit 6. [ The interlayer connection 5 can be formed, for example, by forming an interlayer connection hole 21 by using a so-called conformal method and then plating the inside of the interlayer connection hole 21. For this plating, electroless copper plating, electroless copper plating, field via plating or the like can be used as thick plating after performing thin-plate electroless copper plating as a base plating. In order to make the thickness of the conductor layer 20 to be etched thin to make it easy to form a fine circuit, it is preferable to form the plating resist after the thin plating base plating and thickly adhere the plating by electroplating or field via plating . The inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary portion of the conductor layer 20 by etching.

Next, as shown in Figs. 4 (g) and 4 (h) and 5 (i) and 5 (j), the insulating layer 3 and the conductor layer 20 The inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 may be formed so as to have the desired number of layers as in the case of Figs. 3 (e) and 3 (f).

Next, as shown in FIG. 6 (k), the multilayer body 22 is sandwiched between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, Physically peeled off from the core substrate 17 and separated. At this time, it is preferable that the peeling layer 14 between the second carrier metal foil 11 and the base metal foil 12 of the multi-layer metal foil 9 migrates to the base metal foil 12 side. As a result, since the surface of the second carrier metal foil 11 is exposed on the side of the layered product 22 after the base metal foil 12 has been peeled off, the etching of the second carrier metal foil 11, (14).

Next, as shown in Figs. 7 (1), (m), and (n), an etching resist 25 is formed on the second carrier metal foil 11 of the layered body 22, The second patterned metal foil 11 of the second patterned metal layer 22 is etched and the first patterned plating 18 is exposed on the surface of the insulating layer 3 and the first patterned plating 18 or the insulating layer 3 And a molded circuit 24 is formed on the circuit board 24. As shown in Figs. 8 (1), 8 (m), and 8 (n), the second pattern plating 23 is performed on the second carrier metal foil 11 of the laminated body 22, The second carrier metal foil 11 other than the portion where the two-pattern plating 23 is performed is removed by etching to expose the first pattern plating 18 on the surface of the insulating layer 3, A solid circuit 24 may be formed on the insulating layer 18 or on the insulating layer 3. [ 10 (1), (m), and (n), the second carrier metal foil 11 of the separated laminate 22 is removed by etching or the like, and the first pattern plating 18 is removed And exposed to the surface of the insulating layer 3. 6 (k), 7 (1), 7 (m), 7 (n), 8 (1) Only the lower portion of the stacked body 22 is shown. As a result, when the outer layer circuit 2 is formed, the side surface of the outer layer circuit 2 is not eroded by etching, so that undercut is not caused and the fine outer layer circuit 2 can be formed. The outer layer circuit 2 formed in the present invention is in a state of being embedded with the insulating layer 3 so that not only the bottom surface of the outer layer circuit 2 but also both side surfaces are in close contact with the insulating layer 3, Even in a fine circuit, sufficient adhesion can be ensured. In addition, when the ultra-thin copper foil (ultra-thin copper foil) having a thickness of 1 m to 5 m is used as the second carrier metal foil 11, the second carrier foil 11 can be removed even with a small etching amount And the surface of the outer layer circuit 2 exposed from the insulating layer 3 is flat and the connection reliability at the time of wire bonding or flip chip connection can be ensured and the connection with the semiconductor element Terminal. Further, since the connection terminals to the semiconductor elements can be provided in the outer layer circuit 2 at a position overlapping with the interlayer connection 5 in plan view, the connection terminals to the semiconductor elements can be disposed immediately above the interlayer connection 5 It is possible to equip it directly underneath, and it is possible to cope with miniaturization and high density. In addition, by forming the solid circuit 24 at an arbitrary position, various metal structures such as bumps and pillars can be formed. By changing the thicknesses of the second carrier metal foil 11 and the second pattern plating 23, It is possible to cope with various semiconductor devices (not shown) and connection forms with other package substrates. For example, as shown in Fig. 9, a PoP can be formed without providing a cavity.

Next, a solder resist (4) or a protective plating (8) may be formed as necessary. As the protective plating 8, nickel plating and gold plating, which are generally used for protective plating of connection terminals of a package substrate, are preferable.

As described above, according to the method for manufacturing a package substrate of the present invention, it is possible to form a package substrate having a flat and fine embedded circuitry at a position overlapping the interlayer connection, and a package suitable for wire bonding or flip- A substrate can be formed. Further, a package substrate having various metal structures such as a bump or a filler can be formed by forming a three-dimensional circuit at an arbitrary position.

Example

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to this embodiment.

(Example 1)

First, as shown in Fig. 1, a multilayer metal foil 9 formed by laminating a first carrier foil 10, a second carrier foil 11, and a base foil 12 in this order was prepared. The first carrier metal foil 10 uses a copper foil of 9 mu m, the second carrier foil 11 uses an ultra-thin copper foil of 3 mu m and the base metal foil 12 uses a copper foil of 18 mu m. A release layer 14 was provided on the surface of the base metal foil 12 (on the surface of the second carrier metal foil 11) so that physical separation was possible. On the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side), unevenness with an average roughness (Ra) of 0.7 占 퐉 was prepared in advance. In addition, a peeling layer 13 was provided between the first carrier metal foil 10 and the irregularities so that physical peeling was possible. The peeling layers 13 and 14 between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier foil 11 and the first carrier foil 10 are made of Ni , Molybdenum (Mo), and citric acid was used to form a metal oxide layer. The adjustment of the peel strength was carried out by adjusting the amount of metal oxide forming the peeling layers 13 and 14 by adjusting the current density and time. The initial peel strength of the base metal foil 12 and the second carrier metal foil 11 before heating / pressing (before the core substrate 17 is formed by laminating the prepreg to be the base material 16) The distance between the second carrier metal foil 11 and the first carrier foil 10 was 29 N / m. Further, the rate of change of the peel strength after heating and pressing (after the prepregs to be the substrate 16 were laminated to form the core substrate 17) was about 10% higher than the initial rate.

The multilayer metal foil 9 shown in Fig. 1 was produced specifically as follows.

(1) An electrolytic copper foil having a thickness of 18 占 퐉 was used as the base metal foil 12, and the substrate was immersed in sulfuric acid at 30 g / L for 60 seconds to clean the acid, washed with water for 30 seconds, .

(2) A plating bath containing Ni (nickel), Mo (molybdenum), and citric acid as a positive electrode for a Ti electrode plate coated with a washed electrolytic copper foil as a negative electrode and having iridium oxide coated thereon was mixed with 30 g / L of lactic acid nickel hexahydrate Dm < 2 >) of a current density of 20 A / dm < 2 > was applied to the shiny side of the electrolytic copper foil in a tank of 3.0 g / L of sodium molybdate dihydrate, 30 g / L of trisodium citrate dihydrate, For 5 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum.

(3) A Ti electrode plate coated with iridium oxide in a bath of 200 g / L of copper sulfate pentahydrate, 100 g / L of sulfuric acid and a liquid temperature of 40 DEG C was used as a positive electrode on the surface after the release layer 14 was formed, Electrolytic plating was performed at a current density of 4 A / dm 2 for 200 seconds to form a metal layer to be a second carrier metal foil 11 having a thickness of 3 탆.

(4) Electrolytic treatment was carried out for 10 seconds at a current density of 10 A / dm 2 on the surface of the second carrier metal foil 11 after forming the metal layer using the bath (2) A peeling layer 13 containing a metal oxide made of molybdenum was formed.

(5) The surface after the release layer 13 was formed was electrolytically plated for 600 seconds at a current density of 4 A / dm 2 using the same set as in the above (3) to form a first carrier metal foil 10 ) Was formed.

(6) Grain-shaped coarse particles were formed on the surface in contact with the base material 16 by copper sulfate plating, and chromating treatment and silane coupling agents treatment were carried out. Further, the surface not in contact with the base material 16 was subjected to a chromate treatment.

Next, as shown in Fig. 2 (a), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17. A multilayer metal foil 9 was laminated on both upper and lower sides of the prepreg, and the laminate was integrated by heating and pressing using a hot press.

Next, as shown in Fig. 2 (b), the first carrier metallic foil 10 was physically peeled off between the first carrier metallic foil 10 and the second carrier metallic foil 11 of the multilayer metallic foil 9 .

Next, as shown in Fig. 2 (c), the first pattern plating 18 was performed on the second carrier metal foil 11 remaining on the core substrate 17. [ The first pattern plating 18 was formed by forming a photosensitive plating resist on the second carrier metal foil 11 and then using copper sulfate electroplating.

3 (d), an insulating layer 3 and a copper foil (12 占 퐉) are laminated as a conductor layer 20 on the second carrier metal foil 11 including the first patterned plating 18. Then, Thereby forming the layered product 22. [ As the insulating layer 3, an epoxy-based adhesive sheet was formed by heating and pressing using a hot press to laminate and integrate.

Next, as shown in Figs. 3 (e) and 3 (f), the interlayer connection 5 and the inner layer circuit 6 were formed. The interlayer connection 5 is formed by forming an interlayer connection hole 21 using a conformal method and plating the interlayer connection hole 21. In this plating, a thin plating electroless copper plating was performed as a base plating, a photosensitive plating resist was formed, and thick plating was performed by copper sulfate electroplating. Thereafter, the conductor layer 20 in an unnecessary portion was removed by etching to form the inner layer circuit 6.

Next, as shown in Figs. 4 (g) and 4 (h) and 5 (i) and 5 (j), the insulating layer 3 and the conductor layer 20 were further formed and an inner layer circuit 6, outer layer circuits 2 and 7 and an interlayer connection 5 were formed to form a layered body 22 having four conductor layers 20.

Next, as shown in FIG. 6 (k), the multilayer body 22 is sandwiched between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, Physically separated from the core substrate 17 and separated.

Next, as shown in Figs. 7 (1), (m) and (n), etching resist is formed on the second carrier metal foil 11 of the laminated body 22, The second patterned metal foil 11 is etched and the first patterned plating 18 is exposed on the surface of the insulating layer 3 and the first patterned plating 18 is formed on the first patterned plating 18 or on the insulating layer 3 A molded circuit 24 was formed.

Next, a photosensitive solder resist was formed, and then electroless nickel plating and electroless gold plating were performed as protective plating to form a package substrate.

(Example 2)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) The amount of metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current density and time at the time of forming the metal oxide layer using a plating bath containing citric acid. Specifically, electrolytic treatment was carried out at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytic treatment at a current density of 7.5 A / dm 2 for 15 seconds To form a release layer 13 containing a metal oxide of nickel and molybdenum. The initial peel strength before heating and pressing at this time was set to 23 N / m between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier foil 11 and the first carrier foil 10 Lt; RTI ID = 0.0 > N / m. Further, the peel strength after heating and pressing was about 10 to 20% higher than the initial peel strength. A package substrate was produced in the same manner as in Example 1 except for the above.

(Example 3)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) The amount of metal oxide forming the release layers 13 and 14 was adjusted by changing the current at the time of forming the metal oxide layer using a plating bath containing citric acid. Specifically, electrolytic treatment was carried out at a current density of 5 A / dm 2 for 20 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytically treated at a current density of 2 A / dm 2 for 20 seconds , And a release layer 13 containing a metal oxide composed of nickel and molybdenum. The initial peel strength before heating and pressing at this time is set to 15 N / m between the base metal foil 12 and the second carrier metal foil 11, the second carrier metal foil 11 and the first carrier metal foil 10, Was 2 N / m. Further, the peel strength after heating and pressing was about 10 to 20% higher than the initial peel strength. A package substrate was produced in the same manner as in Example 1 except for the above.

(Example 4)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) By changing the current at the time of forming the metal oxide layer using a plating bath containing citric acid, the amount of metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment was carried out at a current density of 25 A / dm 2 for 4 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytically treated at a current density of 20 A / dm 2 for 4 seconds , And a release layer 13 containing a metal oxide composed of nickel and molybdenum. The initial peel strength before heating and pressing at this time was 68 N / m between the base metal foil 12 and the second carrier foil 11 and between the second carrier foil 11 and the first carrier foil 10, Was 48 N / m. The peel strength after heating and pressing was about 5 to 10% higher than that at the initial stage.

(L), (m), and (n) in place of the steps shown in Figs. 7 (1), (m), and (n) The second patterned plating 23 is performed on the second carrier metal foil 11 of the laminated body 22 which has been peeled off separately and the second patterned metal foil 11 The first pattern plating 18 is exposed on the surface of the insulating layer 3 and the third circuit 24 is formed on the first pattern plating 18 or the insulating layer 3, . A package substrate was produced in the same manner as in Example 1 except for this process.

(Example 5)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) By changing the current at the time of forming the metal oxide layer using a plating bath containing citric acid, the amount of metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment was carried out at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytically treated at a current density of 10 A / dm 2 for 10 seconds , And a release layer 13 containing a metal oxide composed of nickel and molybdenum. The initial peel strength before the heating and pressing at this time was 43 N / m between the base metal foil 12 and the second carrier foil 11 and between the second carrier foil 11 and the first carrier foil 10, Was 28 N / m. The peel strength after heating and pressing was about 10 to 15% higher than that at the initial stage. A package substrate was produced in the same manner as in Example 4 except for the above.

(Example 6)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) By changing the current at the time of forming the metal oxide layer using a plating bath containing citric acid, the amount of metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment was carried out at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytically treated at a current density of 2.5 A / dm 2 for 40 seconds , And a release layer 13 containing a metal oxide composed of nickel and molybdenum. The initial peel strength before heating and pressing at this time was 22 N / m between the base metal foil 12 and the second carrier foil 11 and between the second carrier foil 11 and the first carrier foil 10, Was 4 N / m. Further, the peel strength after heating and pressing was about 5 to 15% higher than the initial peel strength. A package substrate was produced in the same manner as in Example 4 except for the above.

(Example 7)

The peel strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier foil 10 are both Ni (nickel), Mo (molybdenum) By changing the current at the time of forming the metal oxide layer using a plating bath containing citric acid, the amount of metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment was carried out at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide of nickel and molybdenum and electrolytically treated at a current density of 10 A / dm 2 for 10 seconds , And a release layer 13 containing a metal oxide composed of nickel and molybdenum. The initial peel strength before heating and pressing was 45 N / m between the base metal foil 12 and the second carrier foil 11, and between the second carrier foil 11 and the first carrier foil 10, Was 26 N / m. Further, the peel strength after heating and pressing was about 10% higher than the initial peel strength.

Instead of the steps shown in Figs. 7 (1), 7 (m), and 7 (n) of Example 1 using the multi-layered metal foil 9 prepared above, The second carrier metal foil 11 of the laminated body 22 which has been separated and peeled off is removed by etching and the first pattern plating 18 is exposed on the surface of the insulating layer 3 to form the insulating layer 3 The embedded outer layer circuit 2 was formed. A package substrate was produced in the same manner as in Example 1 except for this process.

Table 1 shows the relationship between the completion state of the outer layer circuit 2 formed in the insulating layer 3 and the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11 in Examples 1 to 7, The peel strength between the second carrier metal foil 11 and the base metal foil 12, and the peeling off of the carrier metal foil during handling. In each of Examples 1 to 7, a fine outer layer circuit 2 having a line / space of up to 10 mu m / 10 mu m could be formed ("O" in Table 1 indicates no undercut). In addition, as a result of observing the cross section, no undercut occurred. In addition, from the observation results of the cross section, the second carrier metal foil 11 uses a polar beating of 3 mu m so that it is uniformly removed with a slight etching amount, and the surface of the outer layer circuit 2 is almost flat. In Examples 1 to 6, the first carrier metal foil 10 and the second carrier metal foil 11 were bonded together by the handling in the manufacturing process, and the second carrier metal foil 11 and the base metal foil 12 There was nothing to peel off ("o" in Table 1 indicates no peeling). Further, when peeling off between the first carrier metal foil 10 and the second carrier foil 11, there was no peeling between the second carrier foil 11 and the base foil 12.

Item Line / space (占 퐉 / 占 퐉) Peel strength (N / m) Peeling of metal foil when handling 10/10 15/15 20/20 First carrier metal foil / second carrier metal foil Second carrier metal foil / base metal foil Example 1 29 47 Example 2 18 23 Example 3 2 15 Example 4 48 68 Example 5 28 43 Example 6 4 22 Example 7 26 45

The initial peel strength (N / m) before the heating and pressurization (before the core substrate 17 was formed by laminating prepregs to be the substrate 16) was measured by cutting A multilayer metal foil sample was prepared and subjected to a 90 degree pulling and peeling test according to JIS Z 0237 using Tensilon RTM-100 (trade name, Tensilon, a trade name, manufactured by ORIENTECH CORPORATION) The first carrier metal foil was peeled off at a rate of 300 mm per minute in a direction of 90 degrees and then the second carrier metal foil was peeled off at a rate of 300 mm per minute in a direction of 90 degrees. The peeling strength after heating and pressing (after the prepregs to be the substrate 16 were laminated to form the core substrate 17) was measured to be the same as the initial peeling strength, and the change rate at the initial stage was obtained . The heating and pressing conditions for forming the core substrate 17 by laminating the multilayer metal foil 9 and the glass epoxy prepreg for forming the substrate 16 were a vacuum press and a pressure of 3 MPa and a temperature of 175 DEG C , And the holding time is 1.5 hr.

1: Package substrate for mounting a semiconductor element
2: outer layer circuit or buried circuit
3: Insulating layer
4: Solder resist
5: Interlayer connection
6: Inner layer circuit
7: outer layer circuit
8: Protection plating
9: multilayer metal foil
10: first carrier metal foil
11: second carrier metal foil
12: Base metal foil
13: Release layer
14: Release layer
16: substrate
17: Core substrate
18: 1st pattern plating
20: conductor layer
21: interlayer connection hole
22:
23: Second pattern plating
24:
25: etching resist
26: Solder
27: Semiconductor device
28: semiconductor package
29: Seal material

Claims (5)

  1. A step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated in this order, forming a core substrate by laminating a base metal foil side of the multi-
    A step of physically peeling the first carrier metal foil between the first carrier metallic foil and the second carrier metallic foil of the multi-
    Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
    A step of laminating an insulating layer on a second carrier metal foil including the first pattern plating to form a laminate,
    Separating the multilayer body from the core substrate together with the second carrier metal foil and separating the second multilayer metal foil from the second carrier metal foil and the base metal foil;
    Forming an etching resist on the second carrier metal foil of the peeled laminate to perform etching and forming a solid circuit by the second patterned metal foil or the second carrier foil remaining on the insulating layer
    Of the package substrate.
  2. A step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated in this order, forming a core substrate by laminating a base metal foil side of the multi-
    A step of physically peeling the first carrier metal foil between the first carrier metallic foil and the second carrier metallic foil of the multi-
    Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
    A step of laminating an insulating layer on a second carrier metal foil including the first pattern plating to form a laminate,
    Separating the multilayer body from the core substrate together with the second carrier metal foil and separating the second multilayer metal foil from the second carrier metal foil and the base metal foil;
    A step of performing second pattern plating on the second carrier metal foil of the peeled laminate,
    The second carrier metal foil other than the portion where the second pattern plating is performed is removed by etching and the second pattern plating remaining on the first patterned plating layer or the insulating layer and the second carrier metal foil to form a three- fair
    Of the package substrate.
  3. A step of preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil and a base metal foil are laminated in this order, forming a core substrate by laminating a base metal foil side of the multi-
    A step of physically peeling the first carrier metal layer between the first carrier metal foil and the second carrier metal foil of the multi-
    Performing a first pattern plating on the second carrier metal foil remaining on the core substrate;
    A step of laminating an insulating layer on a second carrier metal foil including the first pattern plating to form a laminate,
    Separating the multilayer body from the core substrate together with the second carrier metal foil and separating the second multilayer metal foil from the second carrier metal foil and the base metal foil;
    Removing the second carrier metal foil of the separated laminate and exposing the first pattern plating to the surface of the insulating layer
    Of the package substrate.
  4. 3. The method according to claim 1 or 2,
    Wherein the multilayered metal foil is a multilayered metal foil in which the peel strength between the second carrier metal foil and the base metal foil is larger than the peel strength between the first carrier metal foil and the second carrier metal foil.
  5. 4. The method according to any one of claims 1 to 3,
    Wherein the multilayer metal foil is a multilayer metal foil in which a first carrier copper foil is laminated on a surface of a second carrier copper foil provided with unevenness with an average roughness (Ra) of 0.3 to 1.2 mu m in advance.
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JPJP-P-2011-207249 2011-09-22
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WO2017204553A1 (en) * 2016-05-27 2017-11-30 (주) 화인켐 Fine-wiring flexible circuit board and manufacturing method therefor

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