CN102544269A - Manufacturing method for LED chip with micro-cylinder lens array patterns on side wall - Google Patents
Manufacturing method for LED chip with micro-cylinder lens array patterns on side wall Download PDFInfo
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- CN102544269A CN102544269A CN2012100557904A CN201210055790A CN102544269A CN 102544269 A CN102544269 A CN 102544269A CN 2012100557904 A CN2012100557904 A CN 2012100557904A CN 201210055790 A CN201210055790 A CN 201210055790A CN 102544269 A CN102544269 A CN 102544269A
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Abstract
The invention provides a manufacturing method for an LED chip with micro-cylinder lens array patterns on the side wall. The manufacturing method comprises the following steps: growing an epitaxial layer and a current diffusion on a substrate layer sequentially from top to bottom; photoetching by using a photoetching plate with an arc-shaped array and table-board patterns on the side wall; forming photoresist on the current diffusion layer, wherein the photoresist is provided with side micro-cylinder lens array and table-board patterns; performing wet chemical etching on the current diffusion layer by using the photoresist as a mask; performing dry etching on the epitaxial layer by continuously using the photoresist as the mask to form the table-board; removing the photoresist and forming the epitaxial layer with the micro-cylinder lens array patterns on the side wall and the current diffusion layer with the arc-shaped array patterns on the side wall respectively; and manufacturing a P electrode on the current diffusion layer and manufacturing an N electrode on the table-board. According to the manufacturing method, cost is taken into consideration, process flow is simplified, technological complexity is reduced, technological stability is improved, and light extraction efficiency of the LED chip is improved.
Description
Technical field
The invention belongs to luminescent device and make the field, relate in particular to the manufacturing approach that a kind of sidewall has the led chip of microtrabeculae lens arra pattern.
Background technology
Raising along with the high speed development and the electrical efficiency of semiconductor integrated technology; With the III group-III nitride is light-emitting diode (the Light Emitting Diode of material; LED) as a kind of new type light source, use more and more extensivelyr, extensively applied to before and after backlight and the automobile of traffic lights, full color display, liquid crystal display screen lamp etc.; This new type light source has plurality of advantages such as energy-saving and environmental protection, life-span length, and is expected to become the developing direction of new generation of green environmental protection solid-state illumination.
Yet the manufacturing cost of LED and electrical efficiency are the principal elements that its alternative conventional light source of restriction is applied to the speed of illuminating industry.Single LEDs crystal grain electrical efficiency is low; High-power LED lighting fixture must be made up of plurality of LEDs crystal grain connection in series-parallel more so; This directly causes the cost of high-power LED lighting fixture to increase; And electric energy to be converted into the efficient of light outgoing low more,, device junction temperature just more according to the heat energy that stores in the conservation of energy chip material rises, light fixture is in the material selection of cooling system, the increase that design can cause the various costs in the LED industrial chain.Obviously; If the electrical efficiency of single LEDs improves, the quantity of light outgoing increases under the similarity condition, and then identical high-power LED lighting fixture can dispose some LED crystal grain less; The heat energy that transforms by electric energy still less, light fixture is in the input that material is selected, design aspect can reduce cost of cooling system.So, the manufacturing cost of LED electrical efficiency decision product, both inversely proportional relations.
The LED electrical efficiency is mainly by electric current injection efficiency, internal quantum efficiency and get the product decision of optical efficiency.Wherein, the electrode design of chip and ohmic contact resistance influence the electric current injection efficiency, and the general electric current injection efficiency of chip preferably can reach more than 90%.Internal quantum efficiency is mainly by growth technology, material behavior and the decision of gap structure designing institute; The current challenge that faces mainly exists p-GaN (P type gallium nitride) the doping difficulty that lacks suitable backing material, high-quality, high hole concentration, the problems such as dislocation density height of active layer material InGaN (indium gallium nitride); However; GaN (gallium nitride) epitaxial wafer generally can reach the internal quantum efficiency more than 70% at present, and along with the development of technology is also improving year by year.Compare the above two, getting optical efficiency is to influence the low substantive reason of LED electrical efficiency.Because the wide part that the LED lighting sends at active area is from the top outgoing of p type island region, and the refractive index difference of semi-conducting material and air is bigger, for example GaN material refractive index is 2.5; Air refraction is 1.0; In the time of can causing the light air little from the big semi-conducting material of refractive index to refractive index, both have total reflection at the interface, the angle of total reflection is about 23 °; Therefore, most of light are owing to full emission is limited in chip; Simultaneously; The phenomenon of light lateral transport in chip clearly; Because there is certain absorption in semi-conducting material to light, each also has certain loss to light at the interface, when light repeatedly comes transmission back in chip again; Can constantly be absorbed and lose, the light that produces on the active layer of undressed LED only has few part outgoing to go out.So, cause at last entire chip to get optical efficiency lower.
At present, commonly usedly pass through to improve LED and get the technology that optical efficiency improves the electrical efficiency of led light source chip and comprise chip surface roughening process and micro lens technology.The chip surface coarsening technique normally utilizes dry method or methods such as wet-chemical chamber, deposit to make originally smooth interface become periodic regular (like photonic crystal) or texture structure at random; Change some incidence angle when active area sends or after reflection light arrives active area and air interface in chip; If this moment, incidence angle was less than 23 °; Light can be expected to outgoing in the circular light cone, improves and gets optical efficiency.A kind of method that improves light efficiency in p-GaN face wet-chemical etching alligatoring of carrying out to the chip surface roughening process in the prior art.As everyone knows, grow in the GaN crystal of Sapphire Substrate generally speaking, crystal face outwardly is the very strong Ga atomic plane of corrosion resistance, and conventional etching condition is difficult to surface coarsening.Based on this thought, this method is passed through the long Mg of p-GaN surface regeneration (magnesium) highly doped (10
20Atoms/cm
3) the p-GaN layer because the p-GaN layer carry out Mg highly doped after, its Ga face and N (nitrogen) face can realize the counter-rotating make corrosion-prone N atomic plane outwardly, use thermokalite KOH (potassium hydroxide) solution can realize surface coarsening then.Nonetheless, because the conductivity of high Mg doped p-GaN layer is relatively poor,, otherwise too thinly also be unfavorable for alligatoring if the too thick forward voltage that will certainly cause increases.So there be the complexity and the stability problem of technology in this technology.
Micro lens technology then is to utilize methods such as dry etching, ion beam ball milling or photoresist backflow to make micron-sized periodicity lens or half-cylindrical lens arra at chip surface; Can know the bright dipping best results for the spherical convex surface of point-source of light by theory, this technology has been proved to be has remarkable effect to improving the LED light efficiency.The preparation method of a kind of all-side-wall saw-tooth coarsened light-emitting diode chip that carries out to micro lens technology in the prior art; Adopt jagged Mesa (table top) mask and the photoetching of jagged ITO (tin indium oxide) mask to add etching respectively and obtain side-wall saw-tooth coarsened n-GaN table top and ITO current-diffusion layer; Improved the LED luminous efficiency; But this sidewall coarsening technique adopts the twice photoetching, and technological process is simplified inadequately; Cost increases and because hard roasting backflow of photoresist is difficult to form the pattern of desirable pointed sawtooth, actual controllability is not strong.The preparation method of another kind of little (cylindricality) lens pattern of carrying out to micro lens technology in the prior art, this method reach and improve the light efficiency effect through making little (cylindricality) convex lens pattern at p-GaN face, Sapphire Substrate and n-GaN face.But these work or need make reticle or laser lift-off in addition, shortcomings such as loaded down with trivial details, the controlled difficulty of technology is big, cost height.
Yet, no matter be for chip surface alligatoring or micro lens technology, be to apply to p-GaN (P type gallium nitride) face, n-GaN (n type gallium nitride) face or the work of Sapphire Substrate face at present mostly; These methods generally all need be added some technologies; Make reticle like other, perhaps use expensive equipment and complicated technology, like need laser lift-off equipment etc.; Even if improved the light extraction efficiency of LED; But uneconomical from cost, the surface coarsening technology of relatively cheap wet-chemical etching is still immature, does not generally also adopt in the industry.And fewer to the alligatoring of chip sidewall and micro lens technology utilization, high temperature corrosion (Sidewall Etching) technology of oppose side wall also needs special etching apparatus usually, and is dangerous and stable inadequately.
In order to address the above problem; Need seek a kind of cost of taking into account pays, simplifies under the prerequisite of technological process; The realization led chip is got the process that optical efficiency promotes, and cost height, technology exist process complexity and the not high problem of stability in the production led chip process to solve.
Summary of the invention
The purpose of this invention is to provide the manufacturing approach that a kind of sidewall has the led chip of microtrabeculae lens arra pattern, to take into account the cost expenditure, simplify technological process, reduce process complexity, when promoting technology stability, and the realization led chip is got the lifting of optical efficiency.
For addressing the above problem, the invention provides the manufacturing approach that a kind of sidewall has the led chip of microtrabeculae lens arra pattern, comprise the steps:
Grown epitaxial layer and current-diffusion layer successively from the bottom to top on a substrate;
The reticle of utilizing sidewall to have circular arc array and table top pattern is carried out photoetching process, on said current-diffusion layer, forms photoresist, and said photoresist sidewall has microtrabeculae lens arra and table top pattern;
With said photoresist is mask, and current-diffusion layer is carried out the wet-chemical over etching;
Continuation is a mask with said photoresist, and epitaxial loayer is carried out dry etching, forms table top;
Remove said photoresist, form sidewall respectively and have the epitaxial loayer of microtrabeculae lens arra pattern and the current-diffusion layer that sidewall has the circular arc pattern;
On said current-diffusion layer, make the P electrode, on said table top, make the N electrode.
Visible by technique scheme; Compare with the chip surface alligatoring or the micro lens technology manufacturing process of traditional common, sidewall disclosed by the invention has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, earlier at the substrate growing epitaxial layers; The technology that forms current-diffusion layer is prepended to before the mesa etch technology; The reticle that has circular arc array pattern and a table top pattern through sidewall is then carried out design transfer, has realized the sidewall microtrabeculae lens pattern etching of led chip and the sidewall circular arc array pattern etching of current-diffusion layer, optimizes the technological process that has improved chip; Reduce lithography step; When reducing cost, promote the electrical efficiency of LED effectively, and then improved led chip brightness.
Description of drawings
Fig. 1 has the flow chart of manufacturing approach of the led chip of microtrabeculae lens arra pattern for the sidewall of one embodiment of the invention;
Fig. 2 a to Fig. 2 f is the device sketch map in the manufacturing approach of the led chip of the sidewall of one embodiment of the invention with microtrabeculae lens arra pattern.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual manufacturing, should comprise in addition, length, width and the degree of depth.
Be example with method flow shown in Figure 1 below, in conjunction with accompanying drawing 2a to 2f, the manufacturing approach that oppose side wall has the led chip of microtrabeculae lens arra pattern is described in detail.
The manufacturing approach that said sidewall has the led chip of microtrabeculae lens arra pattern comprises:
S100: grown epitaxial layer and current-diffusion layer successively from the bottom to top on a substrate.
At first, referring to Fig. 2 a, a substrate 200 is provided, said substrate 200 is a Sapphire Substrate.On said substrate 200, adopt metal organic chemical vapor deposition technology (MOVCD) grown epitaxial layer 202, said epitaxial loayer 202 comprises resilient coating 204, n type gallium nitride layer 206, multiple quantum well layer 208 and P type gallium nitride layer 210 from the bottom to top successively.Wherein, multiple quantum well layer 208 comprise a plurality of barrier layers and with a plurality of active layers of the mutual alternating growth of a plurality of barrier layers be potential well layer, the energy bandgaps of active layer is less than the energy bandgaps of adjacent barrier layer, and decision emission wavelength, color etc.
Then,, clean said epitaxial loayer 202 earlier, on said epitaxial loayer 202, deposit tin indium oxide (ITO) again, form transparent current-diffusion layer 212, to improve the luminous exitance of led chip of subsequent technique preparation through evaporation process referring to Fig. 2 b.
S101: the reticle of utilizing sidewall to have circular arc array and table top pattern is carried out photoetching process, on said current-diffusion layer, forms photoresist, and said photoresist sidewall has microtrabeculae lens arra and table top pattern.
Referring to Fig. 2 c; First spin coating photoresist on said current-diffusion layer 212; And photoetching processes such as the reticle of utilizing sidewall to have circular arc array and table top pattern is made public, development, on said current-diffusion layer 212, form the photoresist 214 that sidewall has compact arranged microtrabeculae lens arra and table top pattern.
S102: with said photoresist is mask, and current-diffusion layer is carried out the wet-chemical over etching.
Referring to Fig. 2 d; The photoresist 214 that has microtrabeculae lens arra and table top pattern with sidewall is a mask, and said current-diffusion layer 212 is carried out the wet-chemical over etching, and current-diffusion layer 212 is contracted in etching has microtrabeculae lens arra and a table top pattern along sidewall photoresist 214 carries out slightly; Because the thickness of current-diffusion layer deposition is with respect to the diameter of its sidewall circular arc; Can ignore, therefore, the pattern that forms at the sidewall of said current-diffusion layer 212 can be described as the circular arc array pattern.
S103: continuing with said photoresist is mask, and epitaxial loayer is carried out etching.
Referring to Fig. 2 e, continuation is a mask with the photoresist 214 that sidewall has microtrabeculae lens arra and table top pattern, and said epitaxial loayer 202 is carried out ICP (inductively coupled plasma) etching, forms table top 218.Said table top 218 runs through current-diffusion layer 212, P type gallium nitride layer 210, multiple quantum well layer 208 from top to bottom successively, and etching stopping is in said n type gallium nitride layer 206.
S104: remove said photoresist, form sidewall respectively and have the epitaxial loayer of microtrabeculae lens arra pattern and the current-diffusion layer that sidewall has the circular arc pattern.
Continuation after removal has the photoresist 214 of sidewall microtrabeculae lens arra and table top pattern, has formed microtrabeculae lens arra and circular arc array pattern respectively referring to Fig. 2 e on the sidewall of epitaxial loayer 202 and current-diffusion layer 212.
Wherein, The diameter of said circular arc is a micron level; And its size can be adjusted according to the resolution of mask aligner under the condition that lithographic accuracy guarantees, thus through around the compact arranged circular arc array pattern size that shifts the microtrabeculae lens arra pattern of preparation also can adjust through the adjustment of circular arc.
Because said current-diffusion layer 212 is to form before mask carries out etching technics at the photoresist that has microtrabeculae lens arra and table top pattern with sidewall 214; Therefore; The optimization of the formation of follow-up led chip having been carried out technological process improves; Reduce lithography step, when having reduced cost, realized the sidewall microtrabeculae lens arra patterning etching of led chip and the sidewall circular arc array pattern etching of transparent current-diffusion layer; Promote the electrical efficiency of LED effectively, and then improved led chip brightness.
S105: on said current-diffusion layer, make the P electrode, on said table top, make the N electrode.
Referring to Fig. 2 f, with general photoetching process, ion beam evaporation process, peel off (lift-off) technology and annealing process, on said current-diffusion layer 212, make P electrode 220, make N electrodes 222 at said table top 218, form led chip.
Wherein, the material of said P electrode 220 and N electrode 222 can be chromium gold (Cr/Au) alloy or chromium platinum alloy (Cr/Pt/Au) or nickel gold (Ni/Au) alloy or other metals.
Certainly; Can also the deposit passivation layer (not shown) on epitaxial loayer 202 sidewalls and surface in said led chip structure, on the surface of current-diffusion layer 212 and on the said table top 218; To avoid the damage on led chip surface, the material of said passivation layer can be silica (SiO
2).
Visible by technique scheme; Compare with the chip surface alligatoring or the micro lens technology manufacturing process of traditional common, sidewall disclosed by the invention has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, earlier at the substrate growing epitaxial layers; The technology that forms current-diffusion layer is prepended to before the etching technics; The reticle that has circular arc array pattern and a table top pattern through sidewall is then carried out pattern transfer, has showed the sidewall microtrabeculae lens arra patterning etching of led chip and the sidewall circular arc array pattern etching of transparent current-diffusion layer, optimizes the technological process that has improved chip; Reduce lithography step; When reducing cost, promote the electrical efficiency of LED effectively, and then improved led chip brightness.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (6)
1. a sidewall has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, comprising:
Grown epitaxial layer and current-diffusion layer successively from the bottom to top on a substrate;
The reticle of utilizing sidewall to have circular arc array and table top pattern is carried out photoetching process, on said current-diffusion layer, forms photoresist, and said photoresist sidewall has microtrabeculae lens arra and table top pattern;
With said photoresist is mask, and current-diffusion layer is carried out the wet-chemical over etching;
Continuation is a mask with said photoresist, and epitaxial loayer is carried out dry etching, forms table top;
Remove said photoresist, form sidewall respectively and have the epitaxial loayer of microtrabeculae lens arra pattern and the current-diffusion layer that sidewall has the circular arc array pattern;
On said current-diffusion layer, make the P electrode, on said table top, make the N electrode.
2. sidewall according to claim 1 has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, it is characterized in that: said epitaxial loayer comprises resilient coating, n type gallium nitride layer, multiple quantum well layer and P type gallium nitride layer from the bottom to top successively.
3. sidewall according to claim 2 has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, it is characterized in that: epitaxial loayer is carried out in the step of etching, etching stopping is in said n type gallium nitride layer.
4. sidewall according to claim 1 has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, it is characterized in that: current-diffusion layer is carried out the wet-chemical over etching said current-diffusion layer is contracted in carrying out.
5. sidewall according to claim 1 has the manufacturing approach of the led chip of microtrabeculae lens arra pattern; It is characterized in that: on said current-diffusion layer, make the P electrode; On said table top, make after the N electrode, also comprise: forming passivation layer on the sidewall and surface of said epitaxial loayer, on the current-diffusion layer and on the table top.
6. sidewall according to claim 1 has the manufacturing approach of the led chip of microtrabeculae lens arra pattern, it is characterized in that: the material that said current-diffusion layer uses is tin indium oxide.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633205A (en) * | 2013-12-19 | 2014-03-12 | 聚灿光电科技(苏州)有限公司 | Production method of LED (light emitting diode) chip |
| CN104538511A (en) * | 2014-12-25 | 2015-04-22 | 聚灿光电科技股份有限公司 | LED chip with high light out-coupling efficiency and manufacturing method thereof |
| CN107293621A (en) * | 2017-07-24 | 2017-10-24 | 湘能华磊光电股份有限公司 | A kind of LED chip and preparation method thereof |
| CN107507894A (en) * | 2017-07-25 | 2017-12-22 | 厦门三安光电有限公司 | A kind of LED chip construction and preparation method thereof |
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| US20020125485A1 (en) * | 1999-12-22 | 2002-09-12 | Lumileds Lighting U.S. Llc | Semiconductor light emitting device and method |
| US20030047745A1 (en) * | 2001-08-31 | 2003-03-13 | Shin-Etsu Handotai Co., Ltd. | GaP-base semiconductor light emitting device |
| CN1489225A (en) * | 2002-10-11 | 2004-04-14 | 三星电机株式会社 | Efficient luminous diode and its manufacturing method |
| US20100123146A1 (en) * | 2008-11-19 | 2010-05-20 | Huga Optotech Inc. | Light-emitting device structure and semiconductor wafer structure with the same |
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| JPH10200156A (en) * | 1996-12-28 | 1998-07-31 | Sanken Electric Co Ltd | Semiconductor light emitting element |
| US20020125485A1 (en) * | 1999-12-22 | 2002-09-12 | Lumileds Lighting U.S. Llc | Semiconductor light emitting device and method |
| US20030047745A1 (en) * | 2001-08-31 | 2003-03-13 | Shin-Etsu Handotai Co., Ltd. | GaP-base semiconductor light emitting device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103633205A (en) * | 2013-12-19 | 2014-03-12 | 聚灿光电科技(苏州)有限公司 | Production method of LED (light emitting diode) chip |
| CN104538511A (en) * | 2014-12-25 | 2015-04-22 | 聚灿光电科技股份有限公司 | LED chip with high light out-coupling efficiency and manufacturing method thereof |
| CN107293621A (en) * | 2017-07-24 | 2017-10-24 | 湘能华磊光电股份有限公司 | A kind of LED chip and preparation method thereof |
| CN107507894A (en) * | 2017-07-25 | 2017-12-22 | 厦门三安光电有限公司 | A kind of LED chip construction and preparation method thereof |
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Application publication date: 20120704 |