CN104617191A - LED vertical chip with current block structure and preparation method thereof - Google Patents
LED vertical chip with current block structure and preparation method thereof Download PDFInfo
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- CN104617191A CN104617191A CN201510019276.9A CN201510019276A CN104617191A CN 104617191 A CN104617191 A CN 104617191A CN 201510019276 A CN201510019276 A CN 201510019276A CN 104617191 A CN104617191 A CN 104617191A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention provides a LED vertical chip with current block structure and a preparation method thereof; the method etches an area of an ITO transparent conductive layer corresponding to a vertical projection of a N electrode, uses a high contact resistance area (Schottky contact) between a P-type GaN layer and a P electrode layer to for the current block structure; in the obtained LED vertical chip, the injected current can be effectively expanded, thereby relieving the congestion of current below the N electrode, increasing the uniform distribution of the current, thus increasing the light emitting performance of the vertical structure LED. Comparing to the conventional current block technology, the provided method is simple in technology, low cost, high in yield; and the obtained LED is uneasy to peel off, thus increasing the reliability of the vertical chip.
Description
Technical field
The invention belongs to LED chip field, relate to a kind of LED vertical chip with current blocking structures and preparation method thereof.
Background technology
After Japanese Ya company in 1994 obtains important breakthrough in the research of the GaN base LED based on Sapphire Substrate, each major company of the world and research institution all join in the exploitation of high brightness GaN-based LED in input huge fund, have greatly promoted the industrialization process of high-brightness LED.Recently, due to the raising of GaN base LED luminance, make its application prospect in display, traffic lights, mobile phone backlight more wide.
Compared to the positive assembling structure of traditional GaN base LED, vertical stratification has good heat dissipation, can bearing great current, luminous intensity is high, the advantages such as power consumption is little, the life-span is long, be widely used in the fields such as general illumination, Landscape Lighting, special lighting, automotive lighting, become the solution of generation high-power GaN-based LED great potential, be just subject to industry and more and more paying close attention to and study.Vertical structure LED is by bonding chip or galvanoplastic, in conjunction with techniques such as laser lift-offs, GaN base extension is transferred to heat-conductivity conducting metal of good performance or semiconductor substrate materials from Sapphire Substrate, forms the electrode structure distributed up and down, make electric current flow vertically through whole device.As shown in Figure 1, be shown as the LED of general vertical stratification, comprise substrate, P electrode, P-GaN layer, Multiple Quantum Well (MWQ), N-GaN layer and N electrode from bottom to top successively.
But in the LED chip structure of vertical stratification, be the most concentrated region of pulse current injectingt below N electrode, this part light can be blocked by electrode or absorb finally becomes invalid luminescence, thus reduces luminous intensity and the efficiency of LED component.For addressing this problem, scheme relatively more conventional in vertical structure LED device is that introducing one current barrier layer (Current Block, CB) is to limit or significantly to reduce the luminescence of active layer below N electrode.As shown in Figures 2 and 3, be shown as the LED that two kinds have current barrier layer (CB) respectively, wherein, in LED shown in Fig. 2, current barrier layer is positioned at N-GaN layer upper surface and is covered by N electrode, in LED shown in Fig. 3, current barrier layer be positioned at P-GaN layer lower surface and cover by P electrode.
Conventional SiO in blue-light LED chip
2or Si
3n
4as current blocking layer material, but this insulating material complicated process of preparation, cost is high, more there is the problem not good with the adhesiveness of GaN, can affect the firmness of bonding chip, thus cause substrate desquamation yield reduce and affect reliability.
Therefore, a kind of LED vertical chip with current blocking structures newly and preparation method thereof is provided to be necessary to solve the problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of LED vertical chip with current blocking structures and preparation method thereof, for solving current barrier layer complicated process of preparation in prior art, not good with the adhesiveness of GaN, LED vertical chip preparation cost is caused to raise and the problem that reduces of reliability.
For achieving the above object and other relevant objects, the invention provides a kind of preparation method with the LED vertical chip of current blocking structures, at least comprise the following steps:
One substrate is provided, grows involuntary doped gan layer, N-type GaN layer, multiple quantum well layer and P type GaN layer over the substrate successively;
ITO transparency conducting layer is formed on described P type GaN layer surface;
The etching away regions corresponding with the upright projection of the follow-up N electrode that will be formed by described ITO transparency conducting layer, obtains the opening that exposes described P type GaN layer in described ITO transparency conducting layer;
P electrode layer is formed further in described ITO layer at transparent layer, described P electrode layer is filled into described opening and contacts with the P type GaN layer that described opening exposes, and the contact area of the P type GaN layer that described P electrode layer and described opening expose is as current blocking structures;
At described P electrode layer surface bond one substrate;
Remove described substrate and described involuntary doped gan layer successively, and form the Cutting Road running through described N-type GaN layer, multiple quantum well layer and P type GaN layer from top to bottom, obtain MESA table top;
N electrode is formed on described N-type GaN layer surface.
Alternatively, before described N-type GaN layer surface forms described N electrode, by described N-type GaN layer surface coarsening.
Alternatively, form reflection electrode layer and bonding metal layer successively in described ITO layer at transparent layer, described reflection electrode layer and bonding metal layer are jointly as described P electrode layer.
Alternatively, ohmic contact is between described ITO transparency conducting layer and described P type GaN layer and described P electrode layer; Be Schottky contacts between the P type GaN layer that described P electrode layer and described open bottom expose.
Alternatively, utilize wet processing to etch and obtain described opening.
Alternatively, adopt laser lift-off to remove described substrate, adopt ICP method to remove described involuntary doped gan layer.
The present invention also provides a kind of LED vertical chip with current blocking structures, comprises substrate and is formed at P electrode layer, ITO transparency conducting layer, P type GaN layer, multiple quantum well layer, N-type GaN layer and the N electrode on described substrate from bottom to top successively, wherein:
Have an opening in described ITO transparency conducting layer, the position of described opening is corresponding with the upright projection position of described N electrode on described ITO transparency conducting layer;
Described opening exposes described P type GaN layer, and described P electrode layer is filled into described opening and contacts with the P type GaN layer that described opening exposes; The contact area of the P type GaN layer that described P electrode layer and described opening expose is as current blocking structures.
Alternatively, ohmic contact is between described ITO transparency conducting layer and described P type GaN layer and described P electrode layer; Be Schottky contacts between the P type GaN layer that described P electrode layer and described open bottom expose.
Alternatively, described substrate is Si sheet, W/Cu substrate or Mo/Cu substrate.
Alternatively, described P electrode layer comprises reflection electrode layer and bonding metal layer, and wherein, described reflection electrode layer is connected with described ITO transparency conducting layer, and described bonding metal layer is connected with described substrate.
Alternatively, described N-type GaN layer surface is through roughening treatment.
As mentioned above, LED vertical chip with current blocking structures of the present invention and preparation method thereof, there is following beneficial effect: the present invention is fallen by the region etch that ITO transparency conducting layer is corresponding with the upright projection of N electrode, the high contact resistance region (Schottky contacts) between P type GaN layer and P electrode layer is utilized to form current blocking structures, thus Injection Current is effectively expanded, alleviate the crowded of N electrode low-side current, improve being uniformly distributed of electric current, thus improve the luminescent properties of vertical structure LED.Compare traditional current blocking technique, method technique of the present invention is simple, and cost is low, and production capacity is high, and the LED obtained is less likely to occur to peel off, thus improves the reliability of vertical chip.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of the LED of general vertical stratification in prior art.
Fig. 2 is shown as the schematic diagram that one in prior art has the LED of current barrier layer (CB).
Fig. 3 is shown as the schematic diagram that another kind in prior art has the LED of current barrier layer (CB).
Fig. 4 is shown as the process chart with the preparation method of the LED vertical chip of current blocking structures of the present invention.
Fig. 5 is shown as the schematic diagram growing involuntary doped gan layer, N-type GaN layer, multiple quantum well layer and P type GaN layer on substrate successively.
Fig. 6 is shown as the schematic diagram forming ITO transparency conducting layer on described P type GaN layer surface.
The region etch that Fig. 7 is shown as ITO transparency conducting layer is corresponding with the upright projection of the follow-up N electrode that will be formed falls, and obtains the schematic diagram that exposes the opening of P type GaN layer.
Fig. 8 is shown as the schematic diagram forming P electrode layer further in described ITO layer at transparent layer.
Fig. 9 is shown as the schematic diagram at described P electrode layer surface bond one substrate.
Figure 10 is shown as the schematic diagram removing described substrate.
Figure 11 is shown as and removes described involuntary doped gan layer and the schematic diagram forming Cutting Road.
Figure 12 is shown as the schematic diagram of described N-type GaN layer surface coarsening.
Figure 13 is shown as the schematic diagram forming N electrode on described N-type GaN layer surface.
Figure 14 is shown as current blocking and the current expansion effect schematic diagram of expection.
Element numbers explanation
S1 ~ S7 step
1 substrate
2 involuntary doped gan layer
3 N-type GaN layer
4 multiple quantum well layers
5 P type GaN layer
6 ITO transparency conducting layers
7 openings
8 P electrode layers
9 substrates
10 Cutting Roads
11 N electrode
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 4 to Figure 14.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The invention provides a kind of preparation method with the LED vertical chip of current blocking structures, refer to Fig. 4, be shown as the process chart of the method, at least comprise the following steps:
S1: provide a substrate, grows involuntary doped gan layer, N-type GaN layer, multiple quantum well layer and P type GaN layer over the substrate successively;
S2: form ITO transparency conducting layer on described P type GaN layer surface;
S3: the etching away regions corresponding with the upright projection of the follow-up N electrode that will be formed by described ITO transparency conducting layer, obtains the opening that exposes described P type GaN layer in described ITO transparency conducting layer;
S4: form P electrode layer in described ITO layer at transparent layer further, described P electrode layer is filled into described opening and contacts with the P type GaN layer that described opening exposes, and the contact area of the P type GaN layer that described P electrode layer and described opening expose is as current blocking structures;
S5: at described P electrode layer surface bond one substrate;
S6: remove described substrate and described involuntary doped gan layer successively, and form the Cutting Road running through described N-type GaN layer from top to bottom, obtain MESA table top;
S7: form N electrode on described N-type GaN layer surface.
First refer to Fig. 5, perform step S1: a substrate 1 is provided, described substrate 1 grows involuntary doped gan layer 2, N-type GaN layer 3, multiple quantum well layer 4 and P type GaN layer 5 successively.
Concrete, described substrate 1 can adopt sapphire, spinelle (MgAl
2o
4), SiC, ZnS, ZnO or GaAs etc. be applicable to LED chip manufacture substrate, in the present embodiment, described substrate 1 preferably adopts Sapphire Substrate.
Concrete, adopt epitaxy method to form described involuntary doped gan layer 2, N-type GaN layer 3, multiple quantum well layer 4 and P type GaN layer 5.Described involuntary doped gan layer (un-intentionally doped GaN, UID GaN) refer to and do not comprise any dopant, but the involuntary gallium nitride layer being attached to pollutant in film or impurity can be comprised, as the body layer of the N-type GaN layer 3 of next step extension.Described multiple quantum well layer (MWQ) is as the luminescent layer of LED chip.
Then refer to Fig. 6, perform step S2: form ITO transparency conducting layer 6 on described P type GaN layer 5 surface.
Concrete, adopt vapour deposition method to form described ITO transparency conducting layer 6.Described ITO transparency conducting layer 6, as current extending, plays the effect that diffusion Injection Current improves brightness.
Then refer to Fig. 7, perform step S3: the etching away regions corresponding with the upright projection of the follow-up N electrode that will be formed by described ITO transparency conducting layer 6, obtains the opening 7 that exposes described P type GaN layer 5 in described ITO transparency conducting layer 6.
Concrete, adopt the common process such as photoetching, development, etching to form described opening 7, wherein, preferably adopt wet processing etching to obtain described opening 7.It should be noted that; above-mentioned corresponding region refers to the view field of N electrode on ITO transparency conducting layer 6; but the area of described opening 7 can not be strictly equal with the area of described N electrode; except described opening 7 and the situation of described N electrode area equation; the area of described opening 7 can be slightly smaller than or be a bit larger tham the area (within ± 20%) of described N electrode, should too not limit the scope of the invention herein.
Refer to Fig. 8 again, perform step S4: form P electrode layer 8 on described ITO transparency conducting layer 6 surface further, described P electrode layer 8 is filled into described opening 7 and contacts with the P type GaN layer 5 that described opening 7 exposes, and the contact area of the P type GaN layer 5 that described P electrode layer 8 exposes with described opening 7 is as current blocking structures.
Concrete, form reflection electrode layer and bonding metal layer successively on described ITO transparency conducting layer 6 surface, described reflection electrode layer and bonding metal layer are jointly as described P electrode layer 8.Described reflection electrode layer can be single or multiple lift structure, and to comprise in the materials such as Ag, Au, Al, Ti, Ni, Pt one or more, in the present embodiment, described reflection electrode layer preferably adopts Ag.Described bonding metal layer can be also single or multiple lift structure, and to comprise in the materials such as Au, Sn, Ag, Al, Ti, Ni, Pt one or more, in the present embodiment, described bonding metal layer preferably adopts Au/Sn composite bed.
Especially, ohmic contact is between described ITO transparency conducting layer 6 and described P type GaN layer 5 and described P electrode layer 8; And be Schottky contacts between the P type GaN layer 5 of described P electrode layer 8 and described opening 7 bottom-exposed, the effect of current blocking can be played in this high contact resistance region, electric current is effectively expanded and comes, make electric current can not be crowded below N electrode, thus improve the luminous efficiency of LED vertical chip.
Then refer to Fig. 9, perform step S5: at described P electrode layer 8 surface bond one substrate 9.
Concrete, described substrate 9, as bonded substrate, can be the metal substrate of Si sheet or electric-conductivity heat-conductivity high rate, as W/Cu substrate or Mo/Cu substrate etc.It is pointed out that for W/Cu substrate, refer to that bonded substrate is at least superposed by W layer and Cu layer and once form; In like manner, be also identical rule for Mo/Cu substrate.
Refer to Figure 10 and Figure 11 again, S6: remove described substrate 1 and described involuntary doped gan layer 2 successively, and form the Cutting Road 10 running through described N-type GaN layer 3 from top to bottom, obtain MESA table top.
Concrete, as shown in Figure 10, first adopt laser lift-off to remove described substrate 1; As shown in figure 11, then adopt ICP method to remove described involuntary doped gan layer 2, and form the Cutting Road 10 running through described N-type GaN layer 3, multiple quantum well layer 4 and P type GaN layer 5 from top to bottom, obtain MESA table top.
ICP (inductively coupled plasma system) is senior sub-micron process design.ICP technique can reach the industrial standard without electric charge destruction, Min. pollution, residue removal ability, high ash rate.
Described Cutting Road 10 is for separating multiple MESA table top.In order to illustrated convenience, in Figure 11, illustrate only a MESA table top, but notice, in actual process, according to the single led chip unit area of Substrate Area and design, mark off some LED chip unit by Cutting Road.
Finally refer to Figure 12 and Figure 13, perform step S7: form N electrode 11 on described N-type GaN layer 3 surface.
Concrete, before forming described N electrode 11, can first by described N-type GaN layer 3 surface coarsening.By carrying out roughening treatment to GaN surface, formed irregular concavo-convex (as shown in figure 12), thus reduce or destroy the total reflection at GaN material and Air Interface place, the light extraction efficiency of LED can be improved.
Concrete, form described N electrode 11 by evaporation coating method, described N electrode 11 can adopt the composite constructions such as Ni/Au, Al/Ti/Pt/Au, Cr/Pt/Au.
So far, complete the making of LED vertical chip, wherein, be Schottky contacts between the P type GaN layer 5 of described P electrode layer 8 and described opening 7 bottom-exposed, this high contact resistance region is as current barrier layer.
Refer to Figure 14, be shown as current blocking and the current expansion effect schematic diagram of expection, visible, described P electrode layer 8 and the contact area of the P type GaN layer 5 of described opening 7 bottom-exposed can play the effect of obvious current blocking, electric current is effectively expanded and comes, make electric current can not be crowded below N electrode, thus improve the luminous efficiency of LED vertical chip.
Preparation method's technique with the LED vertical chip of current blocking structures of the present invention is simple, and cost is low, contributes to improving production capacity; Simultaneously owing to not needing the current barrier layer introducing other materials, directly fallen by the region etch that ITO transparency conducting layer is corresponding with the upright projection of N electrode, utilize high contact resistance region (Schottky contacts) between P type GaN layer and P electrode layer as current blocking structures, thus be not easy to cause stripping, while the luminescent properties improving vertical structure LED, improve its reliability.
Embodiment two
The present invention also provides a kind of LED vertical chip with current blocking structures, refer to Figure 13, this LED vertical chip comprises substrate 9 and is formed at P electrode layer 8, ITO transparency conducting layer 6, P type GaN layer 5, multiple quantum well layer 4, N-type GaN layer 3 and the N electrode 11 on described substrate 9 from bottom to top successively, wherein:
Have an opening in described ITO transparency conducting layer 6, the position of described opening is corresponding with the upright projection position of described N electrode 11 on described ITO transparency conducting layer 6;
Described opening exposes described P type GaN layer 5, and described P electrode layer 8 is filled into described opening and contacts with the P type GaN layer 5 that described opening exposes; The contact area of the P type GaN layer 5 that described P electrode layer 8 exposes with described opening is as current blocking structures.
Concrete, be ohmic contact between described ITO transparency conducting layer 6 and described P type GaN layer 5 and described P electrode 8; Be Schottky contacts between the P type GaN layer 5 that described P electrode layer 8 and described open bottom expose, this high resistance contact area is as the current blocking structures of LED vertical chip.
It should be noted that; the area of described opening 7 can not be strictly equal with the area of described N electrode; except described opening 7 and the situation of described N electrode area equation; the area of described opening 7 can be slightly smaller than or be a bit larger tham the area (within ± 20%) of described N electrode, should too not limit the scope of the invention herein.
Concrete, described substrate 1, as bonded substrate, includes but not limited to the metal substrate of Si sheet or electric-conductivity heat-conductivity high rate, as W/Cu substrate or Mo/Cu substrate etc.
Described P electrode layer 8 comprises reflection electrode layer and bonding metal layer, and wherein, described reflection electrode layer is connected with described ITO transparency conducting layer 6, and described bonding metal layer is connected with described 9.Described reflection electrode layer can be single or multiple lift structure, and to comprise in the materials such as Ag, Au, Al, Ti, Ni, Pt one or more, in the present embodiment, described reflection electrode layer preferably adopts Ag.Described bonding metal layer can be also single or multiple lift structure, and to comprise in the materials such as Au, Sn, Ag, Al, Ti, Ni, Pt one or more, in the present embodiment, described bonding metal layer preferably adopts Au/Sn composite bed.
Described N-type GaN layer surface can be passed through roughening treatment, is formed irregular concavo-convex, thus reduces or destroy the total reflection at GaN material and Air Interface place, can improve the light extraction efficiency of LED.
Of the present invention have in the LED vertical chip of current blocking structures, utilize high contact resistance region (Schottky contacts) between P type GaN layer and P electrode layer as current blocking structures, the position of this current blocking structures is corresponding with the upright projection region of described N electrode on described ITO transparency conducting layer, Injection Current effectively can be expanded, alleviate the crowded of N electrode low-side current, improve being uniformly distributed of electric current, thus improve the luminescent properties of vertical structure LED.Owing to not introducing other materials, LED vertical chip is less likely to occur to peel off, and reliability is improved.
In sum, the preparation method with the LED vertical chip of current blocking structures of the present invention is fallen by the region etch that ITO transparency conducting layer is corresponding with the upright projection of N electrode, the high contact resistance region (Schottky contacts) between P type GaN layer and P electrode layer is utilized to form current blocking structures, in the LED vertical chip obtained, Injection Current can effectively be expanded, alleviate the crowded of N electrode low-side current, improve being uniformly distributed of electric current, thus improve the luminescent properties of vertical structure LED.Compare traditional current blocking technique, method technique of the present invention is simple, and cost is low, and production capacity is high, and the LED obtained is less likely to occur to peel off, thus improves the reliability of vertical chip.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (11)
1. there is a preparation method for the LED vertical chip of current blocking structures, it is characterized in that, at least comprise the following steps:
One substrate is provided, grows involuntary doped gan layer, N-type GaN layer, multiple quantum well layer and P type GaN layer over the substrate successively;
ITO transparency conducting layer is formed on described P type GaN layer surface;
The etching away regions corresponding with the upright projection of the follow-up N electrode that will be formed by described ITO transparency conducting layer, obtains the opening that exposes described P type GaN layer in described ITO transparency conducting layer;
P electrode layer is formed further in described ITO layer at transparent layer, described P electrode layer is filled into described opening and contacts with the P type GaN layer that described opening exposes, and the contact area of the P type GaN layer that described P electrode layer and described opening expose is as current blocking structures;
At described P electrode layer surface bond one substrate;
Remove described substrate and described involuntary doped gan layer successively, and form the Cutting Road running through described N-type GaN layer, multiple quantum well layer and P type GaN layer from top to bottom, obtain MESA table top;
N electrode is formed on described N-type GaN layer surface.
2. the preparation method with the LED vertical chip of current blocking structures according to claim 1, is characterized in that: before described N-type GaN layer surface forms described N electrode, by described N-type GaN layer surface coarsening.
3. the preparation method with the LED vertical chip of current blocking structures according to claim 1, it is characterized in that: form reflection electrode layer and bonding metal layer successively in described ITO layer at transparent layer, described reflection electrode layer and bonding metal layer are jointly as described P electrode layer.
4. the preparation method with the LED vertical chip of current blocking structures according to claim 1, is characterized in that: be ohmic contact between described ITO transparency conducting layer and described P type GaN layer and described P electrode layer; Be Schottky contacts between the P type GaN layer that described P electrode layer and described open bottom expose.
5. the preparation method with the LED vertical chip of current blocking structures according to claim 1, is characterized in that: utilize wet processing to etch and obtain described opening.
6. the preparation method with the LED vertical chip of current blocking structures according to claim 1, is characterized in that: adopt laser lift-off to remove described substrate, adopts ICP method to remove described involuntary doped gan layer.
7. there is a LED vertical chip for current blocking structures, comprise substrate and be formed at P electrode layer, ITO transparency conducting layer, P type GaN layer, multiple quantum well layer, N-type GaN layer and the N electrode on described substrate from bottom to top successively, it is characterized in that:
Have an opening in described ITO transparency conducting layer, the position of described opening is corresponding with the upright projection position of described N electrode on described ITO transparency conducting layer;
Described opening exposes described P type GaN layer, and described P electrode layer is filled into described opening and contacts with the P type GaN layer that described opening exposes; The contact area of the P type GaN layer that described P electrode layer and described opening expose is as current blocking structures.
8. the LED vertical chip with current blocking structures according to claim 7, is characterized in that: be ohmic contact between described ITO transparency conducting layer and described P type GaN layer and described P electrode layer; Be Schottky contacts between the P type GaN layer that described P electrode layer and described open bottom expose.
9. the LED vertical chip with current blocking structures according to claim 7, is characterized in that: described substrate is Si sheet, W/Cu substrate or Mo/Cu substrate.
10. the LED vertical chip with current blocking structures according to claim 7, it is characterized in that: described P electrode layer comprises reflection electrode layer and bonding metal layer, wherein, described reflection electrode layer is connected with described ITO transparency conducting layer, and described bonding metal layer is connected with described substrate.
11. LED vertical chip with current blocking structures according to claim 7, is characterized in that: described N-type GaN layer surface is through roughening treatment.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105609596A (en) * | 2015-09-11 | 2016-05-25 | 映瑞光电科技(上海)有限公司 | LED vertical chip possessing current blocking structure and manufacturing method thereof |
| CN107799635A (en) * | 2017-10-27 | 2018-03-13 | 厦门乾照光电股份有限公司 | A kind of LED chip and its manufacture method |
| CN108269897A (en) * | 2018-01-24 | 2018-07-10 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and preparation method thereof |
| CN108281516A (en) * | 2018-01-22 | 2018-07-13 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and preparation method thereof |
| CN109768137A (en) * | 2018-12-29 | 2019-05-17 | 晶能光电（江西）有限公司 | Light emitting diode (LED) chip with vertical structure and preparation method thereof |
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| CN102097569A (en) * | 2009-12-09 | 2011-06-15 | Lg伊诺特有限公司 | Light emitting device, light emitting device manufacturing method, light emitting package, and lighting system |
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