CN102473640A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN102473640A
CN102473640A CN2011800030798A CN201180003079A CN102473640A CN 102473640 A CN102473640 A CN 102473640A CN 2011800030798 A CN2011800030798 A CN 2011800030798A CN 201180003079 A CN201180003079 A CN 201180003079A CN 102473640 A CN102473640 A CN 102473640A
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China
Prior art keywords
semiconductor substrate
layer
insulation division
electrode
semiconductor device
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Pending
Application number
CN2011800030798A
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English (en)
Chinese (zh)
Inventor
泷井谦昌
甲斐隆行
齐藤太志郎
大熊崇文
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN102473640A publication Critical patent/CN102473640A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01955—Changing the shapes of bond pads by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN2011800030798A 2010-05-31 2011-03-28 半导体装置及其制造方法 Pending CN102473640A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010124013A JP5352534B2 (ja) 2010-05-31 2010-05-31 半導体装置及びその製造方法
JP2010-124013 2010-05-31
PCT/JP2011/001825 WO2011151961A1 (ja) 2010-05-31 2011-03-28 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
CN102473640A true CN102473640A (zh) 2012-05-23

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Family Applications (1)

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CN2011800030798A Pending CN102473640A (zh) 2010-05-31 2011-03-28 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US20120119384A1 (https=)
JP (1) JP5352534B2 (https=)
CN (1) CN102473640A (https=)
WO (1) WO2011151961A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367139A (zh) * 2013-07-11 2013-10-23 华进半导体封装先导技术研发中心有限公司 一种tsv孔底部介质层刻蚀方法
CN108022966A (zh) * 2016-11-01 2018-05-11 日月光半导体制造股份有限公司 半导体晶片及半导体封装
CN112997304A (zh) * 2018-12-18 2021-06-18 索尼半导体解决方案公司 半导体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148202B (zh) * 2010-02-09 2016-06-08 精材科技股份有限公司 晶片封装体及其形成方法
US9437783B2 (en) 2012-05-08 2016-09-06 Cree, Inc. Light emitting diode (LED) contact structures and process for fabricating the same
MA36343B1 (fr) * 2013-10-14 2016-04-29 Nemotek Technologies Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d
JP2016174101A (ja) 2015-03-17 2016-09-29 株式会社東芝 半導体装置およびその製造方法
KR102493464B1 (ko) 2018-07-19 2023-01-30 삼성전자 주식회사 집적회로 장치 및 이의 제조 방법
JP7067448B2 (ja) * 2018-12-10 2022-05-16 三菱電機株式会社 半導体装置の製造方法、半導体装置
CN112185984B (zh) * 2020-09-17 2022-07-12 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板

Citations (6)

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JPS5538061A (en) * 1978-09-11 1980-03-17 Fujitsu Ltd Bridging wiring method
JP2003198122A (ja) * 2001-12-28 2003-07-11 Kanegafuchi Chem Ind Co Ltd 配線板の製造方法
CN1755916A (zh) * 2004-09-29 2006-04-05 三洋电机株式会社 半导体装置及其制造方法
CN1779962A (zh) * 2004-10-26 2006-05-31 三洋电机株式会社 半导体装置及其制造方法
US20070069364A1 (en) * 2005-09-29 2007-03-29 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090284631A1 (en) * 2007-12-27 2009-11-19 Mie Matsuo Semiconductor package and camera module

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WO2004064159A1 (ja) * 2003-01-15 2004-07-29 Fujitsu Limited 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法
JP4331033B2 (ja) * 2004-03-29 2009-09-16 浜松ホトニクス株式会社 半導体光検出素子及びその製造方法
JP5036127B2 (ja) * 2004-10-26 2012-09-26 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
JP5021992B2 (ja) * 2005-09-29 2012-09-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5596919B2 (ja) * 2008-11-26 2014-09-24 キヤノン株式会社 半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538061A (en) * 1978-09-11 1980-03-17 Fujitsu Ltd Bridging wiring method
JP2003198122A (ja) * 2001-12-28 2003-07-11 Kanegafuchi Chem Ind Co Ltd 配線板の製造方法
CN1755916A (zh) * 2004-09-29 2006-04-05 三洋电机株式会社 半导体装置及其制造方法
CN1779962A (zh) * 2004-10-26 2006-05-31 三洋电机株式会社 半导体装置及其制造方法
US20070069364A1 (en) * 2005-09-29 2007-03-29 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090284631A1 (en) * 2007-12-27 2009-11-19 Mie Matsuo Semiconductor package and camera module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367139A (zh) * 2013-07-11 2013-10-23 华进半导体封装先导技术研发中心有限公司 一种tsv孔底部介质层刻蚀方法
CN108022966A (zh) * 2016-11-01 2018-05-11 日月光半导体制造股份有限公司 半导体晶片及半导体封装
CN112997304A (zh) * 2018-12-18 2021-06-18 索尼半导体解决方案公司 半导体装置
US12154874B2 (en) 2018-12-18 2024-11-26 Sony Semiconductor Solutions Corporation Semiconductor device

Also Published As

Publication number Publication date
WO2011151961A1 (ja) 2011-12-08
US20120119384A1 (en) 2012-05-17
JP2011249718A (ja) 2011-12-08
JP5352534B2 (ja) 2013-11-27

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Application publication date: 20120523