CN102468274B - Shadow effect analyzing structure, and forming method and analyzing method thereof - Google Patents
Shadow effect analyzing structure, and forming method and analyzing method thereof Download PDFInfo
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- CN102468274B CN102468274B CN 201010546311 CN201010546311A CN102468274B CN 102468274 B CN102468274 B CN 102468274B CN 201010546311 CN201010546311 CN 201010546311 CN 201010546311 A CN201010546311 A CN 201010546311A CN 102468274 B CN102468274 B CN 102468274B
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Abstract
The invention provides a shadow effect analyzing structure. The shadow effect analyzing structure comprises a test substrate and at least two photoresist columns, wherein the test substrate comprises an ion implantation area and a non-ion implantation area; and the two photoresist columns are arranged on the surface of the non-ion implantation area positioned on the test substrate and have different heights. The invention also provides a forming method and an analyzing method of the shadow effect analyzing structure. By the structure and the analyzing method thereof, the shadow effect analyzing cost is reduced, the shadow effect analyzing efficiency is improved, the height of a photoresist layer formed through ion implantation can be also optimized, and the shadow effect is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of shadow effect analytical structure, its formation method and its analytical method.
Background technology
Method at the semiconductor surface impurity generally realizes by thermal diffusion or Implantation.Owing to there is no sideways diffusion in ion implantation technology, and the implantation temperature of Implantation is near room temperature, easily position and the quantity of adulterating in wafer carried out good control, so doping process adopts Implantation to realize mostly.
With reference to figure 1, Fig. 1 is the schematic diagram that the prior art intermediate ion injects, such as when the bag-shaped doped region 1 in nmos area 4 is carried out Implantation (as shown in the direction of arrow in Fig. 1), in order to prevent Implantation PMOS district 5, need to form one deck photoresist layer 3 and come blocks ions to inject on 5 surfaces, PMOS district.Owing to usually all needing to tilt certain angle to carry out when bag-shaped doped region 1 carries out Implantation, and existing manufacture method, photoresist layer 3 is by after exposing and developing, the photoresist layer 3 that forms all presents column structure, its side is vertical side, has limited the range of tilt angles of Implantation.Therefore, its shadow effect (shadow effect) is difficult to avoid, and originally needing to cause the zone 2 of Implantation can't ion.
In order to overcome above-mentioned shadow effect, the method that usually adopts has by reducing the height of photoresist layer 3, to obtain larger ion incidence angle, reduces shadow effect.
But, along with the characteristic size of device is further dwindled, distance between NMOS and PMOS district 5 is shortened also, photoresist layer 3 width and highly also thereupon dwindling, the height that further reduces photoresist layer 3 will cause the ion of high strength and high concentration to punch photoresist layer entering PMOS district 5, perhaps enter isolated area 2, affect the isolation effect of isolated area 2.
So when device is carried out Implantation, assessment shadow effect and obtain that the photoresist layer height is extremely important accurately.
During for accurate Implantation, the height of required photoresist layer, at first need to carry out the photoresist layer high measure on test substrate.Its detailed process is: at first a collection of test substrate is provided, and described test substrate and regular are formed with identical device architecture and distribution, include ion implanted region and nonionic injection region on described test substrate; The corresponding photoresist post that forms respectively differing heights on the nonionic injection region of different test substrate, wherein the photoresist post height on the monolithic test substrate is identical; The ion beam that use has the incident of certain angle of inclination carries out Implantation to the ion implanted region on test substrate; Carry out the follow-up technique that routinizes, form the MOS transistor of some numbers on described test substrate; By the electric property of the MOS transistor that forms in the analytical test substrate, comprise threshold voltage and leakage current at last; Predefined level threshold value voltage and standard leakage current are provided, and the threshold voltage of acquisition and the threshold voltage of standard are compared, leakage current value and the standard leakage current that obtains compared the shadow effect that the photoresist layer of minute factorial differing heights causes.
But the inventor finds, above-mentioned analytical method need to form corresponding differing heights photoresist layer on different test substrate, the primary ions injection process can only photoresist post height of correspondence analysis, test process is complicated, need a large amount of test substrate quantity, analysis cost is higher, and analysis efficiency is lower.
Summary of the invention
The problem that the present invention solves is to provide a kind of shadow effect analytical structure, its formation method and its analytical method, to reduce the shadow effect analysis cost, improve the analysis efficiency of shadow effect, the photoresist layer height of the optimization when further also obtaining Implantation improves shadow effect.
For addressing the above problem, the invention provides a kind of shadow effect analytical structure, comprising: test substrate, described test substrate comprise ion implanted region and nonionic injection region, and are positioned at least two photoresist posts on the surface, nonionic injection region of described test substrate; Wherein have at least the height of two photoresist posts not identical.
Optionally, described photoresist post height successively decreases successively to both sides with described test substrate center line.
Optionally, the height with center line described photoresist post to both sides of described test substrate increases progressively successively.
The present invention also provides a kind of formation method of shadow effect analytical structure, comprise: test substrate is provided, described test substrate comprises ion implanted region and nonionic injection region, forms photoresist layer on described test substrate, and described photoresist layer has nonreentrant surface or recessed surface; Described photoresist layer is carried out patterned process, form at least two photoresist posts on the surface, nonionic injection region of described test substrate, and have at least the height of two photoresist posts not identical.
Optionally, if described photoresist layer is nonreentrant surface, successively decrease successively with the height of described test substrate center line to both sides photoresist post.
Optionally, if described photoresist layer is recessed surface, increase progressively successively with the height of described test substrate center line to both sides photoresist post.
Optionally, form photoresist layer and comprise on described test substrate: shoot out photoresist by shower nozzle to described test substrate, test substrate rotation simultaneously is so that photoresist is formed on the full wafer test substrate.
Optionally, when forming photoresist layer, by controlling the speed of rotation of test substrate, form the photoresist layer of different surfaces shape on described test substrate.
Optionally, when the speed of rotation scope of described test substrate was 0RPM～3000RPM, described photoresist layer had nonreentrant surface.
Optionally, when the speed of rotation scope of described test substrate was 3000RPM～6000RPM, described photoresist layer had recessed surface.
The present invention provides again a kind of analytical method of described shadow effect analytical structure, comprising: the shadow effect analytical structure is provided, is formed with the photoresist post of some numbers on described shadow effect analytical structure, have at least the height of two photoresist posts not identical; Use ion beam to carry out Implantation to the ion implanted region on test substrate and form ion doped region; Carry out the follow-up technique that routinizes, form the MOS transistor of some numbers on described test substrate;
Obtain threshold voltage and the leakage current of MOS transistor;
The level threshold value that sets in advance voltage range is provided, and standard leakage current scope;
The threshold voltage and the level threshold value voltage range that obtain are compared, to obtain simultaneously leakage current and standard leakage current scope relatively, if the threshold voltage value of described acquisition falls into the level threshold value voltage range, the leakage current value of simultaneously described acquisition falls into standard leakage current value scope, and the shadow effect that causes because of the photoresist post of corresponding MOS transistor is in the tolerable scope.
Compared with prior art, technique scheme has the following advantages:
The present invention in order to cause shadow effect at the photoresist post of a test substrate test differing heights, has reduced the analysis cost of shadow effect by be formed with the photoresist post of differing heights on a test substrate, improves analysis efficiency;
Further, the speed of rotation of test substrate when the present invention shoots out photoresist by control, have the photoresist layer of recessed surface or nonreentrant surface to form on test substrate, and described photoresist layer is carried out patterning, form the photoresist post with differing heights distribution; Can cause shadow effect at the photoresist post of a test substrate test differing heights;
At last, inject by described shadow effect analytical structure being carried out primary ions, can obtain the shadow effect of the photoresist post of differing heights, and analyze the variation of the electric property that different shadow effects causes, reduce the analysis cost of shadow effect, improved analysis efficiency.
Description of drawings
Fig. 1 is semiconductor device Implantation schematic diagram in existing technique.
The formation method flow schematic diagram of the shadow effect analytical structure of Fig. 2 one embodiment of the invention.
Fig. 3, Fig. 4, Fig. 5 and Fig. 7 are the formation method structural representations of the shadow effect analytical structure of one embodiment of the invention.
Fig. 6 is photoresist layer shape and the test substrate speed of rotation distribution map of one embodiment of the invention.
Fig. 8 is the analytical method schematic diagram of the shadow effect analytical structure of one embodiment of the invention.
Embodiment
Existing shadow effect analytical structure and analytical method thereof, need to form corresponding differing heights photoresist layer on different test substrate, the primary ions injection process can only photoresist post height of correspondence analysis, test process is complicated, need a large amount of test substrate quantity, analysis cost is higher, and analysis efficiency is lower.
For addressing the above problem, the invention provides a kind of shadow effect analytical structure, reduce the analysis cost of shadow effect, improve the analysis efficiency of shadow effect.Described shadow effect analytical structure comprises: test substrate, described test substrate comprise ion implanted region and nonionic injection region, and are positioned at least two photoresist posts on the nonionic injection region of described test substrate; Wherein, have at least the height of two photoresist posts not identical.
As an embodiment, the photoresist post on described test substrate can be following distribution: described photoresist post height successively decreases successively to both sides with described test substrate center line; Perhaps the height with described test substrate center line described photoresist post to both sides increases progressively successively.
The present invention also provides a kind of formation method of shadow effect analytical structure, comprise: test substrate is provided, described test substrate comprises ion implanted region and nonionic injection region, forms photoresist layer on described test substrate, and described photoresist layer has nonreentrant surface or recessed surface; Described photoresist layer is carried out patterned process, form the photoresist post of some numbers on the surface, nonionic injection region of described test substrate, have at least the height of two photoresist posts not identical.
The present invention in order to cause shadow effect at the photoresist post of a test substrate test differing heights, has reduced the analysis cost of shadow effect by be formed with the photoresist post of differing heights on a test substrate, improves analysis efficiency; Further, the speed of rotation of test substrate when the present invention shoots out photoresist by control, have the photoresist layer of recessed surface or nonreentrant surface to form on test substrate, and described photoresist layer is carried out patterning, form the photoresist post with differing heights distribution; Can cause shadow effect at the photoresist post of a test substrate test differing heights.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 2 is the formation method flow diagram of the shadow effect analytical structure of one embodiment of the invention, comprising:
At first execution in step S1 provides test substrate, and described test substrate includes ion implanted region and nonionic injection region.
Execution in step S2 shoots out photoresist by shower nozzle, and the rotary test substrate, form photoresist layer on the full wafer test substrate simultaneously, and by controlling the rotary speed of test substrate, makes described photoresist layer have recessed surface or nonreentrant surface.
Execution in step S3 exposes to described photoresist layer, forms the photoresist post of some numbers on the nonionic injection region of described test substrate, and has at least two photoresist posts to have different height to distribute.
Fig. 3 to Fig. 8 is the generalized section of one embodiment of the invention shadow effect analytical method.
At first as shown in Figure 3, provide test substrate 100, need to form the MOS transistor of some numbers on described test substrate 100.Wherein, described test substrate 100 includes ion implanted region 120 and nonionic injection region 130, and described nonionic injection region 130 does not need to carry out the electricity device district of Implantation for the isolated area of MOS transistor and grid structure or other.Described ion implanted region 120 is source region and the drain region of MOS transistor.Described test substrate 100 has been completed the technique of isolated area and grid structure, and subsequent technique need to carry out Implantation to described ion implanted region 120.
Be illustrated in figure 4 as a device architecture in the present embodiment, comprise nmos pass transistor district 11, PMOS transistor area 12 and be used for the isolated area 13 of isolation nmos pass transistor district and PMOS transistor area.In follow-up ion implantation process, source region in described nmos pass transistor district 11 and drain region 011 are ion implanted region, the source region of described PMOS transistor area 12 and drain region 012 are the nonionic injection region, follow-uply need to form photoresist layer so that active area 012 is blocked on described PMOS transistor area 12.
As shown in Figure 5, form one deck photoresist layer 110 on described test substrate 100, described photoresist layer 110 has nonreentrant surface or recessed surface, originally illustrates the photoresist layer 110 of nonreentrant surface.The formation method of described photoresist layer 110 is spin-coating method, comprising: at first shoot out photoresist to form photoresist layer 110 by shower nozzle.Rotary test substrate 100 simultaneously is so that described photoresist is formed on the test substrate 100 of full wafer.
When the present invention shoots out photoresist with formation photoresist layer 110 at shower nozzle, by controlling the spin coating speed of test substrate, to form the photoresist layer on difformity surface.As an embodiment, when the speed of rotation scope of described test substrate was 0RPM～3000RPM, described photoresist layer had nonreentrant surface; When the speed of rotation scope of described test substrate was 3000RPM～6000RPM, described photoresist layer had recessed surface.
Further, if described photoresist layer is nonreentrant surface, the height with described test substrate 100 center lines 001 described photoresist post to both sides successively decreases successively; If described photoresist layer is recessed surface, the height with described test substrate 100 center lines 001 described photoresist post to both sides increases progressively successively.
As an embodiment, be illustrated in figure 6 as photoresist layer shape and the test substrate speed of rotation distribution map of an embodiment of invention, wherein the speed of rotation of the test substrate of each lines representative is respectively: the speed of rotation of lines 1 test substrate is 3000rpm; The speed of rotation of lines 2 test substrate is 3500rpm, the speed of rotation of lines 3 test substrate is 4000rmp, the speed of rotation of lines 4 test substrate is 4500rpm, and the speed of rotation of lines 5 test substrate is 5000rpm, and the speed of rotation of lines 6 test substrate is 5500rpm.
Can be found by upper table: when the speed of rotation of test substrate during less than 4500RPM, described photoresist layer has nonreentrant surface, and along with the reduction (4500RPM drops to 3000RPM by spin coating speed) of the speed of rotation, the convex curvature on described photoresist layer surface is larger; During greater than 4500RPM, described photoresist layer has recessed surface when the speed of rotation of test substrate, and along with the raising (4500RPM is increased to 6000RPM by the speed of rotation) of speed, the recessed curvature on described recessed surface is larger.
With reference to figure 5 and Fig. 6, the speed of rotation of test substrate described in the present embodiment 100 is 3500RPM, the height of described photoresist layer distributes and is specially: take the former heart of described test substrate 100 as the nonreentrant surface peak, and descend gradually along the height of described test substrate 100 center lines described photoresist layer 110 to both sides.
At first need to prove, according to the difference of photoresist layer kind and character, the spin coating speed of the test substrate of photoresist layer to be formed is also different, therefore can be according to the needs of concrete application, select the photoresist layer of respective classes, thereby determine the spin coating speed of concrete test substrate.
As shown in Figure 7, described photoresist layer 110 is carried out patterned process, form the photoresist post 111 of some numbers on the ion implanted region 120 of test substrate, the part of not blocked by described photoresist post 111 is ion implanted region 130.The number of the photoresist post that originally illustrates is 5, and the number of described ion implanted region is 4.
By the formation method of above-mentioned shadow effect analytical structure, can obtain shadow effect analytical structure provided by the present invention as shown in Figure 7.
The present invention provides again a kind of analytical method of described shadow effect analytical structure, comprising: the shadow effect analytical structure is provided, is formed with at least two photoresist posts on described shadow effect analytical structure, and have at least the height of two photoresist posts not identical; Use ion beam to carry out Implantation to the ion implanted region on test substrate and form ion doped region; Carry out the follow-up technique that routinizes, form the MOS transistor of some numbers on described test substrate; Obtain threshold voltage and the leakage current of MOS transistor; The level threshold value that sets in advance voltage range is provided, and standard leakage current scope; The threshold voltage and the level threshold value voltage range that obtain are compared, to obtain simultaneously leakage current and standard leakage current scope relatively, if the threshold voltage value of described acquisition falls into the level threshold value voltage range, the leakage current value of simultaneously described acquisition falls into standard leakage current value scope, and the shadow effect that causes because of the photoresist post of corresponding MOS transistor is in the tolerable scope.
Below in conjunction with accompanying drawing, the analytical method of shadow effect analytical structure of the present invention is described.
At first, as shown in Figure 7, provide shade failure analysis structure, comprising: test substrate 100, described test substrate 100 comprise ion implanted region 120 and nonionic injection region 130, and are positioned at the photoresist post 111 on the nonionic injection region 130 of described test substrate; Wherein, described photoresist post 111 has 5, successively decreases successively with the height of described test substrate 100 center lines described photoresist post 111 to both sides.
Further, also provide regular, described test substrate 100 is formed with identical device architecture and distribution (not shown) with regular.Namely at first carry out the shadow effect analysis on described test substrate 100, obtain the height of the photoresist post of shadow effect in the tolerable scope, then form corresponding photoresist post height on described regular.
As shown in Figure 8, adopt the ion implanted region 120 of 140 pairs of described test substrate 100 of ion beam to carry out Implantation, by the photoresist post 111 of differing heights, described ion implanted region 120 is carried out Implantation particularly.In prior art, be difficult to obtain the ion beam 140 on vertical described ion implanted region 120 surfaces, so described ion beam 140 has certain angle of inclination with photoresist post 110.
Continuation is with reference to figure 8, because described photoresist post 110 is for the blocking of ion beam 140, and described ion beam 140 has certain angle of inclination, is formed with the shadow region of part on described ion implanted region 120 by the ion beam 140 of photoresist post 110.In same Implantation environment, the height of described photoresist post 110 is higher, and the area in described shadow region is larger.The area in different shadow regions 130 will cause different shadow effects.
Take semiconductor structure shown in Figure 4 as example, form photoresist post (not shown) on nonionic injection region 012, if described photoresist post height is excessive, the shadow region of causing because of described photoresist post is larger, the area of the isolated area 13 that described shadow region covers is larger, if the zone that described shadow region covers is greater than described isolated area 13, and then be coated with the ion implanted region 011 of part, can blocks ions be injected into described ion implanted region 011; Otherwise, if the insufficient area that described shadow region covers covers described isolated area 13 or is easily punctured by ion beam because photoresist post height is too little, can cause described isolated area 13 also Implantation will be arranged, have influence on the isolation effect of isolated area 13, further affect the leakage current value of device architecture.So during Implantation, the height that accurately is used for the photoresist layer that blocks ions injects is extremely important.
After carrying out Implantation, described test substrate is carried out the follow-up technique that routinizes, form the MOS transistor of some numbers on described test substrate 100.In the present embodiment, the part source region of described MOS transistor and drain region are ion implanted region 120.
Then, obtain threshold voltage and the leakage current value of above-mentioned each MOS transistor, wherein, described threshold voltage and leakage current value are the normal definition of using of the art, are the raceway groove cut-in voltage as threshold voltage, and leakage current is the leakage current value of raceway groove.
Predefined level threshold value voltage range and leakage current scope are provided, if in the data of above-mentioned acquisition, threshold voltage falls into described normalization voltage range, and described leakage current falls into described standard leakage current scope, described MOS transistor is qualified MOS transistor, corresponding, described MOS transistor is when Implantation, the shadow effect that causes because of the photoresist height is also in the tolerable scope, and namely described photoresist height is in the tolerable scope.wherein, described tolerable scope is specially: in forming the MOS transistor process, when carrying out Implantation by the photoresist post, the shadow region of blocking generation because of the photoresist post all can appear, the size in described shadow region is determined by the height of photoresist post, and the large young pathbreaker in described shadow region affects the electric property of MOS transistor, the general electric property deviation range of specifying acceptable qualified MOS transistor to cause because of shadow effect of needing on technique, it is the tolerable scope of shadow effect, in described tolerable scope, described MOS transistor is acceptable on production line.
Such as the threshold voltage of the MOS transistor that forms by measurement in the present invention and the deviation range of leakage current electric property, the shadow effect that measurement causes because of the photoresist post of different-thickness, if the electric property of one of them or several MOS transistor is in level threshold value voltage range and leakage current scope, accordingly, the shadow effect that causes because of the photoresist post in described MOS transistor is also in the tolerable scope.
As shown in Figure 8, by above-mentioned analysis, in the present embodiment, the height of the photoresist post shown in photoresist post label a is in the tolerable scope.As other embodiment, the height of plural photoresist post can be arranged in the tolerable scope on a test substrate.
Further, by above-mentioned analysis, can form the photoresist post of above-mentioned shadow effect in the tolerable scope on regular, and adopt described photoresist post, the ion implanted region of described regular is being carried out Implantation.Just be not described in detail herein.
In above embodiment, when shooing out photoresist, control the speed of rotation of test substrate, the surface of the photoresist layer that obtains is nonreentrant surface.As other embodiment, can also be by further improving the speed of rotation of described test substrate, can obtain the photoresist layer on recessed surface, the photoresist post that further obtains the test substrate center is minimum altitude, the distribution of the photoresist post that successively decreases along the center line of test substrate 100 to the both sides height.Just be not described in detail herein.
Further, because form the test substrate speed of rotation of nonreentrant surface less than the test substrate speed of rotation on the recessed surface of formation.And because the formation process of the less speed of rotation is more easy to control, thus in actual process, with the photoresist layer that forms nonreentrant surface for better.
Compared with prior art, technique scheme has the following advantages:
The present invention in order to cause shadow effect at the photoresist post of a test substrate test differing heights, has reduced the analysis cost of shadow effect by be formed with the photoresist post of differing heights on a test substrate, improves analysis efficiency;
Further, the speed of rotation of test substrate when the present invention shoots out photoresist by control, have the photoresist layer of recessed surface or nonreentrant surface to form on test substrate, and described photoresist layer is carried out patterning, form the photoresist post with differing heights distribution; Can cause shadow effect at the photoresist post of a test substrate test differing heights;
At last, inject by described shadow effect analytical structure being carried out primary ions, can obtain the shadow effect of the photoresist post of differing heights, and analyze the variation of the electric property that different shadow effects causes, reduce the analysis cost of shadow effect, improved analysis efficiency.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the analytical method of a shadow effect analytical structure, is characterized in that, comprising:
The shadow effect analytical structure is provided, described shadow effect analytical structure comprises: test substrate, described test substrate comprises ion implanted region and nonionic injection region, and be positioned at least two photoresist posts on the surface, nonionic injection region of described test substrate, and have at least the height of two photoresist posts not identical; Use ion beam to carry out Implantation to the ion implanted region on test substrate and form ion doped region; Carry out the follow-up technique that routinizes, form the MOS transistor of some numbers on described test substrate;
Obtain threshold voltage and the leakage current of MOS transistor;
The level threshold value that sets in advance voltage range is provided, and standard leakage current scope;
The threshold voltage and the level threshold value voltage range that obtain are compared, to obtain simultaneously leakage current and standard leakage current scope relatively, if the threshold voltage value of described acquisition falls into the level threshold value voltage range, the leakage current value of simultaneously described acquisition falls into standard leakage current value scope, and the shadow effect that causes because of the photoresist post of corresponding MOS transistor is in the tolerable scope.
2. the analytical method of shadow effect analytical structure according to claim 1, is characterized in that, described photoresist post height successively decreases successively to both sides with described test substrate center line.
3. the analytical method of shadow effect analytical structure according to claim 1, is characterized in that, increases progressively successively with the height of described test substrate center line described photoresist post to both sides.
4. the analytical method of shadow effect analytical structure according to claim 1, it is characterized in that, the formation method of described shadow effect analytical structure comprises: test substrate is provided, described test substrate comprises ion implanted region and nonionic injection region, form photoresist layer on described test substrate, described photoresist layer has nonreentrant surface or recessed surface; Described photoresist layer is carried out patterned process, form the photoresist post of some numbers on the surface, nonionic injection region of described test substrate, have at least the height of two photoresist posts not identical.
5. the analytical method of shadow effect analytical structure according to claim 4, is characterized in that, if described photoresist layer is nonreentrant surface, the height with described test substrate center line described photoresist post to both sides successively decreases successively.
6. the analytical method of shadow effect analytical structure according to claim 4, is characterized in that, if described photoresist layer is recessed surface, the height with described test substrate center line described photoresist post to both sides increases progressively successively.
7. the analytical method of shadow effect analytical structure according to claim 4, it is characterized in that, forming photoresist layer on described test substrate comprises: shoot out photoresist by shower nozzle to described test substrate, test substrate rotation simultaneously is so that photoresist is formed on the full wafer test substrate.
8. the analytical method of shadow effect analytical structure according to claim 7, is characterized in that, when forming photoresist layer, by controlling the speed of rotation of test substrate, forms difform photoresist layer on described test substrate.
9. the analytical method of shadow effect analytical structure according to claim 8, is characterized in that, when the speed of rotation scope of described test substrate was 0RPM～3000RPM, described photoresist layer had nonreentrant surface.
10. the analytical method of shadow effect analytical structure according to claim 8, is characterized in that, when the speed of rotation scope of described test substrate was 3000RPM～6000RPM, described photoresist layer had recessed surface.
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| CN103488045B (en) * | 2012-06-14 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of restraining barrier method for making of ion implantation |
| CN107134416A (en) * | 2016-02-26 | 2017-09-05 | 北大方正集团有限公司 | Shadow effect analytical structure and preparation method thereof and analysis method |
| CN106024601B (en) * | 2016-05-16 | 2018-11-09 | 上海华力微电子有限公司 | A kind of forming method of ion implanted layer shadow effect analysis structure |
| CN111463171B (en) * | 2020-04-10 | 2022-11-29 | 上海华力集成电路制造有限公司 | Method for manufacturing pattern structure |
| CN113097058A (en) * | 2021-06-09 | 2021-07-09 | 晶芯成(北京)科技有限公司 | Semiconductor device and method for manufacturing the same |
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| US6828202B1 (en) * | 2002-10-01 | 2004-12-07 | T-Ram, Inc. | Semiconductor region self-aligned with ion implant shadowing |
| CN101465272A (en) * | 2007-12-17 | 2009-06-24 | 中芯国际集成电路制造(上海)有限公司 | Method for optimizing semiconductor device ion injection technology |
| CN101640173A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Light resistance structure suitable for ion injecting technology |
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|---|---|---|---|---|
| US6828202B1 (en) * | 2002-10-01 | 2004-12-07 | T-Ram, Inc. | Semiconductor region self-aligned with ion implant shadowing |
| CN101465272A (en) * | 2007-12-17 | 2009-06-24 | 中芯国际集成电路制造(上海)有限公司 | Method for optimizing semiconductor device ion injection technology |
| CN101640173A (en) * | 2009-06-09 | 2010-02-03 | 上海宏力半导体制造有限公司 | Light resistance structure suitable for ion injecting technology |
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