CN1476064A

CN1476064A - Method of forming light doped drain electrode using inverse taper grid structure

Info

Publication number: CN1476064A
Application number: CNA021305439A
Authority: CN
Inventors: 蔡孟锦; 金平中
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2002-08-14
Filing date: 2002-08-14
Publication date: 2004-02-18
Anticipated expiration: 2022-08-14
Also published as: CN1265445C

Abstract

In the method, a counter-trapeziodal structure with wide top edge and narrow bottom edge is formed by utilizing etching technique to etch grid stack structure after a gate oxide layer and grid stack structure of polysilicon layer are formed at the surface of a substrate. A vertical implanting step of shallow ion doping is carried on by utilizing the grid stack structure as shield to form a shallow ion doping region in the substrate at two sides of the grid stack stracture so the shallow ion doping region can be diffused horizontally to substrate under bottom periphery of the grid stack structure to form lightly doped drain structure in the following heat preparation process.

Description

Utilize inverse taper grid structure to form the method for lightly doped drain

[technical field]

The present invention is relevant a kind of manufacturing method of semiconductor module, and particularly relevant for a kind of grid structure that forms the inverse taper shape that utilizes, (lightly doped drain, method LDD) is with accurate control channel length to form lightly doped drain.

[background technology]

Under the situation that the semiconductor subassembly size is dwindled, channel length is also dwindled relatively, the problem of short channel effect just can take place this moment, the method of the thermoelectronic effect that known solution short channel effect is caused is shown in Figure 1A, in substrate 10, form the stack structure of gate oxide 12 and polysilicon gate 14, with this polysilicon gate 14 is shielding, carries out the shallow ion dopping process, to form shallow ion doped region 16.

Then see also Figure 1B, form clearance wall (spacer) 18 in polysilicon gate 14 2 sides, is shielding with this clearance wall 18 with polysilicon gate 14, carry out dark dopping process, to form source electrode 20 and drain electrode 22 structures, wherein the position of not mixed by deep ion in the shallow ion doped region is lightly doped drain lightly doped drain (LDD) 24.

But above-mentioned lightly doped drain (LDD) 24 structures are in follow-up hot processing procedure, influence because of ambient temperature, make that the ion of lightly doped drain (LDD) 24 will horizontal proliferation shown in Fig. 1 C, and invade the length that shortens channel to channel region, this phenomenon can cause the parasitic capacitance short channel effects such as (parasitic capacitor) of leakage current, punch-through effect and gate pole and shallow ion doped region, this short channel effect especially in inferior micron system (less than 0.15 μ m processing procedure) obvious especially.

Therefore it is more and more higher to face the semiconductor subassembly integration, under the more and more little situation of the live width of processing procedure, the horizontal proliferation that hot processing procedure in the manufacture of semiconductor is caused the shallow ion doped region, not only shortened the channel length between source electrode and drain electrode, further more cause short channel effect, influence the stability of assembly, make to be difficult to make less semiconductor subassembly, reduce the qualification rate and the electrical quality of assembly.Therefore, the present invention promptly at above-mentioned disappearance, proposes a kind of method of utilizing inverse taper grid structure to form LDD, effectively to overcome the disappearance of traditional approach.

[summary of the invention]

Main purpose of the present invention is that a kind of method of utilizing inverse taper grid structure to form LDD is being provided, and wherein can accurately control the length of polysilicon gate below channel, and it be can be applicable in time manufacture of semiconductor of micron.

Secondary objective of the present invention is a kind of method of utilizing inverse taper grid structure to form LDD to be provided, to reduce the generation of short channel effect, to promote the characteristic and the electrical quality of assembly.

A further object of the present invention is a kind of method of utilizing inverse taper grid structure to form LDD to be provided, to make when semiconductor subassembly dwindles, still can keep the characteristic of assembly, in order to assembly manufacturing and lifting product percent of pass.

For reaching above-mentioned purpose, the present invention is after a substrate surface is finished the stack structure, utilize etched mode this stack etch structures to be become the aspect of inverse taper, in the substrate of stack structure both sides, form a shallow ion doped region again, when hot fabrication process, this shallow ion doped region is only understood the substrate of horizontal proliferation to the grid root edge, and can not diffuse to the substrate below the stack structure.

Below illustrate in detail by the specific embodiment conjunction with figs., when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.

[description of drawings]

Figure 1A to Fig. 1 C is the generalized section of known making LDD.

Fig. 2 A to Fig. 2 E makes the generalized section of LDD for the present invention.

[embodiment]

The present invention is a preformed stack structure in substrate, and this stack etch structures is become the shape of inverse taper, make it after forming the shallow ion doped region, through hot processing procedure shallow ion doped region only horizontal proliferation to the substrate of the base periphery below of stack structure, carry out that heavy ion mixes and when forming the LDD structure, can guarantee the length of channel, effectively solve short channel effect common in the sub-micrometer semiconductor processing procedure.

Fig. 2 A to Fig. 2 E is respectively each step generalized section that LDD is made in preferred embodiment of the present invention; As shown in the figure, manufacture method of the present invention is to include the following step:

See also Fig. 2 A, at first in substrate 20, form a gate oxide 22; On gate oxide 22, deposit a polysilicon layer 24 then, utilize this polysilicon layer 24 of photolithography techniques etching off, form a stack structure 26 with definition, wherein forming this grid oxic horizon 22 is to utilize thermal oxidation method, forms polysilicon layer 24 and adopts chemical vapour deposition technique (CVD).

Follow this stack structure 26 of etching, these stack structure 26 etchings are formed shape just like the inverse taper shown in Fig. 2 B, the width that is stack structure 26 top margins 261 is wide (represented as dotted line) than base 263, and wherein this engraving method can be the etch process of anisotropic.

See also Fig. 2 C again, think shielding, carry out a shallow ion dopping process, the ion that mixes is implanted substrate 20 (promptly vertical with substrate 20 with ion beam) with the angle at 0 degree angle, in inverse taper stack structure 26 both sides, form a shallow ion doped region 28, because the inverse taper shape of stack structure 26, the scope that makes ion implant only reaches the outer district of vertical line of stack structure 26 top margins 261, and the ion of this shallow ion doped region 28 is phosphonium ion or boron ion.

Carry out a hot processing procedure again, as Rapid Thermal tempering (RTA), make 28 horizontal proliferation of shallow ion doped region, the zone of this horizontal proliferation is with the usefulness as LDD, also can repair by impaired lattice when carrying out ion doping simultaneously, and the ion of implantation is evenly distributed.Shown in Fig. 2 D, the scope of ions diffusion only arrives the position of base 263 peripheries of inverse taper stack structure 26, i.e. the both sides on stack structure 26 bases 263, and can not diffuse to the channel of stack structure 26 belows.

Be shielding with stack structure 26 again, shown in Fig. 2 E, carrying out a heavy ion dopping process perpendicular to the angle of substrate 20, forming source electrode 30 and drain electrode 32 respectively, and the place of not mixed by deep ion in shallow ion doped region 28 is the structure of LDD 34.

Therefore, form the stack structure of an inverse taper among the present invention, can be widely used in the manufacture of semiconductor, utilize etching technique that the stack etch structures is formed the inverse taper aspect of a top margin than bottom side length, promptly reserve the distance that the shallow ion doped region may spread in the subsequent thermal processing procedure, can effectively reduce the shallow ion doped region because of thermogenetic horizontal proliferation, and the generation of shortening channel distance, not only reduced the parasitic capacitance between polysilicon gate and shallow ion doped region, more can prevent the generation that source electrode and drain electrode produce punch-through and leakage current, increase the characteristic and the electrical quality of product by this, to promote the qualification rate of product.

Above-described embodiment only is for technological thought of the present invention and characteristics are described, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.

Claims

1. a method of utilizing inverse taper grid structure to form lightly doped drain is characterized in that comprising the following steps:

One substrate is provided, has formed a stack structure on it, this stack structure includes a gate oxide and polysilicon gate;

This stack structure of etching is to form the top margin inverse taper aspect wide than the base;

With this stack structure is shielding, carries out a shallow ion dopping process, with in this substrate of these stack structure both sides, forms a shallow ion doped region; And

Carry out a hot processing procedure, make this shallow ion doped region horizontal proliferation to this substrate of the base periphery of this stack structure, to form ldd structure.

2. the method for utilizing inverse taper grid structure to form lightly doped drain according to claim 1 is characterized in that this shallow ion implantation is to mix with the angle of vertical this substrate.

3. the method for utilizing inverse taper grid structure to form lightly doped drain according to claim 1 is characterized in that after carrying out this hot fabrication steps, more can carry out deep ion and implant in this substrate, to form source electrode and drain electrode.

4. the method for utilizing inverse taper grid structure to form lightly doped drain according to claim 1 is characterized in that after the step that forms this shallow ion doped region, more can carry out deep ion and implant in this substrate, to form source electrode and drain electrode.

5. the method for utilizing inverse taper grid structure to form lightly doped drain according to claim 1 is characterized in that it is boron implant ion or phosphonium ion that this shallow ion mixes.